From 000c32a56865445b2f92d4fd5d195380492a315f Mon Sep 17 00:00:00 2001 From: Augustin Cavalier Date: Thu, 21 Aug 2025 21:50:36 -0400 Subject: [PATCH] asix88xxx: Import drivers from FreeBSD to replace usb_asix. The homegrown usb_asix was partially based on the upstream FreeBSD driver anyway, and hasn't seen much maintenance in recent years. We might as well replace it with the FreeBSD version. In the process, also add the "axge" driver, supporting the Gigabit version of this hardware. Tested by smrobtzz with the AX88179A: "it seems to work perfectly". Change-Id: I37fdfc2cef6100916d6034817f117286f7f443b2 Reviewed-on: https://review.haiku-os.org/c/haiku/+/9600 Reviewed-by: waddlesplash --- build/jam/images/definitions/minimum | 2 +- .../kernel/drivers/network/ether/Jamfile | 2 +- .../drivers/network/ether/asix88xxx/Jamfile | 32 + .../network/ether/asix88xxx/dev/mii/axphy.c | 174 ++ .../ether/asix88xxx/dev/usb/net/if_axe.c | 1510 +++++++++++++++++ .../ether/asix88xxx/dev/usb/net/if_axereg.h | 363 ++++ .../ether/asix88xxx/dev/usb/net/if_axge.c | 1111 ++++++++++++ .../ether/asix88xxx/dev/usb/net/if_axgereg.h | 216 +++ .../drivers/network/ether/asix88xxx/glue.c | 44 + 9 files changed, 3452 insertions(+), 2 deletions(-) create mode 100644 src/add-ons/kernel/drivers/network/ether/asix88xxx/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/mii/axphy.c create mode 100644 src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axe.c create mode 100644 src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axereg.h create mode 100644 src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axge.c create mode 100644 src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axgereg.h create mode 100644 src/add-ons/kernel/drivers/network/ether/asix88xxx/glue.c diff --git a/build/jam/images/definitions/minimum b/build/jam/images/definitions/minimum index f85d4744cb..e233c0c3df 100644 --- a/build/jam/images/definitions/minimum +++ b/build/jam/images/definitions/minimum @@ -312,6 +312,7 @@ SYSTEM_ADD_ONS_DRIVERS_MIDI = ; SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures x86,x86_64,riscv64 @{ 3com + asix88xxx atheros813x atheros81xx attansic_l1 @@ -339,7 +340,6 @@ SYSTEM_ADD_ONS_DRIVERS_NET = [ FFilterByBuildFeatures etherpci pegasus - usb_asix usb_davicom usb_rndis wb840 diff --git a/src/add-ons/kernel/drivers/network/ether/Jamfile b/src/add-ons/kernel/drivers/network/ether/Jamfile index 1b421ce7bf..1a950b4ecc 100644 --- a/src/add-ons/kernel/drivers/network/ether/Jamfile +++ b/src/add-ons/kernel/drivers/network/ether/Jamfile @@ -4,7 +4,6 @@ SubDir HAIKU_TOP src add-ons kernel drivers network ether ; HaikuSubInclude etherpci ; HaikuSubInclude pegasus ; HaikuSubInclude virtio ; -HaikuSubInclude usb_asix ; HaikuSubInclude usb_davicom ; HaikuSubInclude usb_ecm ; HaikuSubInclude usb_rndis ; @@ -12,6 +11,7 @@ HaikuSubInclude wb840 ; # FreeBSD drivers HaikuSubInclude 3com ; +HaikuSubInclude asix88xxx ; HaikuSubInclude atheros81xx ; HaikuSubInclude atheros813x ; HaikuSubInclude attansic_l1 ; diff --git a/src/add-ons/kernel/drivers/network/ether/asix88xxx/Jamfile b/src/add-ons/kernel/drivers/network/ether/asix88xxx/Jamfile new file mode 100644 index 0000000000..9a9e248788 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/asix88xxx/Jamfile @@ -0,0 +1,32 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network ether asix88xxx ; + +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] + : true ; +UsePrivateHeaders net system ; +UsePrivateKernelHeaders ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ; + +UseHeaders [ FDirName $(SUBDIR) ] : true ; + +SEARCH_SOURCE += [ FDirName $(SUBDIR) dev mii ] ; +SEARCH_SOURCE += [ FDirName $(SUBDIR) dev usb net ] ; + +KernelAddon asix88xxx : + glue.c + axphy.c + if_axe.c + if_axge.c + : + freebsd_mii.a + freebsd_usb.a + libfreebsd_network.a + ; + +ObjectHdrs [ FGristFiles if_axe$(SUFOBJ) if_axge$(SUFOBJ) ] + : [ FDirName $(HAIKU_COMMON_PLATFORM_OBJECT_DIR) libs compat freebsd_network ] ; +Includes [ FGristFiles if_axe.c if_axge.c ] : usbdevs.h ; + +ObjectHdrs [ FGristFiles axphy$(SUFOBJ) ] + : [ FDirName $(HAIKU_COMMON_PLATFORM_OBJECT_DIR) libs compat freebsd_network ] ; +Includes [ FGristFiles axphy.c ] : miidevs.h ; diff --git a/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/mii/axphy.c b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/mii/axphy.c new file mode 100644 index 0000000000..8bb5a94897 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/mii/axphy.c @@ -0,0 +1,174 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2009 M. Warner Losh + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ +#include +/* + * driver for internal phy in the AX88x9x chips. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include "miidevs.h" + +#include "miibus_if.h" + +static int axphy_probe(device_t dev); +static int axphy_attach(device_t dev); + +static device_method_t axphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, axphy_probe), + DEVMETHOD(device_attach, axphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + DEVMETHOD_END +}; + +static driver_t axphy_driver = { + "axphy", + axphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(axphy, miibus, axphy_driver, 0, 0); + +static int axphy_service(struct mii_softc *, struct mii_data *, int); +static void axphy_status(struct mii_softc *); + +static const struct mii_phydesc axphys[] = { + MII_PHY_DESC(xxASIX, AX88X9X), + MII_PHY_END +}; + +static const struct mii_phy_funcs axphy_funcs = { + axphy_service, + axphy_status, + mii_phy_reset +}; + +static int +axphy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, axphys, BUS_PROBE_DEFAULT)); +} + +static int +axphy_attach(device_t dev) +{ + struct mii_softc *sc; + + sc = device_get_softc(dev); + + mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE, + &axphy_funcs, 1); + mii_phy_setmedia(sc); + + return (0); +} + +static int +axphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + + switch (cmd) { + case MII_POLLSTAT: + break; + + case MII_MEDIACHG: + mii_phy_setmedia(sc); + break; + + case MII_TICK: + if (mii_phy_tick(sc) == EJUSTRETURN) + return (0); + break; + } + + /* Update the media status. */ + PHY_STATUS(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} + +static void +axphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int bmsr, bmcr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); + if (bmsr & BMSR_LINK) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(sc, MII_BMCR); + if (bmcr & BMCR_ISO) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if (bmcr & BMCR_LOOP) + mii->mii_media_active |= IFM_LOOP; + + if (bmcr & BMCR_AUTOEN) { + if ((bmsr & BMSR_ACOMP) == 0) { + mii->mii_media_active |= IFM_NONE; + return; + } + +#if 0 + scr = PHY_READ(sc, MII_AXPHY_SCR); + if (scr & SCR_S100) + mii->mii_media_active |= IFM_100_TX; + else + mii->mii_media_active |= IFM_10_T; + if (scr & SCR_FDX) + mii->mii_media_active |= + IFM_FDX | mii_phy_flowstatus(sc); + else + mii->mii_media_active |= IFM_HDX; +#endif + } else + mii->mii_media_active = ife->ifm_media; +} diff --git a/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axe.c b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axe.c new file mode 100644 index 0000000000..2fa0cc3a69 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axe.c @@ -0,0 +1,1510 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1997, 1998, 1999, 2000-2003 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. + * Used in the LinkSys USB200M and various other adapters. + * + * Manuals available from: + * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF + * Note: you need the manual for the AX88170 chip (USB 1.x ethernet + * controller) to find the definitions for the RX control register. + * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF + * + * Written by Bill Paul + * Senior Engineer + * Wind River Systems + */ + +/* + * The AX88172 provides USB ethernet supports at 10 and 100Mbps. + * It uses an external PHY (reference designs use a RealTek chip), + * and has a 64-bit multicast hash filter. There is some information + * missing from the manual which one needs to know in order to make + * the chip function: + * + * - You must set bit 7 in the RX control register, otherwise the + * chip won't receive any packets. + * - You must initialize all 3 IPG registers, or you won't be able + * to send any packets. + * + * Note that this device appears to only support loading the station + * address via autload from the EEPROM (i.e. there's no way to manually + * set it). + * + * (Adam Weinberger wanted me to name this driver if_gir.c.) + */ + +/* + * Ax88178 and Ax88772 support backported from the OpenBSD driver. + * 2007/02/12, J.R. Oldroyd, fbsd@opal.com + * + * Manual here: + * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf + * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include "usbdevs.h" + +#define USB_DEBUG_VAR axe_debug +#include +#include + +#include +#include + +#include "miibus_if.h" + +/* + * AXE_178_MAX_FRAME_BURST + * max frame burst size for Ax88178 and Ax88772 + * 0 2048 bytes + * 1 4096 bytes + * 2 8192 bytes + * 3 16384 bytes + * use the largest your system can handle without USB stalling. + * + * NB: 88772 parts appear to generate lots of input errors with + * a 2K rx buffer and 8K is only slightly faster than 4K on an + * EHCI port on a T42 so change at your own risk. + */ +#define AXE_178_MAX_FRAME_BURST 1 + +#define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) + +#ifdef USB_DEBUG +static int axe_debug = 0; + +static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, + "USB axe"); +SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, + "Debug level"); +#endif + +/* + * Various supported device vendors/products. + */ +static const STRUCT_USB_HOST_ID axe_devs[] = { +#define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } + AXE_DEV(ABOCOM, UF200, 0), + AXE_DEV(ACERCM, EP1427X2, 0), + AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), + AXE_DEV(ASIX, AX88172, 0), + AXE_DEV(ASIX, AX88178, AXE_FLAG_178), + AXE_DEV(ASIX, AX88772, AXE_FLAG_772), + AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), + AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), + AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), + AXE_DEV(ATEN, UC210T, 0), + AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), + AXE_DEV(BILLIONTON, USB2AR, 0), + AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), + AXE_DEV(COREGA, FETHER_USB2_TX, 0), + AXE_DEV(DLINK, DUBE100, 0), + AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), + AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), + AXE_DEV(GOODWAY, GWUSB2E, 0), + AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), + AXE_DEV(JVC, MP_PRX1, 0), + AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), + AXE_DEV(LINKSYS2, USB200M, 0), + AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), + AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), + AXE_DEV(MELCO, LUAU2KTX, 0), + AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), + AXE_DEV(NETGEAR, FA120, 0), + AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), + AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), + AXE_DEV(SITECOM, LN029, 0), + AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), + AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178), + AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), +#undef AXE_DEV +}; + +static device_probe_t axe_probe; +static device_attach_t axe_attach; +static device_detach_t axe_detach; + +static usb_callback_t axe_bulk_read_callback; +static usb_callback_t axe_bulk_write_callback; + +static miibus_readreg_t axe_miibus_readreg; +static miibus_writereg_t axe_miibus_writereg; +static miibus_statchg_t axe_miibus_statchg; + +static uether_fn_t axe_attach_post; +static uether_fn_t axe_init; +static uether_fn_t axe_stop; +static uether_fn_t axe_start; +static uether_fn_t axe_tick; +static uether_fn_t axe_setmulti; +static uether_fn_t axe_setpromisc; + +static int axe_attach_post_sub(struct usb_ether *); +static int axe_ifmedia_upd(if_t); +static void axe_ifmedia_sts(if_t, struct ifmediareq *); +static int axe_cmd(struct axe_softc *, int, int, int, void *); +static void axe_ax88178_init(struct axe_softc *); +static void axe_ax88772_init(struct axe_softc *); +static void axe_ax88772_phywake(struct axe_softc *); +static void axe_ax88772a_init(struct axe_softc *); +static void axe_ax88772b_init(struct axe_softc *); +static int axe_get_phyno(struct axe_softc *, int); +static int axe_ioctl(if_t, u_long, caddr_t); +static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); +static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, + unsigned offset, unsigned, struct axe_csum_hdr *); +static void axe_csum_cfg(struct usb_ether *); + +static const struct usb_config axe_config[AXE_N_TRANSFER] = { + [AXE_BULK_DT_WR] = { + .type = UE_BULK, + .endpoint = UE_ADDR_ANY, + .direction = UE_DIR_OUT, + .frames = 16, + .bufsize = 16 * MCLBYTES, + .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, + .callback = axe_bulk_write_callback, + .timeout = 10000, /* 10 seconds */ + }, + + [AXE_BULK_DT_RD] = { + .type = UE_BULK, + .endpoint = UE_ADDR_ANY, + .direction = UE_DIR_IN, + .bufsize = 16384, /* bytes */ + .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, + .callback = axe_bulk_read_callback, + .timeout = 0, /* no timeout */ + }, +}; + +static const struct ax88772b_mfb ax88772b_mfb_table[] = { + { 0x8000, 0x8001, 2048 }, + { 0x8100, 0x8147, 4096}, + { 0x8200, 0x81EB, 6144}, + { 0x8300, 0x83D7, 8192}, + { 0x8400, 0x851E, 16384}, + { 0x8500, 0x8666, 20480}, + { 0x8600, 0x87AE, 24576}, + { 0x8700, 0x8A3D, 32768} +}; + +static device_method_t axe_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, axe_probe), + DEVMETHOD(device_attach, axe_attach), + DEVMETHOD(device_detach, axe_detach), + + /* MII interface */ + DEVMETHOD(miibus_readreg, axe_miibus_readreg), + DEVMETHOD(miibus_writereg, axe_miibus_writereg), + DEVMETHOD(miibus_statchg, axe_miibus_statchg), + + DEVMETHOD_END +}; + +static driver_t axe_driver = { + .name = "axe", + .methods = axe_methods, + .size = sizeof(struct axe_softc), +}; + +DRIVER_MODULE(axe, uhub, axe_driver, NULL, NULL); +DRIVER_MODULE(miibus, axe, miibus_driver, 0, 0); +MODULE_DEPEND(axe, uether, 1, 1, 1); +MODULE_DEPEND(axe, usb, 1, 1, 1); +MODULE_DEPEND(axe, ether, 1, 1, 1); +MODULE_DEPEND(axe, miibus, 1, 1, 1); +MODULE_VERSION(axe, 1); +USB_PNP_HOST_INFO(axe_devs); + +static const struct usb_ether_methods axe_ue_methods = { + .ue_attach_post = axe_attach_post, + .ue_attach_post_sub = axe_attach_post_sub, + .ue_start = axe_start, + .ue_init = axe_init, + .ue_stop = axe_stop, + .ue_tick = axe_tick, + .ue_setmulti = axe_setmulti, + .ue_setpromisc = axe_setpromisc, + .ue_mii_upd = axe_ifmedia_upd, + .ue_mii_sts = axe_ifmedia_sts, +}; + +static int +axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) +{ + struct usb_device_request req; + usb_error_t err; + + AXE_LOCK_ASSERT(sc, MA_OWNED); + + req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? + UT_WRITE_VENDOR_DEVICE : + UT_READ_VENDOR_DEVICE); + req.bRequest = AXE_CMD_CMD(cmd); + USETW(req.wValue, val); + USETW(req.wIndex, index); + USETW(req.wLength, AXE_CMD_LEN(cmd)); + + err = uether_do_request(&sc->sc_ue, &req, buf, 1000); + + return (err); +} + +static int +axe_miibus_readreg(device_t dev, int phy, int reg) +{ + struct axe_softc *sc = device_get_softc(dev); + uint16_t val; + int locked; + + locked = mtx_owned(&sc->sc_mtx); + if (!locked) + AXE_LOCK(sc); + + axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); + axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); + axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); + + val = le16toh(val); + if (AXE_IS_772(sc) && reg == MII_BMSR) { + /* + * BMSR of AX88772 indicates that it supports extended + * capability but the extended status register is + * revered for embedded ethernet PHY. So clear the + * extended capability bit of BMSR. + */ + val &= ~BMSR_EXTCAP; + } + + if (!locked) + AXE_UNLOCK(sc); + return (val); +} + +static int +axe_miibus_writereg(device_t dev, int phy, int reg, int val) +{ + struct axe_softc *sc = device_get_softc(dev); + int locked; + + val = htole32(val); + locked = mtx_owned(&sc->sc_mtx); + if (!locked) + AXE_LOCK(sc); + + axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); + axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); + axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); + + if (!locked) + AXE_UNLOCK(sc); + return (0); +} + +static void +axe_miibus_statchg(device_t dev) +{ + struct axe_softc *sc = device_get_softc(dev); + struct mii_data *mii = GET_MII(sc); + if_t ifp; + uint16_t val; + int err, locked; + + locked = mtx_owned(&sc->sc_mtx); + if (!locked) + AXE_LOCK(sc); + + ifp = uether_getifp(&sc->sc_ue); + if (mii == NULL || ifp == NULL || + (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) + goto done; + + sc->sc_flags &= ~AXE_FLAG_LINK; + if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == + (IFM_ACTIVE | IFM_AVALID)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + sc->sc_flags |= AXE_FLAG_LINK; + break; + case IFM_1000_T: + if ((sc->sc_flags & AXE_FLAG_178) == 0) + break; + sc->sc_flags |= AXE_FLAG_LINK; + break; + default: + break; + } + } + + /* Lost link, do nothing. */ + if ((sc->sc_flags & AXE_FLAG_LINK) == 0) + goto done; + + val = 0; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { + val |= AXE_MEDIA_FULL_DUPLEX; + if (AXE_IS_178_FAMILY(sc)) { + if ((IFM_OPTIONS(mii->mii_media_active) & + IFM_ETH_TXPAUSE) != 0) + val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; + if ((IFM_OPTIONS(mii->mii_media_active) & + IFM_ETH_RXPAUSE) != 0) + val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; + } + } + if (AXE_IS_178_FAMILY(sc)) { + val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; + if ((sc->sc_flags & AXE_FLAG_178) != 0) + val |= AXE_178_MEDIA_ENCK; + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_1000_T: + val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; + break; + case IFM_100_TX: + val |= AXE_178_MEDIA_100TX; + break; + case IFM_10_T: + /* doesn't need to be handled */ + break; + } + } + err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); + if (err) + device_printf(dev, "media change failed, error %d\n", err); +done: + if (!locked) + AXE_UNLOCK(sc); +} + +/* + * Set media options. + */ +static int +axe_ifmedia_upd(if_t ifp) +{ + struct axe_softc *sc = if_getsoftc(ifp); + struct mii_data *mii = GET_MII(sc); + struct mii_softc *miisc; + int error; + + AXE_LOCK_ASSERT(sc, MA_OWNED); + + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + PHY_RESET(miisc); + error = mii_mediachg(mii); + return (error); +} + +/* + * Report current media status. + */ +static void +axe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) +{ + struct axe_softc *sc = if_getsoftc(ifp); + struct mii_data *mii = GET_MII(sc); + + AXE_LOCK(sc); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + AXE_UNLOCK(sc); +} + +static u_int +axe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) +{ + uint8_t *hashtbl = arg; + uint32_t h; + + h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; + hashtbl[h / 8] |= 1 << (h % 8); + + return (1); +} + +static void +axe_setmulti(struct usb_ether *ue) +{ + struct axe_softc *sc = uether_getsc(ue); + if_t ifp = uether_getifp(ue); + uint16_t rxmode; + uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + + AXE_LOCK_ASSERT(sc, MA_OWNED); + + axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); + rxmode = le16toh(rxmode); + + if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { + rxmode |= AXE_RXCMD_ALLMULTI; + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); + return; + } + rxmode &= ~AXE_RXCMD_ALLMULTI; + + if_foreach_llmaddr(ifp, axe_hash_maddr, &hashtbl); + + axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); +} + +static int +axe_get_phyno(struct axe_softc *sc, int sel) +{ + int phyno; + + switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { + case PHY_TYPE_100_HOME: + case PHY_TYPE_GIG: + phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); + break; + case PHY_TYPE_SPECIAL: + /* FALLTHROUGH */ + case PHY_TYPE_RSVD: + /* FALLTHROUGH */ + case PHY_TYPE_NON_SUP: + /* FALLTHROUGH */ + default: + phyno = -1; + break; + } + + return (phyno); +} + +#define AXE_GPIO_WRITE(x, y) do { \ + axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ + uether_pause(ue, (y)); \ +} while (0) + +static void +axe_ax88178_init(struct axe_softc *sc) +{ + struct usb_ether *ue; + int gpio0, ledmode, phymode; + uint16_t eeprom, val; + + ue = &sc->sc_ue; + axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); + /* XXX magic */ + axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); + eeprom = le16toh(eeprom); + axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); + + /* if EEPROM is invalid we have to use to GPIO0 */ + if (eeprom == 0xffff) { + phymode = AXE_PHY_MODE_MARVELL; + gpio0 = 1; + ledmode = 0; + } else { + phymode = eeprom & 0x7f; + gpio0 = (eeprom & 0x80) ? 0 : 1; + ledmode = eeprom >> 8; + } + + if (bootverbose) + device_printf(sc->sc_ue.ue_dev, + "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, + phymode); + /* Program GPIOs depending on PHY hardware. */ + switch (phymode) { + case AXE_PHY_MODE_MARVELL: + if (gpio0 == 1) { + AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, + hz / 32); + AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, + hz / 32); + AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); + AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, + hz / 32); + } else { + AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | + AXE_GPIO1_EN, hz / 3); + if (ledmode == 1) { + AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, + hz / 3); + } else { + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | + AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | + AXE_GPIO2_EN, hz / 4); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | + AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); + } + } + break; + case AXE_PHY_MODE_CICADA: + case AXE_PHY_MODE_CICADA_V2: + case AXE_PHY_MODE_CICADA_V2_ASIX: + if (gpio0 == 1) + AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | + AXE_GPIO0_EN, hz / 32); + else + AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | + AXE_GPIO1_EN, hz / 32); + break; + case AXE_PHY_MODE_AGERE: + AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | + AXE_GPIO1_EN, hz / 32); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | + AXE_GPIO2_EN, hz / 32); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); + AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | + AXE_GPIO2_EN, hz / 32); + break; + case AXE_PHY_MODE_REALTEK_8211CL: + case AXE_PHY_MODE_REALTEK_8211BN: + case AXE_PHY_MODE_REALTEK_8251CL: + val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : + AXE_GPIO1 | AXE_GPIO1_EN; + AXE_GPIO_WRITE(val, hz / 32); + AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); + AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); + AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); + if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { + axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, + 0x1F, 0x0005); + axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, + 0x0C, 0x0000); + val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, + 0x0001); + axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, + 0x01, val | 0x0080); + axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, + 0x1F, 0x0000); + } + break; + default: + /* Unknown PHY model or no need to program GPIOs. */ + break; + } + + /* soft reset */ + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); + uether_pause(ue, hz / 4); + + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, + AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); + uether_pause(ue, hz / 4); + /* Enable MII/GMII/RGMII interface to work with external PHY. */ + axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); + uether_pause(ue, hz / 4); + + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); +} + +static void +axe_ax88772_init(struct axe_softc *sc) +{ + axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); + uether_pause(&sc->sc_ue, hz / 16); + + if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { + /* ask for the embedded PHY */ + axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); + uether_pause(&sc->sc_ue, hz / 64); + + /* power down and reset state, pin reset state */ + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, + AXE_SW_RESET_CLEAR, NULL); + uether_pause(&sc->sc_ue, hz / 16); + + /* power down/reset state, pin operating state */ + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, + AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); + uether_pause(&sc->sc_ue, hz / 4); + + /* power up, reset */ + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); + + /* power up, operating */ + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, + AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); + } else { + /* ask for external PHY */ + axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); + uether_pause(&sc->sc_ue, hz / 64); + + /* power down internal PHY */ + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, + AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); + } + + uether_pause(&sc->sc_ue, hz / 4); + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); +} + +static void +axe_ax88772_phywake(struct axe_softc *sc) +{ + if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { + /* Manually select internal(embedded) PHY - MAC mode. */ + axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | + AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, + NULL); + uether_pause(&sc->sc_ue, hz / 32); + } else { + /* + * Manually select external PHY - MAC mode. + * Reverse MII/RMII is for AX88772A PHY mode. + */ + axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | + AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); + uether_pause(&sc->sc_ue, hz / 32); + } + /* Take PHY out of power down. */ + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | + AXE_SW_RESET_IPRL, NULL); + uether_pause(&sc->sc_ue, hz / 4); + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); + uether_pause(&sc->sc_ue, hz); + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); + uether_pause(&sc->sc_ue, hz / 32); + axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); + uether_pause(&sc->sc_ue, hz / 32); +} + +static void +axe_ax88772a_init(struct axe_softc *sc) +{ + struct usb_ether *ue; + + ue = &sc->sc_ue; + /* Reload EEPROM. */ + AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); + axe_ax88772_phywake(sc); + /* Stop MAC. */ + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); +} + +static void +axe_ax88772b_init(struct axe_softc *sc) +{ + struct usb_ether *ue; + uint16_t eeprom; + uint8_t *eaddr; + int i; + + ue = &sc->sc_ue; + /* Reload EEPROM. */ + AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); + /* + * Save PHY power saving configuration(high byte) and + * clear EEPROM checksum value(low byte). + */ + axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); + sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; + + /* + * Auto-loaded default station address from internal ROM is + * 00:00:00:00:00:00 such that an explicit access to EEPROM + * is required to get real station address. + */ + eaddr = ue->ue_eaddr; + for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { + axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, + &eeprom); + eeprom = le16toh(eeprom); + *eaddr++ = (uint8_t)(eeprom & 0xFF); + *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); + } + /* Wakeup PHY. */ + axe_ax88772_phywake(sc); + /* Stop MAC. */ + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); +} + +#undef AXE_GPIO_WRITE + +static void +axe_reset(struct axe_softc *sc) +{ + struct usb_config_descriptor *cd; + usb_error_t err; + +#ifdef __HAIKU__ + // TODO + err = 1; +#else + cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); + + err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, + cd->bConfigurationValue); +#endif + if (err) + DPRINTF("reset failed (ignored)\n"); + + /* Wait a little while for the chip to get its brains in order. */ + uether_pause(&sc->sc_ue, hz / 100); + + /* Reinitialize controller to achieve full reset. */ + if (sc->sc_flags & AXE_FLAG_178) + axe_ax88178_init(sc); + else if (sc->sc_flags & AXE_FLAG_772) + axe_ax88772_init(sc); + else if (sc->sc_flags & AXE_FLAG_772A) + axe_ax88772a_init(sc); + else if (sc->sc_flags & AXE_FLAG_772B) + axe_ax88772b_init(sc); +} + +static void +axe_attach_post(struct usb_ether *ue) +{ + struct axe_softc *sc = uether_getsc(ue); + + /* + * Load PHY indexes first. Needed by axe_xxx_init(). + */ + axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); + if (bootverbose) + device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", + sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); + sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); + if (sc->sc_phyno == -1) + sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); + if (sc->sc_phyno == -1) { + device_printf(sc->sc_ue.ue_dev, + "no valid PHY address found, assuming PHY address 0\n"); + sc->sc_phyno = 0; + } + + /* Initialize controller and get station address. */ + if (sc->sc_flags & AXE_FLAG_178) { + axe_ax88178_init(sc); + axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); + } else if (sc->sc_flags & AXE_FLAG_772) { + axe_ax88772_init(sc); + axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); + } else if (sc->sc_flags & AXE_FLAG_772A) { + axe_ax88772a_init(sc); + axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); + } else if (sc->sc_flags & AXE_FLAG_772B) { + axe_ax88772b_init(sc); + } else + axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); + + /* + * Fetch IPG values. + */ + if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { + /* Set IPG values. */ + sc->sc_ipgs[0] = 0x15; + sc->sc_ipgs[1] = 0x16; + sc->sc_ipgs[2] = 0x1A; + } else + axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); +} + +static int +axe_attach_post_sub(struct usb_ether *ue) +{ + struct axe_softc *sc; + if_t ifp; + u_int adv_pause; + int error; + + sc = uether_getsc(ue); + ifp = ue->ue_ifp; + if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); + if_setstartfn(ifp, uether_start); + if_setioctlfn(ifp, axe_ioctl); + if_setinitfn(ifp, uether_init); + if_setsendqlen(ifp, ifqmaxlen); + if_setsendqready(ifp); + + if (AXE_IS_178_FAMILY(sc)) + if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); + if (sc->sc_flags & AXE_FLAG_772B) { + if_setcapabilitiesbit(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM, 0); + if_sethwassist(ifp, AXE_CSUM_FEATURES); + /* + * Checksum offloading of AX88772B also works with VLAN + * tagged frames but there is no way to take advantage + * of the feature because vlan(4) assumes + * IFCAP_VLAN_HWTAGGING is prerequisite condition to + * support checksum offloading with VLAN. VLAN hardware + * tagging support of AX88772B is very limited so it's + * not possible to announce IFCAP_VLAN_HWTAGGING. + */ + } + if_setcapenable(ifp, if_getcapabilities(ifp)); + if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) + adv_pause = MIIF_DOPAUSE; + else + adv_pause = 0; +#ifndef __HAIKU__ + bus_topo_lock(); +#endif + error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, + uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, + BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); +#ifndef __HAIKU__ + bus_topo_unlock(); +#endif + + return (error); +} + +/* + * Probe for a AX88172 chip. + */ +static int +axe_probe(device_t dev) +{ + struct usb_attach_arg *uaa = device_get_ivars(dev); + + if (uaa->usb_mode != USB_MODE_HOST) + return (ENXIO); + if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) + return (ENXIO); + if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) + return (ENXIO); + + return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); +} + +/* + * Attach the interface. Allocate softc structures, do ifmedia + * setup and ethernet/BPF attach. + */ +static int +axe_attach(device_t dev) +{ + struct usb_attach_arg *uaa = device_get_ivars(dev); + struct axe_softc *sc = device_get_softc(dev); + struct usb_ether *ue = &sc->sc_ue; + uint8_t iface_index; + int error; + + sc->sc_flags = USB_GET_DRIVER_INFO(uaa); + + device_set_usb_desc(dev); + + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + iface_index = AXE_IFACE_IDX; + error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, + axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); + if (error) { + device_printf(dev, "allocating USB transfers failed\n"); + goto detach; + } + + ue->ue_sc = sc; + ue->ue_dev = dev; + ue->ue_udev = uaa->device; + ue->ue_mtx = &sc->sc_mtx; + ue->ue_methods = &axe_ue_methods; + + error = uether_ifattach(ue); + if (error) { + device_printf(dev, "could not attach interface\n"); + goto detach; + } + return (0); /* success */ + +detach: + axe_detach(dev); + return (ENXIO); /* failure */ +} + +static int +axe_detach(device_t dev) +{ + struct axe_softc *sc = device_get_softc(dev); + struct usb_ether *ue = &sc->sc_ue; + + usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); + uether_ifdetach(ue); + mtx_destroy(&sc->sc_mtx); + + return (0); +} + +#if (AXE_BULK_BUF_SIZE >= 0x10000) +#error "Please update axe_bulk_read_callback()!" +#endif + +static void +axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) +{ + struct axe_softc *sc = usbd_xfer_softc(xfer); + struct usb_ether *ue = &sc->sc_ue; + struct usb_page_cache *pc; + int actlen; + + usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); + + switch (USB_GET_STATE(xfer)) { + case USB_ST_TRANSFERRED: + pc = usbd_xfer_get_frame(xfer, 0); + axe_rx_frame(ue, pc, actlen); + + /* FALLTHROUGH */ + case USB_ST_SETUP: +tr_setup: + usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); + usbd_transfer_submit(xfer); + uether_rxflush(ue); + return; + + default: /* Error */ + DPRINTF("bulk read error, %s\n", usbd_errstr(error)); + + if (error != USB_ERR_CANCELLED) { + /* try to clear stall first */ + usbd_xfer_set_stall(xfer); + goto tr_setup; + } + return; + } +} + +static int +axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) +{ + struct axe_softc *sc; + struct axe_sframe_hdr hdr; + struct axe_csum_hdr csum_hdr; + int error, len, pos; + + sc = uether_getsc(ue); + pos = 0; + len = 0; + error = 0; + if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { + while (pos < actlen) { + if ((int)(pos + sizeof(hdr)) > actlen) { + /* too little data */ + error = EINVAL; + break; + } + usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); + + if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { + /* we lost sync */ + error = EINVAL; + break; + } + pos += sizeof(hdr); + len = le16toh(hdr.len); + if (pos + len > actlen) { + /* invalid length */ + error = EINVAL; + break; + } + axe_rxeof(ue, pc, pos, len, NULL); + pos += len + (len % 2); + } + } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { + while (pos < actlen) { + if ((int)(pos + sizeof(csum_hdr)) > actlen) { + /* too little data */ + error = EINVAL; + break; + } + usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); + + csum_hdr.len = le16toh(csum_hdr.len); + csum_hdr.ilen = le16toh(csum_hdr.ilen); + csum_hdr.cstatus = le16toh(csum_hdr.cstatus); + if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ + AXE_CSUM_RXBYTES(csum_hdr.ilen)) != + sc->sc_lenmask) { + /* we lost sync */ + error = EINVAL; + break; + } + /* + * Get total transferred frame length including + * checksum header. The length should be multiple + * of 4. + */ + len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); + len = (len + 3) & ~3; + if (pos + len > actlen) { + /* invalid length */ + error = EINVAL; + break; + } + axe_rxeof(ue, pc, pos + sizeof(csum_hdr), + AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); + pos += len; + } + } else + axe_rxeof(ue, pc, 0, actlen, NULL); + + if (error != 0) + if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); + return (error); +} + +static int +axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned offset, + unsigned len, struct axe_csum_hdr *csum_hdr) +{ + if_t ifp = ue->ue_ifp; + struct mbuf *m; + + if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { + if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); + return (EINVAL); + } + + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); + if (m == NULL) { + if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); + return (ENOMEM); + } + m->m_len = m->m_pkthdr.len = MCLBYTES; + m_adj(m, ETHER_ALIGN); + + usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); + + if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = len; + + if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { + if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | + AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | + CSUM_IP_VALID; + if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == + AXE_CSUM_HDR_L4_TYPE_TCP || + (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == + AXE_CSUM_HDR_L4_TYPE_UDP) { + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID | CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + } + + (void)mbufq_enqueue(&ue->ue_rxq, m); + return (0); +} + +#if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) +#error "Please update axe_bulk_write_callback()!" +#endif + +static void +axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) +{ + struct axe_softc *sc = usbd_xfer_softc(xfer); + struct axe_sframe_hdr hdr; + if_t ifp = uether_getifp(&sc->sc_ue); + struct usb_page_cache *pc; + struct mbuf *m; + int nframes, pos; + + switch (USB_GET_STATE(xfer)) { + case USB_ST_TRANSFERRED: + DPRINTFN(11, "transfer complete\n"); + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); + /* FALLTHROUGH */ + case USB_ST_SETUP: +tr_setup: + if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || + (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) { + /* + * Don't send anything if there is no link or + * controller is busy. + */ + return; + } + + for (nframes = 0; nframes < 16 && + !if_sendq_empty(ifp); nframes++) { + m = if_dequeue(ifp); + if (m == NULL) + break; +#ifndef __HAIKU__ /* shouldn't matter for our buffer management? */ + usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, + nframes); +#endif + pos = 0; + pc = usbd_xfer_get_frame(xfer, nframes); + if (AXE_IS_178_FAMILY(sc)) { + hdr.len = htole16(m->m_pkthdr.len); + hdr.ilen = ~hdr.len; + /* + * If upper stack computed checksum, driver + * should tell controller not to insert + * computed checksum for checksum offloading + * enabled controller. + */ + if (if_getcapabilities(ifp) & IFCAP_TXCSUM) { + if ((m->m_pkthdr.csum_flags & + AXE_CSUM_FEATURES) != 0) + hdr.len |= htole16( + AXE_TX_CSUM_PSEUDO_HDR); + else + hdr.len |= htole16( + AXE_TX_CSUM_DIS); + } + usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); + pos += sizeof(hdr); + usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); + pos += m->m_pkthdr.len; + if ((pos % 512) == 0) { + hdr.len = 0; + hdr.ilen = 0xffff; + usbd_copy_in(pc, pos, &hdr, + sizeof(hdr)); + pos += sizeof(hdr); + } + } else { + usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); + pos += m->m_pkthdr.len; + } + + /* + * XXX + * Update TX packet counter here. This is not + * correct way but it seems that there is no way + * to know how many packets are sent at the end + * of transfer because controller combines + * multiple writes into single one if there is + * room in TX buffer of controller. + */ + if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); + + /* + * if there's a BPF listener, bounce a copy + * of this frame to him: + */ + BPF_MTAP(ifp, m); + + m_freem(m); + + /* Set frame length. */ + usbd_xfer_set_frame_len(xfer, nframes, pos); + } + if (nframes != 0) { + usbd_xfer_set_frames(xfer, nframes); + usbd_transfer_submit(xfer); + if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); + } + return; + /* NOTREACHED */ + default: /* Error */ + DPRINTFN(11, "transfer error, %s\n", + usbd_errstr(error)); + + if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); + + if (error != USB_ERR_CANCELLED) { + /* try to clear stall first */ + usbd_xfer_set_stall(xfer); + goto tr_setup; + } + return; + } +} + +static void +axe_tick(struct usb_ether *ue) +{ + struct axe_softc *sc = uether_getsc(ue); + struct mii_data *mii = GET_MII(sc); + + AXE_LOCK_ASSERT(sc, MA_OWNED); + + mii_tick(mii); + if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { + axe_miibus_statchg(ue->ue_dev); + if ((sc->sc_flags & AXE_FLAG_LINK) != 0) + axe_start(ue); + } +} + +static void +axe_start(struct usb_ether *ue) +{ + struct axe_softc *sc = uether_getsc(ue); + + /* + * start the USB transfers, if not already started: + */ + usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); + usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); +} + +static void +axe_csum_cfg(struct usb_ether *ue) +{ + struct axe_softc *sc; + if_t ifp; + uint16_t csum1, csum2; + + sc = uether_getsc(ue); + AXE_LOCK_ASSERT(sc, MA_OWNED); + + if ((sc->sc_flags & AXE_FLAG_772B) != 0) { + ifp = uether_getifp(ue); + csum1 = 0; + csum2 = 0; + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | + AXE_TXCSUM_UDP; + axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); + csum1 = 0; + csum2 = 0; + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) + csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | + AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | + AXE_RXCSUM_IGMP; + axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); + } +} + +static void +axe_init(struct usb_ether *ue) +{ + struct axe_softc *sc = uether_getsc(ue); + if_t ifp = uether_getifp(ue); + uint16_t rxmode; + + AXE_LOCK_ASSERT(sc, MA_OWNED); + + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) + return; + + /* Cancel pending I/O */ + axe_stop(ue); + + axe_reset(sc); + + /* Set MAC address and transmitter IPG values. */ + if (AXE_IS_178_FAMILY(sc)) { + axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, if_getlladdr(ifp)); + axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], + (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); + } else { + axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, if_getlladdr(ifp)); + axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); + axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); + axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); + } + + if (AXE_IS_178_FAMILY(sc)) { + sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); + if ((sc->sc_flags & AXE_FLAG_772B) != 0 && + (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { + sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; + sc->sc_flags |= AXE_FLAG_CSUM_FRAME; + } else { + sc->sc_lenmask = AXE_HDR_LEN_MASK; + sc->sc_flags |= AXE_FLAG_STD_FRAME; + } + } + + /* Configure TX/RX checksum offloading. */ + axe_csum_cfg(ue); + + if (sc->sc_flags & AXE_FLAG_772B) { + /* AX88772B uses different maximum frame burst configuration. */ + axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, + ax88772b_mfb_table[AX88772B_MFB_16K].threshold, + ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); + } + + /* Enable receiver, set RX mode. */ + rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); + if (AXE_IS_178_FAMILY(sc)) { + if (sc->sc_flags & AXE_FLAG_772B) { + /* + * Select RX header format type 1. Aligning IP + * header on 4 byte boundary is not needed when + * checksum offloading feature is not used + * because we always copy the received frame in + * RX handler. When RX checksum offloading is + * active, aligning IP header is required to + * reflect actual frame length including RX + * header size. + */ + rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) + rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; + } else { + /* + * Default Rx buffer size is too small to get + * maximum performance. + */ + rxmode |= AXE_178_RXCMD_MFB_16384; + } + } else { + rxmode |= AXE_172_RXCMD_UNICAST; + } + + /* If we want promiscuous mode, set the allframes bit. */ + if (if_getflags(ifp) & IFF_PROMISC) + rxmode |= AXE_RXCMD_PROMISC; + + if (if_getflags(ifp) & IFF_BROADCAST) + rxmode |= AXE_RXCMD_BROADCAST; + + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); + + /* Load the multicast filter. */ + axe_setmulti(ue); + + usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); + + if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); + /* Switch to selected media. */ + axe_ifmedia_upd(ifp); +} + +static void +axe_setpromisc(struct usb_ether *ue) +{ + struct axe_softc *sc = uether_getsc(ue); + if_t ifp = uether_getifp(ue); + uint16_t rxmode; + + axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); + + rxmode = le16toh(rxmode); + + if (if_getflags(ifp) & IFF_PROMISC) { + rxmode |= AXE_RXCMD_PROMISC; + } else { + rxmode &= ~AXE_RXCMD_PROMISC; + } + + axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); + + axe_setmulti(ue); +} + +static void +axe_stop(struct usb_ether *ue) +{ + struct axe_softc *sc = uether_getsc(ue); + if_t ifp = uether_getifp(ue); + + AXE_LOCK_ASSERT(sc, MA_OWNED); + + if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); + sc->sc_flags &= ~AXE_FLAG_LINK; + + /* + * stop all the transfers, if not already stopped: + */ + usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); + usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); +} + +static int +axe_ioctl(if_t ifp, u_long cmd, caddr_t data) +{ + struct usb_ether *ue = if_getsoftc(ifp); + struct axe_softc *sc; + struct ifreq *ifr; + int error, mask, reinit; + + sc = uether_getsc(ue); + ifr = (struct ifreq *)data; + error = 0; + reinit = 0; + if (cmd == SIOCSIFCAP) { + AXE_LOCK(sc); + mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); + if ((mask & IFCAP_TXCSUM) != 0 && + (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_TXCSUM); + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + if_sethwassistbits(ifp, AXE_CSUM_FEATURES, 0); + else + if_sethwassistbits(ifp, 0, AXE_CSUM_FEATURES); + reinit++; + } + if ((mask & IFCAP_RXCSUM) != 0 && + (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_RXCSUM); + reinit++; + } + if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING) + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); + else + reinit = 0; + AXE_UNLOCK(sc); + if (reinit > 0) + uether_init(ue); + } else + error = uether_ioctl(ifp, cmd, data); + + return (error); +} diff --git a/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axereg.h b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axereg.h new file mode 100644 index 0000000000..4b47fd4b8a --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axereg.h @@ -0,0 +1,363 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1997, 1998, 1999, 2000-2003 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Definitions for the ASIX Electronics AX88172, AX88178 + * and AX88772 to ethernet controllers. + */ + +/* + * Vendor specific commands. ASIX conveniently doesn't document the 'set + * NODEID' command in their datasheet (thanks a lot guys). + * To make handling these commands easier, I added some extra data which is + * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with + * the format: LDCC. L and D are both nibbles in the high byte. L represents + * the data length (0 to 15) and D represents the direction (0 for vendor read, + * 1 for vendor write). CC is the command byte, as specified in the manual. + */ + +#define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) +#define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) +#define AXE_CMD_CMD(x) ((x) & 0x00FF) + +#define AXE_172_CMD_READ_RXTX_SRAM 0x2002 +#define AXE_182_CMD_READ_RXTX_SRAM 0x8002 +#define AXE_172_CMD_WRITE_RX_SRAM 0x0103 +#define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 +#define AXE_172_CMD_WRITE_TX_SRAM 0x0104 +#define AXE_CMD_MII_OPMODE_SW 0x0106 +#define AXE_CMD_MII_READ_REG 0x2007 +#define AXE_CMD_MII_WRITE_REG 0x2108 +#define AXE_CMD_MII_READ_OPMODE 0x1009 +#define AXE_CMD_MII_OPMODE_HW 0x010A +#define AXE_CMD_SROM_READ 0x200B +#define AXE_CMD_SROM_WRITE 0x010C +#define AXE_CMD_SROM_WR_ENABLE 0x010D +#define AXE_CMD_SROM_WR_DISABLE 0x010E +#define AXE_CMD_RXCTL_READ 0x200F +#define AXE_CMD_RXCTL_WRITE 0x0110 +#define AXE_CMD_READ_IPG012 0x3011 +#define AXE_172_CMD_WRITE_IPG0 0x0112 +#define AXE_178_CMD_WRITE_IPG012 0x0112 +#define AXE_172_CMD_WRITE_IPG1 0x0113 +#define AXE_178_CMD_READ_NODEID 0x6013 +#define AXE_172_CMD_WRITE_IPG2 0x0114 +#define AXE_178_CMD_WRITE_NODEID 0x6114 +#define AXE_CMD_READ_MCAST 0x8015 +#define AXE_CMD_WRITE_MCAST 0x8116 +#define AXE_172_CMD_READ_NODEID 0x6017 +#define AXE_172_CMD_WRITE_NODEID 0x6118 + +#define AXE_CMD_READ_PHYID 0x2019 +#define AXE_172_CMD_READ_MEDIA 0x101A +#define AXE_178_CMD_READ_MEDIA 0x201A +#define AXE_CMD_WRITE_MEDIA 0x011B +#define AXE_CMD_READ_MONITOR_MODE 0x101C +#define AXE_CMD_WRITE_MONITOR_MODE 0x011D +#define AXE_CMD_READ_GPIO 0x101E +#define AXE_CMD_WRITE_GPIO 0x011F + +#define AXE_CMD_SW_RESET_REG 0x0120 +#define AXE_CMD_SW_PHY_STATUS 0x0021 +#define AXE_CMD_SW_PHY_SELECT 0x0122 + +/* AX88772A and AX88772B only. */ +#define AXE_CMD_READ_VLAN_CTRL 0x4027 +#define AXE_CMD_WRITE_VLAN_CTRL 0x4028 + +#define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A +#define AXE_772B_CMD_READ_RXCSUM 0x002B +#define AXE_772B_CMD_WRITE_RXCSUM 0x012C +#define AXE_772B_CMD_READ_TXCSUM 0x002D +#define AXE_772B_CMD_WRITE_TXCSUM 0x012E + +#define AXE_SW_RESET_CLEAR 0x00 +#define AXE_SW_RESET_RR 0x01 +#define AXE_SW_RESET_RT 0x02 +#define AXE_SW_RESET_PRTE 0x04 +#define AXE_SW_RESET_PRL 0x08 +#define AXE_SW_RESET_BZ 0x10 +#define AXE_SW_RESET_IPRL 0x20 +#define AXE_SW_RESET_IPPD 0x40 + +/* AX88178 documentation says to always write this bit... */ +#define AXE_178_RESET_MAGIC 0x40 + +#define AXE_178_MEDIA_GMII 0x0001 +#define AXE_MEDIA_FULL_DUPLEX 0x0002 +#define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 + +/* AX88178/88772 documentation says to always write 1 to bit 2 */ +#define AXE_178_MEDIA_MAGIC 0x0004 +/* AX88772 documentation says to always write 0 to bit 3 */ +#define AXE_178_MEDIA_ENCK 0x0008 +#define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 +#define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 +#define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 +#define AXE_178_MEDIA_JUMBO_EN 0x0040 +#define AXE_178_MEDIA_LTPF_ONLY 0x0080 +#define AXE_178_MEDIA_RX_EN 0x0100 +#define AXE_178_MEDIA_100TX 0x0200 +#define AXE_178_MEDIA_SBP 0x0800 +#define AXE_178_MEDIA_SUPERMAC 0x1000 + +#define AXE_RXCMD_PROMISC 0x0001 +#define AXE_RXCMD_ALLMULTI 0x0002 +#define AXE_172_RXCMD_UNICAST 0x0004 +#define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 +#define AXE_RXCMD_BROADCAST 0x0008 +#define AXE_RXCMD_MULTICAST 0x0010 +#define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */ +#define AXE_RXCMD_ENABLE 0x0080 +#define AXE_178_RXCMD_MFB_MASK 0x0300 +#define AXE_178_RXCMD_MFB_2048 0x0000 +#define AXE_178_RXCMD_MFB_4096 0x0100 +#define AXE_178_RXCMD_MFB_8192 0x0200 +#define AXE_178_RXCMD_MFB_16384 0x0300 +#define AXE_772B_RXCMD_HDR_TYPE_0 0x0000 +#define AXE_772B_RXCMD_HDR_TYPE_1 0x0100 +#define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200 +#define AXE_772B_RXCMD_ADD_CHKSUM 0x0400 +#define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */ + +#define AXE_PHY_SEL_PRI 1 +#define AXE_PHY_SEL_SEC 0 +#define AXE_PHY_TYPE_MASK 0xE0 +#define AXE_PHY_TYPE_SHIFT 5 +#define AXE_PHY_TYPE(x) \ + (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) + +#define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ +#define PHY_TYPE_GIG 1 /* Gigabit PHY */ +#define PHY_TYPE_SPECIAL 4 /* Special case */ +#define PHY_TYPE_RSVD 5 /* Reserved */ +#define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ + +#define AXE_PHY_NO_MASK 0x1F +#define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) + +#define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ + +#define AXE_GPIO0_EN 0x01 +#define AXE_GPIO0 0x02 +#define AXE_GPIO1_EN 0x04 +#define AXE_GPIO1 0x08 +#define AXE_GPIO2_EN 0x10 +#define AXE_GPIO2 0x20 +#define AXE_GPIO_RELOAD_EEPROM 0x80 + +#define AXE_PHY_MODE_MARVELL 0x00 +#define AXE_PHY_MODE_CICADA 0x01 +#define AXE_PHY_MODE_AGERE 0x02 +#define AXE_PHY_MODE_CICADA_V2 0x05 +#define AXE_PHY_MODE_AGERE_GMII 0x06 +#define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 +#define AXE_PHY_MODE_REALTEK_8211CL 0x0C +#define AXE_PHY_MODE_REALTEK_8211BN 0x0D +#define AXE_PHY_MODE_REALTEK_8251CL 0x0E +#define AXE_PHY_MODE_ATTANSIC 0x40 + +/* AX88772A/AX88772B only. */ +#define AXE_SW_PHY_SELECT_EXT 0x0000 +#define AXE_SW_PHY_SELECT_EMBEDDED 0x0001 +#define AXE_SW_PHY_SELECT_AUTO 0x0002 +#define AXE_SW_PHY_SELECT_SS_MII 0x0004 +#define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008 +#define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C +#define AXE_SW_PHY_SELECT_SS_ENB 0x0010 + +/* AX88772A/AX88772B VLAN control. */ +#define AXE_VLAN_CTRL_ENB 0x00001000 +#define AXE_VLAN_CTRL_STRIP 0x00002000 +#define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF +#define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000 + +#define AXE_RXCSUM_IP 0x0001 +#define AXE_RXCSUM_IPVE 0x0002 +#define AXE_RXCSUM_IPV6E 0x0004 +#define AXE_RXCSUM_TCP 0x0008 +#define AXE_RXCSUM_UDP 0x0010 +#define AXE_RXCSUM_ICMP 0x0020 +#define AXE_RXCSUM_IGMP 0x0040 +#define AXE_RXCSUM_ICMP6 0x0080 +#define AXE_RXCSUM_TCPV6 0x0100 +#define AXE_RXCSUM_UDPV6 0x0200 +#define AXE_RXCSUM_ICMPV6 0x0400 +#define AXE_RXCSUM_IGMPV6 0x0800 +#define AXE_RXCSUM_ICMP6V6 0x1000 +#define AXE_RXCSUM_FOPC 0x8000 + +#define AXE_RXCSUM_64TE 0x0100 +#define AXE_RXCSUM_PPPOE 0x0200 +#define AXE_RXCSUM_RPCE 0x8000 + +#define AXE_TXCSUM_IP 0x0001 +#define AXE_TXCSUM_TCP 0x0002 +#define AXE_TXCSUM_UDP 0x0004 +#define AXE_TXCSUM_ICMP 0x0008 +#define AXE_TXCSUM_IGMP 0x0010 +#define AXE_TXCSUM_ICMP6 0x0020 +#define AXE_TXCSUM_TCPV6 0x0100 +#define AXE_TXCSUM_UDPV6 0x0200 +#define AXE_TXCSUM_ICMPV6 0x0400 +#define AXE_TXCSUM_IGMPV6 0x0800 +#define AXE_TXCSUM_ICMP6V6 0x1000 + +#define AXE_TXCSUM_64TE 0x0001 +#define AXE_TXCSUM_PPPOE 0x0002 + +#define AXE_BULK_BUF_SIZE 16384 /* bytes */ + +#define AXE_CTL_READ 0x01 +#define AXE_CTL_WRITE 0x02 + +#define AXE_CONFIG_IDX 0 /* config number 1 */ +#define AXE_IFACE_IDX 0 + +/* EEPROM Map. */ +#define AXE_EEPROM_772B_NODE_ID 0x04 +#define AXE_EEPROM_772B_PHY_PWRCFG 0x18 + +struct ax88772b_mfb { + int byte_cnt; + int threshold; + int size; +}; +#define AX88772B_MFB_2K 0 +#define AX88772B_MFB_4K 1 +#define AX88772B_MFB_6K 2 +#define AX88772B_MFB_8K 3 +#define AX88772B_MFB_16K 4 +#define AX88772B_MFB_20K 5 +#define AX88772B_MFB_24K 6 +#define AX88772B_MFB_32K 7 + +struct axe_sframe_hdr { + uint16_t len; +#define AXE_HDR_LEN_MASK 0xFFFF + uint16_t ilen; +} __packed; + +#define AXE_TX_CSUM_PSEUDO_HDR 0x4000 +#define AXE_TX_CSUM_DIS 0x8000 + +/* + * When RX checksum offloading is enabled, AX88772B uses new RX header + * format and it's not compatible with previous RX header format. In + * addition, IP header align option should be enabled to get correct + * frame size including RX header. Total transferred size including + * the RX header is multiple of 4 and controller will pad necessary + * bytes if the length is not multiple of 4. + * This driver does not enable partial checksum feature which will + * compute 16bit checksum from 14th byte to the end of the frame. If + * this feature is enabled, computed checksum value is embedded into + * RX header which in turn means it uses different RX header format. + */ +struct axe_csum_hdr { + uint16_t len; +#define AXE_CSUM_HDR_LEN_MASK 0x07FF +#define AXE_CSUM_HDR_CRC_ERR 0x1000 +#define AXE_CSUM_HDR_MII_ERR 0x2000 +#define AXE_CSUM_HDR_RUNT 0x4000 +#define AXE_CSUM_HDR_BMCAST 0x8000 + uint16_t ilen; + uint16_t cstatus; +#define AXE_CSUM_HDR_VLAN_MASK 0x0007 +#define AXE_CSUM_HDR_VLAN_STRIP 0x0008 +#define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070 +#define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100 +#define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200 +#define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400 +#define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800 +#define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00 +#define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000 +#define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400 +#define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00 +#define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000 +#define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000 + +#ifdef AXE_APPEND_PARTIAL_CSUM + /* + * These members present only when partial checksum + * offloading is enabled. The checksum value is simple + * 16bit sum of received frame starting at offset 14 of + * the frame to the end of the frame excluding FCS bytes. + */ + uint16_t csum_value; + uint16_t dummy; +#endif +} __packed; + +#define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK) + +#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) + +/* The interrupt endpoint is currently unused by the ASIX part. */ +enum { + AXE_BULK_DT_WR, + AXE_BULK_DT_RD, + AXE_N_TRANSFER, +}; + +struct axe_softc { + struct usb_ether sc_ue; + struct mtx sc_mtx; + struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; + int sc_phyno; + + int sc_flags; +#define AXE_FLAG_LINK 0x0001 +#define AXE_FLAG_STD_FRAME 0x0010 +#define AXE_FLAG_CSUM_FRAME 0x0020 +#define AXE_FLAG_772 0x1000 /* AX88772 */ +#define AXE_FLAG_772A 0x2000 /* AX88772A */ +#define AXE_FLAG_772B 0x4000 /* AX88772B */ +#define AXE_FLAG_178 0x8000 /* AX88178 */ + + uint8_t sc_ipgs[3]; + uint8_t sc_phyaddrs[2]; + uint16_t sc_pwrcfg; + uint16_t sc_lenmask; +}; + +#define AXE_IS_178_FAMILY(sc) \ + ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \ + AXE_FLAG_178)) + +#define AXE_IS_772(sc) \ + ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B)) + +#define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) +#define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) diff --git a/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axge.c b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axge.c new file mode 100644 index 0000000000..dae8c9e483 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axge.c @@ -0,0 +1,1111 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2013-2014 Kevin Lo + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * ASIX Electronics AX88178A/AX88179/AX88179A USB 2.0/3.0 gigabit ethernet + * driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include "usbdevs.h" + +#define USB_DEBUG_VAR axge_debug +#include +#include + +#include +#include + +#include "miibus_if.h" + +/* + * Various supported device vendors/products. + */ + +static const STRUCT_USB_HOST_ID axge_devs[] = { +#define AXGE_DEV(v,p,i,...) \ + { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), __VA_ARGS__ } + AXGE_DEV(ASIX, AX88178A, AXGE_FLAG_178A), + AXGE_DEV(ASIX, AX88179, AXGE_FLAG_179, USB_DEV_BCD_LTEQ(0x0100)), + AXGE_DEV(ASIX, AX88179, AXGE_FLAG_179A, USB_DEV_BCD_GTEQ(0x0200)), + AXGE_DEV(BELKIN, B2B128, AXGE_FLAG_179), + AXGE_DEV(DLINK, DUB1312, AXGE_FLAG_179), + AXGE_DEV(LENOVO, GIGALAN, AXGE_FLAG_179), + AXGE_DEV(SITECOMEU, LN032, AXGE_FLAG_179), +#undef AXGE_DEV +}; + +static const struct { + uint8_t ctrl; + uint8_t timer_l; + uint8_t timer_h; + uint8_t size; + uint8_t ifg; +} __packed axge_bulk_size[] = { + { 7, 0x4f, 0x00, 0x12, 0xff }, + { 7, 0x20, 0x03, 0x16, 0xff }, + { 7, 0xae, 0x07, 0x18, 0xff }, + { 7, 0xcc, 0x4c, 0x18, 0x08 } +}; + +/* prototypes */ + +static device_probe_t axge_probe; +static device_attach_t axge_attach; +static device_detach_t axge_detach; + +static usb_callback_t axge_bulk_read_callback; +static usb_callback_t axge_bulk_write_callback; + +static miibus_readreg_t axge_miibus_readreg; +static miibus_writereg_t axge_miibus_writereg; +static miibus_statchg_t axge_miibus_statchg; + +static uether_fn_t axge_attach_post; +static uether_fn_t axge_init; +static uether_fn_t axge_stop; +static uether_fn_t axge_start; +static uether_fn_t axge_tick; +static uether_fn_t axge_rxfilter; + +static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, + uint16_t, void *, int); +static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, + uint16_t, void *, int); +static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); +static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, + uint16_t); +static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, + uint8_t); +static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, + uint16_t, uint16_t); +static void axge_chip_init(struct axge_softc *); +static void axge_reset(struct axge_softc *); + +static int axge_attach_post_sub(struct usb_ether *); +static int axge_ifmedia_upd(if_t); +static void axge_ifmedia_sts(if_t, struct ifmediareq *); +static int axge_ioctl(if_t, u_long, caddr_t); +static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); +static void axge_rxeof(struct usb_ether *, struct usb_page_cache *, + unsigned, unsigned, uint32_t); +static void axge_csum_cfg(struct usb_ether *); + +#define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) + +#ifdef USB_DEBUG +static int axge_debug = 0; + +static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, + "USB axge"); +SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0, + "Debug level"); +#endif + +static const struct usb_config axge_config[AXGE_N_TRANSFER] = { + [AXGE_BULK_DT_WR] = { + .type = UE_BULK, + .endpoint = UE_ADDR_ANY, + .direction = UE_DIR_OUT, + .frames = AXGE_N_FRAMES, + .bufsize = AXGE_N_FRAMES * MCLBYTES, + .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, + .callback = axge_bulk_write_callback, + .timeout = 10000, /* 10 seconds */ + }, + [AXGE_BULK_DT_RD] = { + .type = UE_BULK, + .endpoint = UE_ADDR_ANY, + .direction = UE_DIR_IN, + .bufsize = 65536, + .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, + .callback = axge_bulk_read_callback, + .timeout = 0, /* no timeout */ + }, +}; + +static device_method_t axge_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, axge_probe), + DEVMETHOD(device_attach, axge_attach), + DEVMETHOD(device_detach, axge_detach), + + /* MII interface. */ + DEVMETHOD(miibus_readreg, axge_miibus_readreg), + DEVMETHOD(miibus_writereg, axge_miibus_writereg), + DEVMETHOD(miibus_statchg, axge_miibus_statchg), + + DEVMETHOD_END +}; + +static driver_t axge_driver = { + .name = "axge", + .methods = axge_methods, + .size = sizeof(struct axge_softc), +}; + +DRIVER_MODULE(axge, uhub, axge_driver, NULL, NULL); +DRIVER_MODULE(miibus, axge, miibus_driver, NULL, NULL); +MODULE_DEPEND(axge, uether, 1, 1, 1); +MODULE_DEPEND(axge, usb, 1, 1, 1); +MODULE_DEPEND(axge, ether, 1, 1, 1); +MODULE_DEPEND(axge, miibus, 1, 1, 1); +MODULE_VERSION(axge, 1); +USB_PNP_HOST_INFO(axge_devs); + +static const struct usb_ether_methods axge_ue_methods = { + .ue_attach_post = axge_attach_post, + .ue_attach_post_sub = axge_attach_post_sub, + .ue_start = axge_start, + .ue_init = axge_init, + .ue_stop = axge_stop, + .ue_tick = axge_tick, + .ue_setmulti = axge_rxfilter, + .ue_setpromisc = axge_rxfilter, + .ue_mii_upd = axge_ifmedia_upd, + .ue_mii_sts = axge_ifmedia_sts, +}; + +static int +axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, + uint16_t val, void *buf, int len) +{ + struct usb_device_request req; + + AXGE_LOCK_ASSERT(sc, MA_OWNED); + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = cmd; + USETW(req.wValue, val); + USETW(req.wIndex, index); + USETW(req.wLength, len); + + return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); +} + +static void +axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, + uint16_t val, void *buf, int len) +{ + struct usb_device_request req; + + AXGE_LOCK_ASSERT(sc, MA_OWNED); + + req.bmRequestType = UT_WRITE_VENDOR_DEVICE; + req.bRequest = cmd; + USETW(req.wValue, val); + USETW(req.wIndex, index); + USETW(req.wLength, len); + + if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { + /* Error ignored. */ + } +} + +static uint8_t +axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) +{ + uint8_t val; + + axge_read_mem(sc, cmd, 1, reg, &val, 1); + return (val); +} + +static uint16_t +axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, + uint16_t reg) +{ + uint8_t val[2]; + + axge_read_mem(sc, cmd, index, reg, &val, 2); + return (UGETW(val)); +} + +static void +axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) +{ + axge_write_mem(sc, cmd, 1, reg, &val, 1); +} + +static void +axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, + uint16_t reg, uint16_t val) +{ + uint8_t temp[2]; + + USETW(temp, val); + axge_write_mem(sc, cmd, index, reg, &temp, 2); +} + +static int +axge_miibus_readreg(device_t dev, int phy, int reg) +{ + struct axge_softc *sc; + uint16_t val; + int locked; + + sc = device_get_softc(dev); + locked = mtx_owned(&sc->sc_mtx); + if (!locked) + AXGE_LOCK(sc); + + val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy); + + if (!locked) + AXGE_UNLOCK(sc); + + return (val); +} + +static int +axge_miibus_writereg(device_t dev, int phy, int reg, int val) +{ + struct axge_softc *sc; + int locked; + + sc = device_get_softc(dev); + locked = mtx_owned(&sc->sc_mtx); + if (!locked) + AXGE_LOCK(sc); + + axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val); + + if (!locked) + AXGE_UNLOCK(sc); + + return (0); +} + +static void +axge_miibus_statchg(device_t dev) +{ + struct axge_softc *sc; + struct mii_data *mii; + if_t ifp; + uint8_t link_status, tmp[5]; + uint16_t val; + int locked; + + sc = device_get_softc(dev); + mii = GET_MII(sc); + locked = mtx_owned(&sc->sc_mtx); + if (!locked) + AXGE_LOCK(sc); + + ifp = uether_getifp(&sc->sc_ue); + if (mii == NULL || ifp == NULL || + (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) + goto done; + + sc->sc_flags &= ~AXGE_FLAG_LINK; + if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == + (IFM_ACTIVE | IFM_AVALID)) { + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_10_T: + case IFM_100_TX: + case IFM_1000_T: + sc->sc_flags |= AXGE_FLAG_LINK; + break; + default: + break; + } + } + + /* Lost link, do nothing. */ + if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) + goto done; + + link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); + + val = 0; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { + val |= MSR_FD; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) + val |= MSR_TFC; + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) + val |= MSR_RFC; + } + val |= MSR_RE; + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_1000_T: + val |= MSR_GM | MSR_EN_125MHZ; + if (link_status & PLSR_USB_SS) + memcpy(tmp, &axge_bulk_size[0], 5); + else if (link_status & PLSR_USB_HS) + memcpy(tmp, &axge_bulk_size[1], 5); + else + memcpy(tmp, &axge_bulk_size[3], 5); + break; + case IFM_100_TX: + val |= MSR_PS; + if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) + memcpy(tmp, &axge_bulk_size[2], 5); + else + memcpy(tmp, &axge_bulk_size[3], 5); + break; + case IFM_10_T: + memcpy(tmp, &axge_bulk_size[3], 5); + break; + } + /* Rx bulk configuration. */ + axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); +done: + if (!locked) + AXGE_UNLOCK(sc); +} + +static void +axge_chip_init(struct axge_softc *sc) +{ + /* Power up ethernet PHY. */ + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); + uether_pause(&sc->sc_ue, hz / 4); + axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, + AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); + uether_pause(&sc->sc_ue, hz / 10); + + if ((sc->sc_flags & AXGE_FLAG_179A) != 0) { + /* + * 179A chip has two firmware modes that each use different + * transfer layouts for Ethernet over USB. The newer fw mode has + * larger rx packet headers which seem to + * accomodate for ethernet frames up to 9K length and a VLAN + * field for hardware tagging, but is not backward compatible + * with 178A/179 bulk transfer code due to the change in size + * and field alignments. The other fw mode uses the same packet + * headers as the older 178A/179 chips, which this driver uses. + * + * As we do not currently have VLAN hw tagging or jumbo support + * in this driver anyway, we're ok forcing 179A into its compat + * mode by default. + */ + axge_write_cmd_1(sc, AXGE_FW_MODE, AXGE_FW_MODE_178A179, 0); + } +} + +static void +axge_reset(struct axge_softc *sc) +{ + struct usb_config_descriptor *cd; + usb_error_t err; + +#ifdef __HAIKU__ + // TODO + err = 1; +#else + cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); + + err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, + cd->bConfigurationValue); +#endif + if (err) + DPRINTF("reset failed (ignored)\n"); + + /* Wait a little while for the chip to get its brains in order. */ + uether_pause(&sc->sc_ue, hz / 100); + + /* Reinitialize controller to achieve full reset. */ + axge_chip_init(sc); +} + +static void +axge_attach_post(struct usb_ether *ue) +{ + struct axge_softc *sc; + + sc = uether_getsc(ue); + + /* Initialize controller and get station address. */ + axge_chip_init(sc); + axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, + ue->ue_eaddr, ETHER_ADDR_LEN); +} + +static int +axge_attach_post_sub(struct usb_ether *ue) +{ + if_t ifp; + int error; + + ifp = ue->ue_ifp; + if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); + if_setstartfn(ifp, uether_start); + if_setioctlfn(ifp, axge_ioctl); + if_setinitfn(ifp, uether_init); + if_setsendqlen(ifp, ifqmaxlen); + if_setsendqready(ifp); + + if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM, 0); + if_sethwassist(ifp, AXGE_CSUM_FEATURES); + if_setcapenable(ifp, if_getcapabilities(ifp)); + +#ifndef __HAIKU__ + bus_topo_lock(); +#endif + error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, + uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, + BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE); +#ifndef __HAIKU__ + bus_topo_unlock(); +#endif + + return (error); +} + +/* + * Set media options. + */ +static int +axge_ifmedia_upd(if_t ifp) +{ + struct axge_softc *sc; + struct mii_data *mii; + struct mii_softc *miisc; + int error; + + sc = if_getsoftc(ifp); + mii = GET_MII(sc); + AXGE_LOCK_ASSERT(sc, MA_OWNED); + + LIST_FOREACH(miisc, &mii->mii_phys, mii_list) + PHY_RESET(miisc); + error = mii_mediachg(mii); + + return (error); +} + +/* + * Report current media status. + */ +static void +axge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) +{ + struct axge_softc *sc; + struct mii_data *mii; + + sc = if_getsoftc(ifp); + mii = GET_MII(sc); + AXGE_LOCK(sc); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + AXGE_UNLOCK(sc); +} + +/* + * Probe for a AX88179 chip. + */ +static int +axge_probe(device_t dev) +{ + struct usb_attach_arg *uaa; + + uaa = device_get_ivars(dev); + if (uaa->usb_mode != USB_MODE_HOST) + return (ENXIO); + if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX) + return (ENXIO); + if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX) + return (ENXIO); + + return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa)); +} + +/* + * Attach the interface. Allocate softc structures, do ifmedia + * setup and ethernet/BPF attach. + */ +static int +axge_attach(device_t dev) +{ + struct usb_attach_arg *uaa; + struct axge_softc *sc; + struct usb_ether *ue; + uint8_t iface_index; + int error; + + uaa = device_get_ivars(dev); + sc = device_get_softc(dev); + ue = &sc->sc_ue; + + device_set_usb_desc(dev); + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + sc->sc_flags = USB_GET_DRIVER_INFO(uaa); + + iface_index = AXGE_IFACE_IDX; + error = usbd_transfer_setup(uaa->device, &iface_index, + sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx); + if (error) { + device_printf(dev, "allocating USB transfers failed\n"); + mtx_destroy(&sc->sc_mtx); + return (ENXIO); + } + + ue->ue_sc = sc; + ue->ue_dev = dev; + ue->ue_udev = uaa->device; + ue->ue_mtx = &sc->sc_mtx; + ue->ue_methods = &axge_ue_methods; + + error = uether_ifattach(ue); + if (error) { + device_printf(dev, "could not attach interface\n"); + goto detach; + } + return (0); /* success */ + +detach: + axge_detach(dev); + return (ENXIO); /* failure */ +} + +static int +axge_detach(device_t dev) +{ + struct axge_softc *sc; + struct usb_ether *ue; + uint16_t val; + + sc = device_get_softc(dev); + ue = &sc->sc_ue; + if (device_is_attached(dev)) { + /* wait for any post attach or other command to complete */ + usb_proc_drain(&ue->ue_tq); + + AXGE_LOCK(sc); + /* + * XXX + * ether_ifdetach(9) should be called first. + */ + axge_stop(ue); + /* Force bulk-in to return a zero-length USB packet. */ + val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR); + val |= EPPRCR_BZ | EPPRCR_IPRL; + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val); + /* Change clock. */ + axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0); + /* Disable MAC. */ + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0); + AXGE_UNLOCK(sc); + } + usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER); + uether_ifdetach(ue); + mtx_destroy(&sc->sc_mtx); + + return (0); +} + +static void +axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) +{ + struct axge_softc *sc; + struct usb_ether *ue; + struct usb_page_cache *pc; + int actlen; + + sc = usbd_xfer_softc(xfer); + ue = &sc->sc_ue; + usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); + + switch (USB_GET_STATE(xfer)) { + case USB_ST_TRANSFERRED: + pc = usbd_xfer_get_frame(xfer, 0); + axge_rx_frame(ue, pc, actlen); + + /* FALLTHROUGH */ + case USB_ST_SETUP: +tr_setup: + usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); + usbd_transfer_submit(xfer); + uether_rxflush(ue); + break; + + default: + if (error != USB_ERR_CANCELLED) { + usbd_xfer_set_stall(xfer); + goto tr_setup; + } + break; + } +} + +static void +axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) +{ + struct axge_softc *sc; + if_t ifp; + struct usb_page_cache *pc; + struct mbuf *m; + struct axge_frame_txhdr txhdr; + int nframes, pos; + + sc = usbd_xfer_softc(xfer); + ifp = uether_getifp(&sc->sc_ue); + + switch (USB_GET_STATE(xfer)) { + case USB_ST_TRANSFERRED: + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); + /* FALLTHROUGH */ + case USB_ST_SETUP: +tr_setup: + if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 || + (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) { + /* + * Don't send anything if there is no link or + * controller is busy. + */ + return; + } + + for (nframes = 0; nframes < AXGE_N_FRAMES && + !if_sendq_empty(ifp); nframes++) { + m = if_dequeue(ifp); + if (m == NULL) + break; +#ifndef __HAIKU__ /* shouldn't matter for our buffer management? */ + usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, + nframes); +#endif + pc = usbd_xfer_get_frame(xfer, nframes); + txhdr.mss = 0; + txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len)); + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0 && + (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0) + txhdr.len |= htole32(AXGE_CSUM_DISABLE); + + pos = 0; + usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr)); + pos += sizeof(txhdr); + usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); + pos += m->m_pkthdr.len; + + /* + * if there's a BPF listener, bounce a copy + * of this frame to him: + */ + BPF_MTAP(ifp, m); + + m_freem(m); + + /* Set frame length. */ + usbd_xfer_set_frame_len(xfer, nframes, pos); + } + if (nframes != 0) { + /* + * XXX + * Update TX packet counter here. This is not + * correct way but it seems that there is no way + * to know how many packets are sent at the end + * of transfer because controller combines + * multiple writes into single one if there is + * room in TX buffer of controller. + */ + if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes); + usbd_xfer_set_frames(xfer, nframes); + usbd_transfer_submit(xfer); + if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); + } + return; + /* NOTREACHED */ + default: + if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); + if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); + + if (error != USB_ERR_CANCELLED) { + usbd_xfer_set_stall(xfer); + goto tr_setup; + } + return; + } +} + +static void +axge_tick(struct usb_ether *ue) +{ + struct axge_softc *sc; + struct mii_data *mii; + + sc = uether_getsc(ue); + mii = GET_MII(sc); + AXGE_LOCK_ASSERT(sc, MA_OWNED); + + mii_tick(mii); +} + +static u_int +axge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) +{ + uint8_t *hashtbl = arg; + uint32_t h; + + h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; + hashtbl[h / 8] |= 1 << (h % 8); + + return (1); +} + +static void +axge_rxfilter(struct usb_ether *ue) +{ + struct axge_softc *sc; + if_t ifp; + uint16_t rxmode; + uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; + + sc = uether_getsc(ue); + ifp = uether_getifp(ue); + AXGE_LOCK_ASSERT(sc, MA_OWNED); + + /* + * Configure RX settings. + * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable + * inserting extra padding bytes. This wastes ethernet to USB host + * bandwidth as well as complicating RX handling logic. Current USB + * framework requires copying RX frames to mbufs so there is no need + * to worry about alignment. + */ + rxmode = RCR_DROP_CRCERR | RCR_START; + if (if_getflags(ifp) & IFF_BROADCAST) + rxmode |= RCR_ACPT_BCAST; + if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { + if (if_getflags(ifp) & IFF_PROMISC) + rxmode |= RCR_PROMISC; + rxmode |= RCR_ACPT_ALL_MCAST; + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); + return; + } + + rxmode |= RCR_ACPT_MCAST; + if_foreach_llmaddr(ifp, axge_hash_maddr, &hashtbl); + + axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); +} + +static void +axge_start(struct usb_ether *ue) +{ + struct axge_softc *sc; + + sc = uether_getsc(ue); + /* + * Start the USB transfers, if not already started. + */ + usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]); + usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]); +} + +static void +axge_init(struct usb_ether *ue) +{ + struct axge_softc *sc; + if_t ifp; + + sc = uether_getsc(ue); + ifp = uether_getifp(ue); + AXGE_LOCK_ASSERT(sc, MA_OWNED); + + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) + return; + + /* + * Cancel pending I/O and free all RX/TX buffers. + */ + axge_stop(ue); + + axge_reset(sc); + + /* Set MAC address. */ + axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, + if_getlladdr(ifp), ETHER_ADDR_LEN); + + axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); + axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); + + /* Configure TX/RX checksum offloading. */ + axge_csum_cfg(ue); + + /* Configure RX filters. */ + axge_rxfilter(ue); + + /* + * XXX + * Controller supports wakeup on link change detection, + * magic packet and wakeup frame recpetion. But it seems + * there is no framework for USB ethernet suspend/wakeup. + * Disable all wakeup functions. + */ + axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0); + (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR); + + /* Configure default medium type. */ + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD | + MSR_RFC | MSR_TFC | MSR_RE); + + usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); + + if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); + /* Switch to selected media. */ + axge_ifmedia_upd(ifp); +} + +static void +axge_stop(struct usb_ether *ue) +{ + struct axge_softc *sc; + if_t ifp; + uint16_t val; + + sc = uether_getsc(ue); + ifp = uether_getifp(ue); + + AXGE_LOCK_ASSERT(sc, MA_OWNED); + + val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR); + val &= ~MSR_RE; + axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); + + if (ifp != NULL) + if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); + sc->sc_flags &= ~AXGE_FLAG_LINK; + + /* + * Stop all the transfers, if not already stopped: + */ + usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]); + usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]); +} + +static int +axge_ioctl(if_t ifp, u_long cmd, caddr_t data) +{ + struct usb_ether *ue; + struct axge_softc *sc; + struct ifreq *ifr; + int error, mask, reinit; + + ue = if_getsoftc(ifp); + sc = uether_getsc(ue); + ifr = (struct ifreq *)data; + error = 0; + reinit = 0; + if (cmd == SIOCSIFCAP) { + AXGE_LOCK(sc); + mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); + if ((mask & IFCAP_TXCSUM) != 0 && + (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_TXCSUM); + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + if_sethwassistbits(ifp, AXGE_CSUM_FEATURES, 0); + else + if_sethwassistbits(ifp, 0, AXGE_CSUM_FEATURES); + reinit++; + } + if ((mask & IFCAP_RXCSUM) != 0 && + (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_RXCSUM); + reinit++; + } + if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING) + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); + else + reinit = 0; + AXGE_UNLOCK(sc); + if (reinit > 0) + uether_init(ue); + } else + error = uether_ioctl(ifp, cmd, data); + + return (error); +} + +static void +axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) +{ + struct axge_frame_rxhdr pkt_hdr; + uint32_t rxhdr; + uint32_t pos; + uint32_t pkt_cnt, pkt_end; + uint32_t hdr_off; + uint32_t pktlen; + + /* verify we have enough data */ + if (actlen < (int)sizeof(rxhdr)) + return; + + pos = 0; + + usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); + rxhdr = le32toh(rxhdr); + + pkt_cnt = rxhdr & 0xFFFF; + hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF; + + /* + * On older firmware: + * <----------------------- actlen ------------------------> + * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr] + * + * On newer firmware: + * <----------------------- actlen ----------------- + * [frame #0]...[frame #N][pkt_hdr #0][dummy_hdr]... + * --------------------------------> + * ...[pkt_hdr #N][dummy_hdr][rxhdr] + * + * Each RX frame would be aligned on 8 bytes boundary. If + * RCR_IPE bit is set in AXGE_RCR register, there would be 2 + * padding bytes and 6 dummy bytes(as the padding also should + * be aligned on 8 bytes boundary) for each RX frame to align + * IP header on 32bits boundary. Driver don't set RCR_IPE bit + * of AXGE_RCR register, so there should be no padding bytes + * which simplifies RX logic a lot. + * + * Further, newer firmware interweaves dummy headers that have + * pktlen == 0 and should be skipped without being seen as + * dropped frames. + */ + while (pkt_cnt--) { + /* verify the header offset */ + if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) { + DPRINTF("End of packet headers\n"); + break; + } + usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); + pkt_hdr.status = le32toh(pkt_hdr.status); + pktlen = AXGE_RXBYTES(pkt_hdr.status); + hdr_off += sizeof(pkt_hdr); + + /* Skip dummy packet header. */ + if (pktlen == 0) + continue; + + if (pos + pktlen > pkt_end) { + DPRINTF("Data position reached end\n"); + break; + } + + if (AXGE_RX_ERR(pkt_hdr.status) != 0) { + DPRINTF("Dropped a packet\n"); + if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); + } else + axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status); + pos += (pktlen + 7) & ~7; + } +} + +static void +axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned offset, + unsigned len, uint32_t status) +{ + if_t ifp; + struct mbuf *m; + + ifp = ue->ue_ifp; + if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { + if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); + return; + } + + if (len > MHLEN - ETHER_ALIGN) + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); + else + m = m_gethdr(M_NOWAIT, MT_DATA); + if (m == NULL) { + if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); + return; + } + m->m_pkthdr.rcvif = ifp; + m->m_len = m->m_pkthdr.len = len; + m->m_data += ETHER_ALIGN; + + usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); + + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { + if ((status & AXGE_RX_L3_CSUM_ERR) == 0 && + (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4) + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | + CSUM_IP_VALID; + if ((status & AXGE_RX_L4_CSUM_ERR) == 0 && + ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP || + (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) { + m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | + CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); + + (void)mbufq_enqueue(&ue->ue_rxq, m); +} + +static void +axge_csum_cfg(struct usb_ether *ue) +{ + struct axge_softc *sc; + if_t ifp; + uint8_t csum; + + sc = uether_getsc(ue); + AXGE_LOCK_ASSERT(sc, MA_OWNED); + ifp = uether_getifp(ue); + + csum = 0; + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; + axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); + + csum = 0; + if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) + csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; + axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); +} diff --git a/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axgereg.h b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axgereg.h new file mode 100644 index 0000000000..87e662b6cb --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/asix88xxx/dev/usb/net/if_axgereg.h @@ -0,0 +1,216 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2013-2014 Kevin Lo + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#define AXGE_ACCESS_MAC 0x01 +#define AXGE_ACCESS_PHY 0x02 +#define AXGE_ACCESS_WAKEUP 0x03 +#define AXGE_ACCESS_EEPROM 0x04 +#define AXGE_ACCESS_EFUSE 0x05 +#define AXGE_RELOAD_EEPROM_EFUSE 0x06 +#define AXGE_FW_MODE 0x08 +#define AXGE_WRITE_EFUSE_EN 0x09 +#define AXGE_WRITE_EFUSE_DIS 0x0A +#define AXGE_ACCESS_MFAB 0x10 + +#define AXGE_FW_MODE_178A179 0x0000 +#define AXGE_FW_MODE_179A 0x0001 + +/* Physical link status register */ +#define AXGE_PLSR 0x02 +#define PLSR_USB_FS 0x01 +#define PLSR_USB_HS 0x02 +#define PLSR_USB_SS 0x04 + +/* EEPROM address register */ +#define AXGE_EAR 0x07 + +/* EEPROM data low register */ +#define AXGE_EDLR 0x08 + +/* EEPROM data high register */ +#define AXGE_EDHR 0x09 + +/* EEPROM command register */ +#define AXGE_ECR 0x0a + +/* Rx control register */ +#define AXGE_RCR 0x0b +#define RCR_STOP 0x0000 +#define RCR_PROMISC 0x0001 +#define RCR_ACPT_ALL_MCAST 0x0002 +#define RCR_AUTOPAD_BNDRY 0x0004 +#define RCR_ACPT_BCAST 0x0008 +#define RCR_ACPT_MCAST 0x0010 +#define RCR_ACPT_PHY_MCAST 0x0020 +#define RCR_START 0x0080 +#define RCR_DROP_CRCERR 0x0100 +#define RCR_IPE 0x0200 +#define RCR_TX_CRC_PAD 0x0400 + +/* Node id register */ +#define AXGE_NIDR 0x10 + +/* Multicast filter array */ +#define AXGE_MFA 0x16 + +/* Medium status register */ +#define AXGE_MSR 0x22 +#define MSR_GM 0x0001 +#define MSR_FD 0x0002 +#define MSR_EN_125MHZ 0x0008 +#define MSR_RFC 0x0010 +#define MSR_TFC 0x0020 +#define MSR_RE 0x0100 +#define MSR_PS 0x0200 + +/* Monitor mode status register */ +#define AXGE_MMSR 0x24 +#define MMSR_RWLC 0x02 +#define MMSR_RWMP 0x04 +#define MMSR_RWWF 0x08 +#define MMSR_RW_FLAG 0x10 +#define MMSR_PME_POL 0x20 +#define MMSR_PME_TYPE 0x40 +#define MMSR_PME_IND 0x80 + +/* GPIO control/status register */ +#define AXGE_GPIOCR 0x25 + +/* Ethernet PHY power & reset control register */ +#define AXGE_EPPRCR 0x26 +#define EPPRCR_BZ 0x0010 +#define EPPRCR_IPRL 0x0020 +#define EPPRCR_AUTODETACH 0x1000 + +#define AXGE_RX_BULKIN_QCTRL 0x2e + +#define AXGE_CLK_SELECT 0x33 +#define AXGE_CLK_SELECT_BCS 0x01 +#define AXGE_CLK_SELECT_ACS 0x02 +#define AXGE_CLK_SELECT_ACSREQ 0x10 +#define AXGE_CLK_SELECT_ULR 0x08 + +/* COE Rx control register */ +#define AXGE_CRCR 0x34 +#define CRCR_IP 0x01 +#define CRCR_TCP 0x02 +#define CRCR_UDP 0x04 +#define CRCR_ICMP 0x08 +#define CRCR_IGMP 0x10 +#define CRCR_TCPV6 0x20 +#define CRCR_UDPV6 0x40 +#define CRCR_ICMPV6 0x80 + +/* COE Tx control register */ +#define AXGE_CTCR 0x35 +#define CTCR_IP 0x01 +#define CTCR_TCP 0x02 +#define CTCR_UDP 0x04 +#define CTCR_ICMP 0x08 +#define CTCR_IGMP 0x10 +#define CTCR_TCPV6 0x20 +#define CTCR_UDPV6 0x40 +#define CTCR_ICMPV6 0x80 + +/* Pause water level high register */ +#define AXGE_PWLHR 0x54 + +/* Pause water level low register */ +#define AXGE_PWLLR 0x55 + +#define AXGE_CONFIG_IDX 0 /* config number 1 */ +#define AXGE_IFACE_IDX 0 + +#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) + +/* The interrupt endpoint is currently unused by the ASIX part. */ +enum { + AXGE_BULK_DT_WR, + AXGE_BULK_DT_RD, + AXGE_N_TRANSFER, +}; + +#define AXGE_N_FRAMES 16 + +struct axge_frame_txhdr { + uint32_t len; +#define AXGE_TXLEN_MASK 0x0001FFFF +#define AXGE_VLAN_INSERT 0x20000000 +#define AXGE_CSUM_DISABLE 0x80000000 + uint32_t mss; +#define AXGE_MSS_MASK 0x00003FFF +#define AXGE_PADDING 0x80008000 +#define AXGE_VLAN_TAG_MASK 0xFFFF0000 +} __packed; + +#define AXGE_TXBYTES(x) ((x) & AXGE_TXLEN_MASK) + +#define AXGE_PHY_ADDR 3 + +struct axge_frame_rxhdr { + uint32_t status; +#define AXGE_RX_L4_CSUM_ERR 0x00000001 +#define AXGE_RX_L3_CSUM_ERR 0x00000002 +#define AXGE_RX_L4_TYPE_UDP 0x00000004 +#define AXGE_RX_L4_TYPE_ICMP 0x00000008 +#define AXGE_RX_L4_TYPE_IGMP 0x0000000C +#define AXGE_RX_L4_TYPE_TCP 0x00000010 +#define AXGE_RX_L4_TYPE_MASK 0x0000001C +#define AXGE_RX_L3_TYPE_IPV4 0x00000020 +#define AXGE_RX_L3_TYPE_IPV6 0x00000040 +#define AXGE_RX_L3_TYPE_MASK 0x00000060 +#define AXGE_RX_VLAN_IND_MASK 0x00000700 +#define AXGE_RX_GOOD_PKT 0x00000800 +#define AXGE_RX_VLAN_PRI_MASK 0x00007000 +#define AXGE_RX_MBCAST 0x00008000 +#define AXGE_RX_LEN_MASK 0x1FFF0000 +#define AXGE_RX_CRC_ERR 0x20000000 +#define AXGE_RX_MII_ERR 0x40000000 +#define AXGE_RX_DROP_PKT 0x80000000 +#define AXGE_RX_LEN_SHIFT 16 +} __packed; + +#define AXGE_RXBYTES(x) (((x) & AXGE_RX_LEN_MASK) >> AXGE_RX_LEN_SHIFT) +#define AXGE_RX_ERR(x) \ + ((x) & (AXGE_RX_CRC_ERR | AXGE_RX_MII_ERR | AXGE_RX_DROP_PKT)) + +struct axge_softc { + struct usb_ether sc_ue; + struct mtx sc_mtx; + struct usb_xfer *sc_xfer[AXGE_N_TRANSFER]; + + int sc_flags; +#define AXGE_FLAG_LINK 0x0001 /* got a link */ +#define AXGE_FLAG_178A 0x1000 /* AX88178A */ +#define AXGE_FLAG_179 0x2000 /* AX88179 */ +#define AXGE_FLAG_179A 0x4000 /* AX88179A */ +}; + +#define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) +#define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) +#define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) diff --git a/src/add-ons/kernel/drivers/network/ether/asix88xxx/glue.c b/src/add-ons/kernel/drivers/network/ether/asix88xxx/glue.c new file mode 100644 index 0000000000..a3db47b7e8 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/ether/asix88xxx/glue.c @@ -0,0 +1,44 @@ +/* + * Copyright 2025, Haiku, Inc. All rights reserved. + * Distributed under the terms of the MIT license. + */ + + +#include + + +extern driver_t* DRIVER_MODULE_NAME(axe, uhub); +extern driver_t* DRIVER_MODULE_NAME(axge, uhub); + +extern driver_t *DRIVER_MODULE_NAME(axphy, miibus); +extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus); + +HAIKU_FBSD_DRIVERS_GLUE(asix88xxx) +HAIKU_DRIVER_REQUIREMENTS(0); +NO_HAIKU_CHECK_DISABLE_INTERRUPTS(); +NO_HAIKU_REENABLE_INTERRUPTS(); + + +driver_t * +__haiku_select_miibus_driver(device_t dev) +{ + driver_t *drivers[] = { + DRIVER_MODULE_NAME(axphy, miibus), + DRIVER_MODULE_NAME(ukphy, miibus), + NULL + }; + + return __haiku_probe_drivers(dev, drivers); +} + + +void +__haiku_init_hardware() +{ + driver_t *usb_drivers[] = { + DRIVER_MODULE_NAME(axe, uhub), + DRIVER_MODULE_NAME(axge, uhub), + NULL + }; + _fbsd_init_hardware_uhub(usb_drivers); +}