intel_extreme: sandy/ivybridge DP links to screens are now programmed to the actual mode if possible
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@@ -857,6 +857,12 @@ struct intel_free_graphics_memory {
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#define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_DISP_PORT_WIDTH_SHIFT 19
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#define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT)
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#define INTEL_DISP_PORT_WIDTH_1 0
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#define INTEL_DISP_PORT_WIDTH_2 1
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#define INTEL_DISP_PORT_WIDTH_4 2
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#define INTEL_TRANSCODER_A_DP_CTL (0x0300 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_B_DP_CTL (0x1300 | REGS_SOUTH_TRANSCODER_PORT)
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#define INTEL_TRANSCODER_C_DP_CTL (0x2300 | REGS_SOUTH_TRANSCODER_PORT)
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