diff --git a/headers/private/graphics/neomagic/DriverInterface.h b/headers/private/graphics/neomagic/DriverInterface.h new file mode 100644 index 0000000000..5d7fc76921 --- /dev/null +++ b/headers/private/graphics/neomagic/DriverInterface.h @@ -0,0 +1,263 @@ +/* + Copyright 1999, Be Incorporated. All Rights Reserved. + This file may be used under the terms of the Be Sample Code License. + + Other authors: + Rudolf Cornelissen 4/2003- +*/ + +#ifndef DRIVERINTERFACE_H +#define DRIVERINTERFACE_H + +#include +#include "video_overlay.h" +#include +#include +#include + +#define DRIVER_PREFIX "nm" // apsed + +/* + Internal driver state (also for sharing info between driver and accelerant) +*/ +#if defined(__cplusplus) +extern "C" { +#endif + +typedef struct { + sem_id sem; + int32 ben; +} benaphore; + +#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; +#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); +#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); +#define DELETE_BEN(x) delete_sem(x.sem); + + +#define MN_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ + +/*dualhead extensions to flags*/ +#define DUALHEAD_OFF (0<<6) +#define DUALHEAD_CLONE (1<<6) +#define DUALHEAD_ON (2<<6) +#define DUALHEAD_SWITCH (3<<6) +#define DUALHEAD_BITS (3<<6) +#define DUALHEAD_CAPABLE (1<<8) +#define TV_BITS (3<<9) +#define TV_MON (0<<9 +#define TV_PAL (1<<9) +#define TV_NTSC (2<<9) +#define TV_CAPABLE (1<<11) + +#define SKD_MOVE_CURSOR 0x00000001 +#define SKD_PROGRAM_CLUT 0x00000002 +#define SKD_SET_START_ADDR 0x00000004 +#define SKD_SET_CURSOR 0x00000008 +#define SKD_HANDLER_INSTALLED 0x80000000 + +enum { + MN_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, + MN_GET_PCI, + MN_SET_PCI, + MN_DEVICE_NAME, + MN_RUN_INTERRUPTS, + MN_ISA_OUT, + MN_ISA_IN +}; + +/* max. number of overlay buffers */ +#define MAXBUFFERS 3 +/* max. pixelclock speed the BES supports */ +#define BESMAXSPEED 135000 + +/* internal used info on overlay buffers */ +typedef struct +{ + uint16 slopspace; + uint32 size; +} int_buf_info; + +typedef struct settings { // apsed, see comments in nm.settings + // for driver + char accelerant[B_FILE_NAME_LENGTH]; + bool dumprom; + // for accelerant + uint32 logmask; + uint32 memory; + bool usebios; + bool hardcursor; +} settings; + +/*shared info*/ +typedef struct { + /*a few ID things*/ + uint16 vendor_id; /* PCI vendor ID, from pci_info */ + uint16 device_id; /* PCI device ID, from pci_info */ + uint8 revision; /* PCI device revsion, from pci_info */ + + /* bug workaround for 4.5.0 */ + uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ + uint32 * clone_bugfix_regs; + uint32 * clone_bugfix_regs2; + + /*memory mappings*/ + area_id regs_area, regs2_area; /* Kernel's area_id for the memory mapped registers. + It will be cloned into the accelerant's address + space. */ + + area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ + area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ + area_id dma_buffer_area; /* Area assigned for dma*/ + + void *framebuffer; /* As viewed from virtual memory */ + void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ + + void *pseudo_dma; /* As viewed from virtual memory */ + + void *dma_buffer; /* buffer for dma*/ + void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ + + /*screenmode list*/ + area_id mode_area; /* Contains the list of display modes the driver supports */ + uint32 mode_count; /* Number of display modes in the list */ + + /*flags - used by driver*/ + uint32 flags; + + /*vblank semaphore*/ + sem_id vblank; /* The vertical blank semaphore. Ownership will be + transfered to the team opening the device first */ + /*cursor information*/ + struct { + uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ + uint16 hot_y; /* is 0,0 */ + uint16 x; /* The location of the cursor hot spot on the */ + uint16 y; /* desktop */ + uint16 width; /* Width and height of the cursor shape (always 16!) */ + uint16 height; + bool is_visible; /* Is the cursor currently displayed? */ + } cursor; + + /*colour lookup table*/ + uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ + + /*more display mode stuff*/ + display_mode dm; /* current display mode configuration: head1 */ + bool acc_mode; /* signals (non)accelerated mode */ + + /*frame buffer config - for BDirectScreen*/ + frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ + + /*acceleration engine*/ + struct { + uint32 count; /* last dwgsync slot used */ + uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ + benaphore lock; /* for serializing access to the acceleration engine */ + } engine; + + /* card info - information gathered from PINS (and other sources) */ + enum + { // card_type in order of date of nm chip design + NM2070 = 0, + NM2090, + NM2093, + NM2097, + NM2160, + NM2200, + NM2230, + NM2360, + NM2380, + G100, + G200 + }; + struct + { + /* specialised registers for predefined cardspecs */ + + /* general card information */ + uint32 card_type; /* see card_type enum above */ + + /* PINS */ + float f_ref; /* PLL reference-oscillator frequency (Mhz) */ + uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ + uint32 min_system_vco; + uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ + uint32 min_pixel_vco; + uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ + uint32 max_dac1_clock; /* dac1 limits (Mhz) */ + uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ + uint32 max_dac1_clock_16; + uint32 max_dac1_clock_24; + uint32 memory_size; /* memory (Kbytes) */ + uint32 curmem_size; /* memory (bytes) */ + uint16 max_crtc_width; /* CRTC max constraints */ + uint16 max_crtc_height; + uint8 panel_type; /* panel type */ + uint16 panel_width; /* panel size */ + uint16 panel_height; + uint8 outputs; /* in BIOS preselected output(s) */ + } ps; + + /*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/ + uint8 rom_mirror[32768]; + + /* apsed: some configuration settings from ~/config/settings/kernel/drivers/nm.settings if exists */ + settings settings; + + struct + { + overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ + int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ + overlay_token myToken; /* scaler is free/in use */ + benaphore lock; /* for creating buffers and aquiring overlay unit routines */ + } overlay; + +} shared_info; + +/* Read or write a value in PCI configuration space */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + uint32 offset; /* Offset to read/write */ + uint32 size; /* Number of bytes to transfer */ + uint32 value; /* The value read or written */ +} mn_get_set_pci; + +/* Read or write a value in ISA I/O space */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + uint16 adress; /* Offset to read/write */ + uint8 size; /* Number of bytes to transfer */ + uint16 data; /* The value read or written */ +} mn_in_out_isa; + +/* Set some boolean condition (like enabling or disabling interrupts) */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + bool do_it; /* state to set */ +} mn_set_bool_state; + +/* Retrieve the area_id of the kernel/accelerant shared info */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + area_id shared_info_area; /* area_id containing the shared information */ +} mn_get_private_data; + +/* Retrieve the device name. Usefull for when we have a file handle, but want +to know the device name (like when we are cloning the accelerant) */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + char *name; /* The name of the device, less the /dev root */ +} mn_device_name; + +enum { + + _WAIT_FOR_VBLANK = (1 << 0) +}; + +#if defined(__cplusplus) +} +#endif + + +#endif diff --git a/headers/private/graphics/neomagic/nm_macros.h b/headers/private/graphics/neomagic/nm_macros.h new file mode 100644 index 0000000000..ee17753e84 --- /dev/null +++ b/headers/private/graphics/neomagic/nm_macros.h @@ -0,0 +1,268 @@ +/* NM registers definitions and macros for access to */ + +/* PCI_config_space */ +#define NMCFG_DEVID 0x00 +#define NMCFG_DEVCTRL 0x04 +#define NMCFG_CLASS 0x08 +#define NMCFG_HEADER 0x0c +#define NMCFG_NMBASE2 0x10 +#define NMCFG_NMBASE1 0x14 +#define NMCFG_NMBASE3 0x18 // >= MYST +#define NMCFG_SUBSYSIDR 0x2c // >= MYST +#define NMCFG_ROMBASE 0x30 +#define NMCFG_CAP_PTR 0x34 // >= MIL2 +#define NMCFG_INTCTRL 0x3c +#define NMCFG_OPTION 0x40 +#define NMCFG_NM_INDEX 0x44 +#define NMCFG_NM_DATA 0x48 +#define NMCFG_SUBSYSIDW 0x4c // >= MYST +#define NMCFG_OPTION2 0x50 // >= G100 +#define NMCFG_OPTION3 0x54 // >= G400 +#define NMCFG_OPTION4 0x58 // >= G450 +#define NMCFG_PM_IDENT 0xdc // >= G100 +#define NMCFG_PM_CSR 0xe0 // >= G100 +#define NMCFG_AGP_IDENT 0xf0 // >= MIL2 +#define NMCFG_AGP_STS 0xf4 // >= MIL2 +#define NMCFG_AGP_CMD 0xf8 // >= MIL2 + +//new: +/* neomagic ISA direct registers */ +/* VGA standard registers: */ +#define NMISA8_ATTRINDW 0x03c0 +#define NMISA8_ATTRINDR 0x03c1 +#define NMISA8_ATTRDATW 0x03c0 +#define NMISA8_ATTRDATR 0x03c1 +#define NMISA8_SEQIND 0x03c4 +#define NMISA8_SEQDAT 0x03c5 +#define NMISA16_SEQIND 0x03c4 +#define NMISA8_CRTCIND 0x03d4 +#define NMISA8_CRTCDAT 0x03d5 +#define NMISA16_CRTCIND 0x03d4 +#define NMISA8_GRPHIND 0x03ce +#define NMISA8_GRPHDAT 0x03cf +#define NMISA16_GRPHIND 0x03ce + +/* neomagic ISA GENERAL direct registers */ +/* VGA standard registers: */ +#define NMISA8_MISCW 0x03c2 +#define NMISA8_MISCR 0x03cc +#define NMISA8_INSTAT1 0x03da + +/* neomagic ISA (DAC) COLOR direct registers (VGA palette RAM) */ +/* VGA standard registers: */ +#define NMISA8_PALMASK 0x03c6 +#define NMISA8_PALINDR 0x03c7 +#define NMISA8_PALINDW 0x03c8 +#define NMISA8_PALDATA 0x03c9 + +/* neomagic ISA CRTC indexed registers */ +/* VGA standard registers: */ +#define NMCRTCX_HTOTAL 0x00 +#define NMCRTCX_HDISPE 0x01 +#define NMCRTCX_HBLANKS 0x02 +#define NMCRTCX_HBLANKE 0x03 +#define NMCRTCX_HSYNCS 0x04 +#define NMCRTCX_HSYNCE 0x05 +#define NMCRTCX_VTOTAL 0x06 +#define NMCRTCX_OVERFLOW 0x07 +#define NMCRTCX_PRROWSCN 0x08 +#define NMCRTCX_MAXSCLIN 0x09 +#define NMCRTCX_VGACURCTRL 0x0a +#define NMCRTCX_FBSTADDH 0x0c +#define NMCRTCX_FBSTADDL 0x0d +#define NMCRTCX_VSYNCS 0x10 +#define NMCRTCX_VSYNCE 0x11 +#define NMCRTCX_VDISPE 0x12 +#define NMCRTCX_PITCHL 0x13 +#define NMCRTCX_VBLANKS 0x15 +#define NMCRTCX_VBLANKE 0x16 +#define NMCRTCX_MODECTL 0x17 +#define NMCRTCX_LINECOMP 0x18 +/* NeoMagic specific registers: */ +#define NMCRTCX_VEXT 0x70 /* >= NM2200 */ + +/* neomagic ISA SEQUENCER indexed registers */ +/* VGA standard registers: */ +#define NMSEQX_RESET 0x00 +#define NMSEQX_CLKMODE 0x01 +#define NMSEQX_MEMMODE 0x04 + +/* neomagic ISA ATTRIBUTE indexed registers */ +/* VGA standard registers: */ +#define NMATBX_MODECTL 0x10 +#define NMATBX_OSCANCOLOR 0x11 +#define NMATBX_COLPLANE_EN 0x12 +#define NMATBX_HORPIXPAN 0x13 +#define NMATBX_COLSEL 0x14 + +/* neomagic ISA GRAPHICS indexed registers */ +/* VGA standard registers: */ +#define NMGRPHX_ENSETRESET 0x01 +#define NMGRPHX_DATAROTATE 0x03 +#define NMGRPHX_READMAPSEL 0x04 +#define NMGRPHX_MODE 0x05 +#define NMGRPHX_MISC 0x06 +#define NMGRPHX_BITMASK 0x08 +/* NeoMagic specific registers: */ +#define NMGRPHX_GRPHXLOCK 0x09 +#define NMGRPHX_GENLOCK 0x0a +#define NMGRPHX_FBSTADDE 0x0e +#define NMGRPHX_CRTC_PITCHE 0x0f +#define NMGRPHX_IFACECTRL 0x11 +#define NMGRPHX_PANELCTRL1 0x20 +#define NMGRPHX_PANELTYPE 0x21 +#define NMGRPHX_PANELCTRL2 0x25 +#define NMGRPHX_PANELVCENT1 0x28 +#define NMGRPHX_PANELVCENT2 0x29 +#define NMGRPHX_PANELVCENT3 0x2a +#define NMGRPHX_PANELCTRL3 0x30 /* > NM2070 */ +#define NMGRPHX_PANELVCENT4 0x32 /* > NM2070 */ +#define NMGRPHX_PANELHCENT1 0x33 /* > NM2070 */ +#define NMGRPHX_PANELHCENT2 0x34 /* > NM2070 */ +#define NMGRPHX_PANELHCENT3 0x35 /* > NM2070 */ +#define NMGRPHX_PANELHCENT4 0x36 /* >= NM2160 */ +#define NMGRPHX_PANELVCENT5 0x37 /* >= NM2200 */ +#define NMGRPHX_PANELHCENT5 0x38 /* >= NM2200 */ +#define NMGRPHX_CURCTRL 0x82 +#define NMGRPHX_COLDEPTH 0x90 +/* (NeoMagic pixelPLL set C registers) */ +#define NMGRPHX_PLLC_NL 0x9b +#define NMGRPHX_PLLC_NH 0x8f /* >= NM2200 */ +#define NMGRPHX_PLLC_M 0x9f + +/* NeoMagic specific PCI cursor registers < NM2200 */ +#define NMCR1_CURCTRL 0x0100 +#define NMCR1_CURX 0x0104 +#define NMCR1_CURY 0x0108 +#define NMCR1_CURBGCOLOR 0x010c +#define NMCR1_CURFGCOLOR 0x0110 +#define NMCR1_CURADDRESS 0x0114 +/* NeoMagic specific PCI cursor registers >= NM2200 */ +#define NMCR1_22CURCTRL 0x1000 +#define NMCR1_22CURX 0x1004 +#define NMCR1_22CURY 0x1008 +#define NMCR1_22CURBGCOLOR 0x100c +#define NMCR1_22CURFGCOLOR 0x1010 +#define NMCR1_22CURADDRESS 0x1014 +//end new. + +/* NM ACCeleration registers */ +#define NMACC_DWGCTL 0x1C00 +#define NMACC_MACCESS 0x1C04 +#define NMACC_MCTLWTST 0x1C08 +#define NMACC_ZORG 0x1C0C +#define NMACC_PLNWT 0x1C1C +#define NMACC_BCOL 0x1C20 +#define NMACC_FCOL 0x1C24 +#define NMACC_XYSTRT 0x1C40 +#define NMACC_XYEND 0x1C44 +#define NMACC_SGN 0x1C58 +#define NMACC_LEN 0x1C5C +#define NMACC_AR0 0x1C60 +#define NMACC_AR3 0x1C6C +#define NMACC_AR5 0x1C74 +#define NMACC_CXBNDRY 0x1C80 +#define NMACC_FXBNDRY 0x1C84 +#define NMACC_YDSTLEN 0x1C88 +#define NMACC_PITCH 0x1C8C +#define NMACC_YDST 0x1C90 +#define NMACC_YDSTORG 0x1C94 +#define NMACC_YTOP 0x1C98 +#define NMACC_YBOT 0x1C9C +#define NMACC_CXLEFT 0x1CA0 +#define NMACC_CXRIGHT 0x1CA4 +#define NMACC_FXLEFT 0x1CA8 +#define NMACC_FXRIGHT 0x1CAC +#define NMACC_STATUS 0x1E14 +#define NMACC_ICLEAR 0x1E18 /* required for interrupt stuff */ +#define NMACC_IEN 0x1E1C /* required for interrupt stuff */ +#define NMACC_RST 0x1E40 +#define NMACC_MEMRDBK 0x1E44 +#define NMACC_OPMODE 0x1E54 +#define NMACC_PRIMADDRESS 0x1E58 +#define NMACC_PRIMEND 0x1E5C +#define NMACC_TEXORG 0x2C24 // >= G100 +#define NMACC_DWGSYNC 0x2C4C // >= G200 +#define NMACC_TEXORG1 0x2CA4 // >= G200 +#define NMACC_TEXORG2 0x2CA8 // >= G200 +#define NMACC_TEXORG3 0x2CAC // >= G200 +#define NMACC_TEXORG4 0x2CB0 // >= G200 +#define NMACC_SRCORG 0x2CB4 // >= G200 +#define NMACC_DSTORG 0x2CB8 // >= G200 + +/*NM BES (Back End Scaler) registers (>= G200) */ +#define NMBES_A1ORG 0x3D00 +#define NMBES_A2ORG 0x3D04 +#define NMBES_B1ORG 0x3D08 +#define NMBES_B2ORG 0x3D0C +#define NMBES_A1CORG 0x3D10 +#define NMBES_A2CORG 0x3D14 +#define NMBES_B1CORG 0x3D18 +#define NMBES_B2CORG 0x3D1C +#define NMBES_CTL 0x3D20 +#define NMBES_PITCH 0x3D24 +#define NMBES_HCOORD 0x3D28 +#define NMBES_VCOORD 0x3D2C +#define NMBES_HISCAL 0x3D30 +#define NMBES_VISCAL 0x3D34 +#define NMBES_HSRCST 0x3D38 +#define NMBES_HSRCEND 0x3D3C +#define NMBES_LUMACTL 0x3D40 +#define NMBES_V1WGHT 0x3D48 +#define NMBES_V2WGHT 0x3D4C +#define NMBES_HSRCLST 0x3D50 +#define NMBES_V1SRCLST 0x3D54 +#define NMBES_V2SRCLST 0x3D58 +#define NMBES_A1C3ORG 0x3D60 +#define NMBES_A2C3ORG 0x3D64 +#define NMBES_B1C3ORG 0x3D68 +#define NMBES_B2C3ORG 0x3D6C +#define NMBES_GLOBCTL 0x3DC0 +#define NMBES_STATUS 0x3DC4 + +/* Macros for convenient accesses to the NM chips */ + +#define NM_REG8(r_) ((vuint8 *)regs)[(r_)] +#define NM_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] + +/* read and write to PCI config space */ +#define CFGR(A) (mn_pci_access.offset=NMCFG_##A, ioctl(fd,MN_GET_PCI, &mn_pci_access,sizeof(mn_pci_access)), mn_pci_access.value) +#define CFGW(A,B) (mn_pci_access.offset=NMCFG_##A, mn_pci_access.value = B, ioctl(fd,MN_SET_PCI,&mn_pci_access,sizeof(mn_pci_access))) + +/* read and write from the powergraphics registers */ +#define ACCR(A) (NM_REG32(NMACC_##A)) +#define ACCW(A,B) (NM_REG32(NMACC_##A)=B) +#define ACCGO(A,B) (NM_REG32(NMACC_##A + 0x0100)=B) + +/* read and write from the backend scaler registers */ +#define BESR(A) (NM_REG32(NMBES_##A)) +#define BESW(A,B) (NM_REG32(NMBES_##A)=B) + +//new: +/* read and write from first CRTC (mapped) */ +#define CR1R(A) (NM_REG32(NMCR1_##A)) +#define CR1W(A,B) (NM_REG32(NMCR1_##A) = (B)) + +/* read and write from ISA I/O space */ +#define ISAWB(A,B)(mn_isa_access.adress=NMISA8_##A, mn_isa_access.data = (uint8)B, mn_isa_access.size = 1, ioctl(fd,MN_ISA_OUT, &mn_isa_access,sizeof(mn_isa_access))) +#define ISAWW(A,B)(mn_isa_access.adress=NMISA16_##A, mn_isa_access.data = B, mn_isa_access.size = 2, ioctl(fd,MN_ISA_OUT, &mn_isa_access,sizeof(mn_isa_access))) +#define ISARB(A) (mn_isa_access.adress=NMISA8_##A, ioctl(fd,MN_ISA_IN, &mn_isa_access,sizeof(mn_isa_access)), (uint8)mn_isa_access.data) +#define ISARW(A) (mn_isa_access.adress=NMISA16_##A, ioctl(fd,MN_ISA_IN, &mn_isa_access,sizeof(mn_isa_access)), mn_isa_access.data) + +/* read and write from ISA CRTC indexed registers */ +#define ISACRTCW(A,B)(ISAWW(CRTCIND, ((NMCRTCX_##A) | ((B) << 8)))) +#define ISACRTCR(A) (ISAWB(CRTCIND, (NMCRTCX_##A)), ISARB(CRTCDAT)) + +/* read and write from ISA GRAPHICS indexed registers */ +#define ISAGRPHW(A,B)(ISAWW(GRPHIND, ((NMGRPHX_##A) | ((B) << 8)))) +#define ISAGRPHR(A) (ISAWB(GRPHIND, (NMGRPHX_##A)), ISARB(GRPHDAT)) + +/* read and write from ISA SEQUENCER indexed registers */ +#define ISASEQW(A,B)(ISAWW(SEQIND, ((NMSEQX_##A) | ((B) << 8)))) +#define ISASEQR(A) (ISAWB(SEQIND, (NMSEQX_##A)), ISARB(SEQDAT)) + +/* read and write from ISA ATTRIBUTE indexed registers */ +/* define DUMMY to prevent compiler warnings */ +#define static uint8 DUMMY; +#define ISAATBW(A,B)(DUMMY = ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISAWB(ATTRDATW, (B))) +#define ISAATBR(A) (DUMMY = ISARB(INSTAT1), ISAWB(ATTRINDW, ((NMATBX_##A) | 0x20)), ISARB(ATTRDATR)) diff --git a/src/add-ons/kernel/drivers/graphics/Jamfile b/src/add-ons/kernel/drivers/graphics/Jamfile index 73cffdf7fc..0db40b4740 100644 --- a/src/add-ons/kernel/drivers/graphics/Jamfile +++ b/src/add-ons/kernel/drivers/graphics/Jamfile @@ -1,4 +1,5 @@ SubDir OBOS_TOP src add-ons kernel drivers graphics ; SubInclude OBOS_TOP src add-ons kernel drivers graphics matrox ; +SubInclude OBOS_TOP src add-ons kernel drivers graphics neomagic ; SubInclude OBOS_TOP src add-ons kernel drivers graphics nvidia ; diff --git a/src/add-ons/kernel/drivers/graphics/neomagic/Jamfile b/src/add-ons/kernel/drivers/graphics/neomagic/Jamfile new file mode 100644 index 0000000000..6f066a7c78 --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/neomagic/Jamfile @@ -0,0 +1,17 @@ +SubDir OBOS_TOP src add-ons kernel drivers graphics neomagic ; + +UsePrivateHeaders graphics ; +UsePrivateHeaders [ FDirName graphics neomagic ] ; + +R5KernelAddon nm.driver : kernel drivers bin : + driver.c +; + +# Link to kernel/drivers/dev/graphics +{ + local dir = [ FDirName $(OBOS_ADDON_DIR) kernel drivers dev graphics ] ; + local instDriver = nm.driver ; + MakeLocate $(instDriver) : $(dir) ; + RelSymLink $(instDriver) : nm.driver ; +} + diff --git a/src/add-ons/kernel/drivers/graphics/neomagic/driver.c b/src/add-ons/kernel/drivers/graphics/neomagic/driver.c new file mode 100644 index 0000000000..99a7fd5826 --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/neomagic/driver.c @@ -0,0 +1,889 @@ +/* + Copyright 1999, Be Incorporated. All Rights Reserved. + This file may be used under the terms of the Be Sample Code License. + + Other authors: + Mark Watson; + Apsed; + Rudolf Cornelissen 5/2002-6/2003. +*/ + +/* standard kernel driver stuff */ +#include +#include +#include +#include +#include +#include +#include // for strtoXX + +/* this is for the standardized portion of the driver API */ +/* currently only one operation is defined: B_GET_ACCELERANT_SIGNATURE */ +#include + +/* this is for sprintf() */ +#include + +/* this is for string compares */ +#include + +/* The private interface between the accelerant and the kernel driver. */ +#include "DriverInterface.h" +#include "nm_macros.h" + +#define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) +#define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) + +#define MAX_DEVICES 8 + +#define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" // apsed + +/* Tell the kernel what revision of the driver API we support */ +int32 api_version = B_CUR_DRIVER_API_VERSION; // apsed, was 2, is 2 in R5 + +/* these structures are private to the kernel driver */ +typedef struct device_info device_info; + +typedef struct { + timer te; /* timer entry for add_timer() */ + device_info *di; /* pointer to the owning device */ + bigtime_t when_target; /* when we're supposed to wake up */ +} timer_info; + +struct device_info { + uint32 is_open; /* a count of how many times the devices has been opened */ + area_id shared_area; /* the area shared between the driver and all of the accelerants */ + shared_info *si; /* a pointer to the shared area, for convenience */ + vuint32 *regs, *regs2; /* kernel's pointer to memory mapped registers */ + pci_info pcii; /* a convenience copy of the pci info for this device */ + char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ +}; + +typedef struct { + uint32 count; /* number of devices actually found */ + benaphore kernel; /* for serializing opens/closes */ + char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ + device_info di[MAX_DEVICES]; /* device specific stuff */ +} DeviceData; + +/* prototypes for our private functions */ +static status_t open_hook (const char* name, uint32 flags, void** cookie); +static status_t close_hook (void* dev); +static status_t free_hook (void* dev); +static status_t read_hook (void* dev, off_t pos, void* buf, size_t* len); +static status_t write_hook (void* dev, off_t pos, const void* buf, size_t* len); +static status_t control_hook (void* dev, uint32 msg, void *buf, size_t len); +static status_t map_device(device_info *di); +static void unmap_device(device_info *di); +static void probe_devices(void); +static int32 mn_interrupt(void *data); + +static DeviceData *pd; +static pci_module_info *pci_bus; +static isa_module_info *isa_bus; + +static device_hooks graphics_device_hooks = { + open_hook, + close_hook, + free_hook, + control_hook, + read_hook, + write_hook, + NULL, + NULL, + NULL, + NULL +}; + +#define VENDOR_ID 0x10c8 /* Neomagic inc. */ + +static uint16 mn_device_list[] = { + 0x0001, /* MagicGraph 128 (NM2070) */ + 0x0002, /* MagicGraph 128V (NM2090) 0x42 */ + 0x0003, /* MagicGraph 128ZV (NM2093) 0x43 */ + 0x0083, /* MagicGraph 128ZV+ (NM2097) */ + 0x0004, /* MagicGraph 128XD (NM2160) 0x44 */ + 0x0005, /* MagicMedia 256AV (NM2200) 0x45 */ + 0x0025, /* MagicMedia 256AV+ (NM2230) */ + 0x0006, /* MagicMedia 256ZX (NM2360) */ + 0x0016, /* MagicMedia 256XL+ (NM2380) */ + 0 +}; + +static struct { + uint16 vendor; + uint16 *devices; +} SupportedDevices[] = { + {VENDOR_ID, mn_device_list}, + {0x0000, NULL} +}; + +static settings current_settings = { // see comments in nm.settings + // for driver + DRIVER_PREFIX ".accelerant", + false, // dumprom + // for accelerant + 0x00000000, // logmask + 0, // memory + false, // usebios + false, // hardcursor +}; + +static void dumprom (void *rom, size_t size) +{ + int fd = open ("/boot/home/" DRIVER_PREFIX ".rom", O_WRONLY | O_CREAT, 0666); + if (fd < 0) return; + write (fd, rom, size); + close (fd); +} + +/*return 1, is interrupt has occured*/ +int caused_vbi(vuint32 * regs, vuint32 * regs2) +{ +// return (ACCR(STATUS)&0x20); +return 0; +} + +/*clear the interrupt*/ +void clear_vbi(vuint32 * regs, vuint32 * regs2) +{ +// ACCW(ICLEAR,0x20); +} + +void enable_vbi(vuint32 * regs, vuint32 * regs2) +{ +// ACCW(IEN,ACCR(IEN)|0x20); +} + +void disable_vbi(vuint32 * regs, vuint32 * regs2) +{ +// ACCW(IEN,(ACCR(IEN)&~0x20)); +// ACCW(ICLEAR,0x20); +} + + +/* + init_hardware() - Returns B_OK if one is + found, otherwise returns B_ERROR so the driver will be unloaded. +*/ +status_t +init_hardware(void) { + long pci_index = 0; + pci_info pcii; + bool found_one = FALSE; + + /* choke if we can't find the PCI bus */ + if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) + return B_ERROR; + + /* choke if we can't find the ISA bus */ + if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) + return B_ERROR; + + /* while there are more pci devices */ + while ((*pci_bus->get_nth_pci_info)(pci_index, &pcii) == B_NO_ERROR) { + int vendor = 0; + + /* if we match a supported vendor */ + while (SupportedDevices[vendor].vendor) { + if (SupportedDevices[vendor].vendor == pcii.vendor_id) { + uint16 *devices = SupportedDevices[vendor].devices; + /* while there are more supported devices */ + while (*devices) { + /* if we match a supported device */ + if (*devices == pcii.device_id ) { + + found_one = TRUE; + goto done; + } + /* next supported device */ + devices++; + } + } + vendor++; + } + /* next pci_info struct, please */ + pci_index++; + } + +done: + /* put away the module managers */ + put_module(B_PCI_MODULE_NAME); + put_module(B_ISA_MODULE_NAME); + + return (found_one ? B_OK : B_ERROR); +} + +status_t +init_driver(void) { + void *settings_handle; + + // get driver/accelerant settings, apsed + settings_handle = load_driver_settings (DRIVER_PREFIX ".settings"); + if (settings_handle != NULL) { + const char *item; + char *end; + uint32 value; + + // for driver + item = get_driver_parameter (settings_handle, "accelerant", "", ""); + if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.accelerant) - 1)) { + strcpy (current_settings.accelerant, item); + } + current_settings.dumprom = get_driver_boolean_parameter (settings_handle, "dumprom", false, false); + + // for accelerant + item = get_driver_parameter (settings_handle, "logmask", "0x00000000", "0x00000000"); + value = strtoul (item, &end, 0); + if (*end == '\0') current_settings.logmask = value; + + item = get_driver_parameter (settings_handle, "memory", "0", "0"); + value = strtoul (item, &end, 0); + if (*end == '\0') current_settings.memory = value; + + current_settings.hardcursor = get_driver_boolean_parameter (settings_handle, "hardcursor", false, false); + current_settings.usebios = get_driver_boolean_parameter (settings_handle, "usebios", false, false); + + unload_driver_settings (settings_handle); + } + + /* get a handle for the pci bus */ + if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) + return B_ERROR; + + /* get a handle for the isa bus */ + if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) + return B_ERROR; + + /* driver private data */ + pd = (DeviceData *)calloc(1, sizeof(DeviceData)); + if (!pd) { + put_module(B_PCI_MODULE_NAME); + put_module(B_ISA_MODULE_NAME); + return B_ERROR; + } + /* initialize the benaphore */ + INIT_BEN(pd->kernel); + /* find all of our supported devices */ + probe_devices(); + return B_OK; +} + +const char ** +publish_devices(void) { + /* return the list of supported devices */ + return (const char **)pd->device_names; +} + +device_hooks * +find_device(const char *name) { + int index = 0; + while (pd->device_names[index]) { + if (strcmp(name, pd->device_names[index]) == 0) + return &graphics_device_hooks; + index++; + } + return NULL; + +} + +void uninit_driver(void) { + + /* free the driver data */ + DELETE_BEN(pd->kernel); + free(pd); + pd = NULL; + + /* put the pci modules away */ + put_module(B_PCI_MODULE_NAME); + put_module(B_ISA_MODULE_NAME); +} + +static status_t map_device(device_info *di) +{ + char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ + shared_info *si = di->si; + uint32 tmpUlong; + pci_info *pcii = &(di->pcii); + system_info sysinfo; + + /*variables for making copy of ROM*/ + char * rom_temp; + area_id rom_area; + + int frame_buffer = 0; + /* only NM2097 and later cards have two register area's: + * older cards have their PCI registers in the frame_buffer space */ + int registers = 1; + int registers2 = 2; + + /* enable memory mapped IO, disable VGA I/O - this is standard*/ + tmpUlong = get_pci(PCI_command, 4); + /* make sure ISA access is enabled: all Neomagic cards still partly rely on this */ + tmpUlong |= PCI_command_io; + /* make sure PCI access is enabled */ + tmpUlong |= PCI_command_memory; + tmpUlong |= PCI_command_master; + set_pci(PCI_command, 4, tmpUlong); + + /*work out which version of BeOS is running*/ + get_system_info(&sysinfo); + if (sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ + { + si->use_clone_bugfix = 1; + } + else + { + si->use_clone_bugfix = 0; + } + + /* map card's register area's */ + switch (di->pcii.device_id) + { + case 0x0001: + case 0x0002: + case 0x0003: + /* NM2070, NM2090 and NM2093 have no seperate register area's, + * so do nothing here. */ + break; + default: + /* work out a name for the register mapping */ + sprintf(buffer, DEVICE_FORMAT " regs", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* get a virtual memory address for the registers*/ + si->regs_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[registers], + di->pcii.u.h0.base_register_sizes[registers], + B_ANY_KERNEL_ADDRESS, + (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), + (void **)&(di->regs)); + si->clone_bugfix_regs = (uint32 *) di->regs; + + /* if mapping registers to vmem failed then pass on error */ + if (si->regs_area < 0) return si->regs_area; + + /* work out a name for the register mapping */ + sprintf(buffer, DEVICE_FORMAT " regs2", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + si->regs2_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[registers2], + di->pcii.u.h0.base_register_sizes[registers2], + B_ANY_KERNEL_ADDRESS, + (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), + (void **)&(di->regs2)); + si->clone_bugfix_regs2 = (uint32 *) di->regs2; + + /* if mapping registers to vmem failed then pass on error */ + if (si->regs2_area < 0) + { + delete_area(si->regs_area); + si->regs_area = -1; + + return si->regs2_area; + } + break; + } + + /* work out a name for the ROM mapping*/ + sprintf(buffer, DEVICE_FORMAT " rom", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /*place ROM over the fbspace (this is definately safe)*/ + tmpUlong = di->pcii.u.h0.base_registers[frame_buffer]; + tmpUlong |= 0x00000001; + set_pci(PCI_rom_base, 4, tmpUlong); + + rom_area = map_physical_memory( + buffer, + (void *)di->pcii.u.h0.base_registers[frame_buffer], + 32768, + B_ANY_KERNEL_ADDRESS, + B_READ_AREA, + (void **)&(rom_temp) + ); + + /* if mapping ROM to vmem failed then clean up and pass on error */ + if (rom_area < 0) { + if (si->regs_area >= 0) + { + delete_area(si->regs_area); + si->regs_area = -1; + } + if (si->regs2_area >= 0) + { + delete_area(si->regs2_area); + si->regs2_area = -1; + } + return rom_area; + } + + /* make a copy of ROM for future reference*/ + memcpy (si->rom_mirror, rom_temp, 32768); + if (current_settings.dumprom) dumprom (rom_temp, 32768); + + /*disable ROM and delete the area*/ + set_pci(PCI_rom_base,4,0); + delete_area(rom_area); + + /* work out a name for the framebuffer mapping*/ + sprintf(buffer, DEVICE_FORMAT " framebuffer", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* map the framebuffer into vmem, using Write Combining*/ + si->fb_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[frame_buffer], + di->pcii.u.h0.base_register_sizes[frame_buffer], + B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, + B_READ_AREA + B_WRITE_AREA, + &(si->framebuffer)); + + /*if failed with write combining try again without*/ + if (si->fb_area < 0) { + si->fb_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[frame_buffer], + di->pcii.u.h0.base_register_sizes[frame_buffer], + B_ANY_KERNEL_BLOCK_ADDRESS, + B_READ_AREA + B_WRITE_AREA, + &(si->framebuffer)); + } + + /* if there was an error, delete our other areas and pass on error*/ + if (si->fb_area < 0) + { + if (si->regs_area >= 0) + { + delete_area(si->regs_area); + si->regs_area = -1; + } + if (si->regs2_area >= 0) + { + delete_area(si->regs2_area); + si->regs2_area = -1; + } + return si->fb_area; + } + + /* older cards have their registers in the framebuffer area */ + switch (di->pcii.device_id) + { + case 0x0001: + /* NM2070 cards */ + di->regs = (uint32 *)((uint8 *)si->framebuffer + 0x100000); + break; + case 0x0002: + case 0x0003: + /* NM2090 and NM2093 cards */ + di->regs = (uint32 *)((uint8 *)si->framebuffer + 0x200000); + break; + } + + /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ + si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; + + // remember settings for use here and in accelerant + si->settings = current_settings; + + /* in any case, return the result */ + return si->fb_area; +} + +static void unmap_device(device_info *di) { + shared_info *si = di->si; + uint32 tmpUlong; + pci_info *pcii = &(di->pcii); + + /* disable memory mapped IO */ + tmpUlong = get_pci(PCI_command, 4); + tmpUlong &= 0xfffffffc; + set_pci(PCI_command, 4, tmpUlong); + /* delete the areas */ + if (si->regs2_area >= 0) delete_area(si->regs2_area); + if (si->regs_area >= 0) delete_area(si->regs_area); + if (si->fb_area >= 0) delete_area(si->fb_area); + si->regs2_area = si->regs_area = si->fb_area = -1; + si->framebuffer = NULL; + di->regs = NULL; +} + +static void probe_devices(void) { + uint32 pci_index = 0; + uint32 count = 0; + device_info *di = pd->di; + + /* while there are more pci devices */ + while ((count < MAX_DEVICES) && ((*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_NO_ERROR)) { + int vendor = 0; + + /* if we match a supported vendor */ + while (SupportedDevices[vendor].vendor) { + if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { + uint16 *devices = SupportedDevices[vendor].devices; + /* while there are more supported devices */ + while (*devices) { + /* if we match a supported device */ + if (*devices == di->pcii.device_id ) { + /* publish the device name */ + sprintf(di->name, "graphics/" DEVICE_FORMAT, + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* remember the name */ + pd->device_names[count] = di->name; + /* mark the driver as available for R/W open */ + di->is_open = 0; + /* mark areas as not yet created */ + di->shared_area = -1; + /* mark pointer to shared data as invalid */ + di->si = NULL; + /* inc pointer to device info */ + di++; + /* inc count */ + count++; + /* break out of these while loops */ + goto next_device; + } + /* next supported device */ + devices++; + } + } + vendor++; + } +next_device: + /* next pci_info struct, please */ + pci_index++; + } + /* propagate count */ + pd->count = count; + /* terminate list of device names with a null pointer */ + pd->device_names[pd->count] = NULL; +} + +static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, vuint32 *regs2, shared_info *si) { + uint32 handled = B_HANDLED_INTERRUPT; + /* release the vblank semaphore */ + if (si->vblank >= 0) { + int32 blocked; + if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { + release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); + handled = B_INVOKE_SCHEDULER; + } + } + return handled; +} + +static int32 +mn_interrupt(void *data) +{ + int32 handled = B_UNHANDLED_INTERRUPT; + device_info *di = (device_info *)data; + shared_info *si = di->si; + int32 *flags = &(si->flags); + vuint32 *regs, *regs2; + + /* is someone already handling an interrupt for this device? */ + if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) { + goto exit0; + } + /* get regs */ + regs = di->regs; + regs2 = di->regs2; + + /* was it a VBI? */ + if (caused_vbi(regs, regs2)) { + /*clear the interrupt*/ + clear_vbi(regs, regs2); + /*release the semaphore*/ + handled = thread_interrupt_work(flags, regs, regs2, si); + } + + /* note that we're not in the handler any more */ + atomic_and(flags, ~SKD_HANDLER_INSTALLED); + +exit0: + return handled; +} + +static status_t open_hook (const char* name, uint32 flags, void** cookie) { + int32 index = 0; + device_info *di; + shared_info *si; + thread_id thid; + thread_info thinfo; + status_t result = B_OK; + vuint32 *regs, *regs2; + char shared_name[B_OS_NAME_LENGTH]; + + /* find the device name in the list of devices */ + /* we're never passed a name we didn't publish */ + while (pd->device_names[index] && (strcmp(name, pd->device_names[index]) != 0)) index++; + + /* for convienience */ + di = &(pd->di[index]); + + /* make sure no one else has write access to the common data */ + AQUIRE_BEN(pd->kernel); + + /* if it's already open for writing */ + if (di->is_open) { + /* mark it open another time */ + goto mark_as_open; + } + /* create the shared area */ + sprintf(shared_name, DEVICE_FORMAT " shared", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + /* create this area with NO user-space read or write permissions, to prevent accidental dammage */ + di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 0); + if (di->shared_area < 0) { + /* return the error */ + result = di->shared_area; + goto done; + } + + /* save a few dereferences */ + si = di->si; + + /* save the vendor and device IDs */ + si->vendor_id = di->pcii.vendor_id; + si->device_id = di->pcii.device_id; + si->revision = di->pcii.revision; + + /* map the device */ + result = map_device(di); + if (result < 0) goto free_shared; + result = B_OK; + + /* create a semaphore for vertical blank management */ + si->vblank = create_sem(0, di->name); + if (si->vblank < 0) { + result = si->vblank; + goto unmap; + } + + /* change the owner of the semaphores to the opener's team */ + /* this is required because apps can't aquire kernel semaphores */ + thid = find_thread(NULL); + get_thread_info(thid, &thinfo); + set_sem_owner(si->vblank, thinfo.team); + + /* assign local regs pointer for SAMPLExx() macros */ + regs = di->regs; + regs2 = di->regs2; + + /* disable and clear any pending interrupts */ + disable_vbi(regs, regs2); + + /* If there is a valid interrupt line assigned then set up interrupts */ + if ((di->pcii.u.h0.interrupt_pin == 0x00) || + (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ + (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ + { + /* interrupt does not exist so exit without installing our handler */ + goto delete_the_sem; + } + else + { + /* otherwise install our interrupt handler */ + result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, mn_interrupt, (void *)di, 0); + /* bail if we couldn't install the handler */ + if (result != B_OK) goto delete_the_sem; + } + +mark_as_open: + /* mark the device open */ + di->is_open++; + + /* send the cookie to the opener */ + *cookie = di; + + goto done; + + +delete_the_sem: + delete_sem(si->vblank); + +unmap: + unmap_device(di); + +free_shared: + /* clean up our shared area */ + delete_area(di->shared_area); + di->shared_area = -1; + di->si = NULL; + +done: + /* end of critical section */ + RELEASE_BEN(pd->kernel); + + /* all done, return the status */ + return result; +} + +/* ---------- + read_hook - does nothing, gracefully +----- */ +static status_t +read_hook (void* dev, off_t pos, void* buf, size_t* len) +{ + *len = 0; + return B_NOT_ALLOWED; +} + + +/* ---------- + write_hook - does nothing, gracefully +----- */ +static status_t +write_hook (void* dev, off_t pos, const void* buf, size_t* len) +{ + *len = 0; + return B_NOT_ALLOWED; +} + +/* ---------- + close_hook - does nothing, gracefully +----- */ +static status_t +close_hook (void* dev) +{ + /* we don't do anything on close: there might be dup'd fd */ + return B_NO_ERROR; +} + +/* ----------- + free_hook - close down the device +----------- */ +static status_t +free_hook (void* dev) { + device_info *di = (device_info *)dev; + shared_info *si = di->si; + vuint32 *regs = di->regs; + vuint32 *regs2 = di->regs2; + + /* lock the driver */ + AQUIRE_BEN(pd->kernel); + + /* if opened multiple times, decrement the open count and exit */ + if (di->is_open > 1) + goto unlock_and_exit; + + /* disable and clear any pending interrupts */ + disable_vbi(regs, regs2); + + /* remove interrupt handler */ + remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, mn_interrupt, di); + + /* delete the semaphores, ignoring any errors ('cause the owning team may have died on us) */ + delete_sem(si->vblank); + si->vblank = -1; + + /* free regs and framebuffer areas */ + unmap_device(di); + + /* clean up our shared area */ + delete_area(di->shared_area); + di->shared_area = -1; + di->si = NULL; + +unlock_and_exit: + /* mark the device available */ + di->is_open--; + /* unlock the driver */ + RELEASE_BEN(pd->kernel); + /* all done */ + return B_OK; +} + +/* ----------- + control_hook - where the real work is done +----------- */ +static status_t +control_hook (void* dev, uint32 msg, void *buf, size_t len) { + device_info *di = (device_info *)dev; + status_t result = B_DEV_INVALID_IOCTL; + + switch (msg) { + /* the only PUBLIC ioctl */ + case B_GET_ACCELERANT_SIGNATURE: { + char *sig = (char *)buf; + strcpy(sig, current_settings.accelerant); + result = B_OK; + } break; + + /* PRIVATE ioctl from here on */ + case MN_GET_PRIVATE_DATA: { + mn_get_private_data *gpd = (mn_get_private_data *)buf; + if (gpd->magic == MN_PRIVATE_DATA_MAGIC) { + gpd->shared_info_area = di->shared_area; + result = B_OK; + } + } break; + case MN_GET_PCI: { + mn_get_set_pci *gsp = (mn_get_set_pci *)buf; + if (gsp->magic == MN_PRIVATE_DATA_MAGIC) { + pci_info *pcii = &(di->pcii); + gsp->value = get_pci(gsp->offset, gsp->size); + result = B_OK; + } + } break; + case MN_SET_PCI: { + mn_get_set_pci *gsp = (mn_get_set_pci *)buf; + if (gsp->magic == MN_PRIVATE_DATA_MAGIC) { + pci_info *pcii = &(di->pcii); + set_pci(gsp->offset, gsp->size, gsp->value); + result = B_OK; + } + } break; + case MN_DEVICE_NAME: { + mn_device_name *dn = (mn_device_name *)buf; + if (dn->magic == MN_PRIVATE_DATA_MAGIC) { + strcpy(dn->name, di->name); + result = B_OK; + } + } break; + case MN_RUN_INTERRUPTS: { + mn_set_bool_state *ri = (mn_set_bool_state *)buf; + if (ri->magic == MN_PRIVATE_DATA_MAGIC) { + vuint32 *regs = di->regs; + vuint32 *regs2 = di->regs2; + if (ri->do_it) { + enable_vbi(regs, regs2); + } else { + disable_vbi(regs, regs2); + } + result = B_OK; + } + } break; + case MN_ISA_OUT: { + mn_in_out_isa *io_isa = (mn_in_out_isa *)buf; + if (io_isa->magic == MN_PRIVATE_DATA_MAGIC) { + if (io_isa->size == 1) + isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); + else + isa_bus->write_io_16(io_isa->adress, io_isa->data); + result = B_OK; + } + } break; + case MN_ISA_IN: { + mn_in_out_isa *io_isa = (mn_in_out_isa *)buf; + if (io_isa->magic == MN_PRIVATE_DATA_MAGIC) { + if (io_isa->size == 1) + io_isa->data = isa_bus->read_io_8(io_isa->adress); + else + io_isa->data = isa_bus->read_io_16(io_isa->adress); + result = B_OK; + } + } break; + } + return result; +} diff --git a/src/add-ons/kernel/drivers/graphics/neomagic/nm.settings b/src/add-ons/kernel/drivers/graphics/neomagic/nm.settings new file mode 100644 index 0000000000..f8e75aeeb0 --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/neomagic/nm.settings @@ -0,0 +1,21 @@ +# Settings file for the nm driver and accelerant +# +# This file should be moved to the directory +# ~/config/settings/kernel/drivers/ +# + +# nm.driver parameters +# accelerant "nm.accelerant" + +# nm.accelerant parameters +usebios false # not used currently +#memory 2048 # in Kb, override builtin memory size detection +hardcursor true # if true use on-chip cursor capabilities +#logmask 0x00000000 # nothing logged, except errors, is default +#logmask 0x80000000 # log card physical features +#logmask 0x80000000 # log following mask +#logmask 0x08000604 # log overlay use in full +#logmask 0xffffffff # log everything +dumprom false # dump bios rom in ~/nm.rom: not yet working + +#--------- that's all. \ No newline at end of file