From 07e14ea9ad8d5e329e028e50da30ab48fdd2bd72 Mon Sep 17 00:00:00 2001
From: Rudolf Cornelissen <rudolf.cornelissen@gmail.com>
Date: Mon, 20 Dec 2004 15:34:56 +0000
Subject: [PATCH] completed engine command struct defines so on-the-fly FIFO
 channel re-assignments can be done. Will be expanded more to include used 3D
 commands.

git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10509 a95241bf-73f2-0310-859d-f6bbb57e9c96
---
 .../private/graphics/nvidia/DriverInterface.h |  9 ++-
 headers/private/graphics/nvidia/nv_acc.h      | 58 +++++++++++++++++++
 headers/private/graphics/nvidia/nv_macros.h   |  6 --
 3 files changed, 62 insertions(+), 11 deletions(-)

diff --git a/headers/private/graphics/nvidia/DriverInterface.h b/headers/private/graphics/nvidia/DriverInterface.h
index 6374015831..876b874afa 100644
--- a/headers/private/graphics/nvidia/DriverInterface.h
+++ b/headers/private/graphics/nvidia/DriverInterface.h
@@ -96,13 +96,12 @@ enum {
 #define MAXBUFFERS 3
 
 /* internal used info on overlay buffers */
-typedef	struct
-{
+typedef	struct {
 	uint16 slopspace;
 	uint32 size;
 } int_buf_info;
 
-typedef struct settings {  // apsed, see comments in nv.settings
+typedef struct { // apsed, see comments in nv.settings
 	// for driver
 	char   accelerant[B_FILE_NAME_LENGTH];
 	bool   dumprom;
@@ -115,7 +114,7 @@ typedef struct settings {  // apsed, see comments in nv.settings
 	bool   force_pci;
 	bool   unhide_fw;
 	bool   pgm_panel;
-} settings;
+} nv_settings;
 
 /*shared info*/
 typedef struct {
@@ -311,7 +310,7 @@ typedef struct {
 	uint8 rom_mirror[65536];
 
 	/* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */
-	settings settings;
+	nv_settings settings;
 
 	struct
 	{
diff --git a/headers/private/graphics/nvidia/nv_acc.h b/headers/private/graphics/nvidia/nv_acc.h
index 97fb44baf1..304fab6748 100644
--- a/headers/private/graphics/nvidia/nv_acc.h
+++ b/headers/private/graphics/nvidia/nv_acc.h
@@ -47,6 +47,64 @@ typedef struct {
 } cmd_nv_image_blit;
 
 typedef struct {
+	uint32 reserved00[0x0004];
+	uint16 FifoFree;			/* little endian (FIFO internal register) */
+	uint16 Nop;					/* little endian (FIFO internal register) */
+	uint32 reserved01[0x00fa];
+	uint32 Color1A;				/* b0-31 is color */
+	struct
+	{
+		uint32 LeftTop;			/* b0-15 is top, b16-31 is left */
+		uint32 WidthHeight;		/* b0-15 is height, b16-31 is width */
+	} UnclippedRectangle[0x40];	/* command can handle upto 64 unclipped rects */
+//XFree also defines: (not used AFAIK ATM)
+/*
+    U032 reserved04[(0x080)-3];
+    struct
+    {
+        U032 TopLeft;
+        U032 BottomRight;
+    } ClipB;
+    U032 Color1B;
+    struct
+    {
+        U032 TopLeft;
+        U032 BottomRight;
+    } ClippedRectangle[64];
+    U032 reserved05[(0x080)-5];
+    struct
+    {
+        U032 TopLeft;
+        U032 BottomRight;
+    } ClipC;
+    U032 Color1C;
+    U032 WidthHeightC;
+    U032 PointC;
+    U032 MonochromeData1C;
+    U032 reserved06[(0x080)+121];
+    struct
+    {
+        U032 TopLeft;
+        U032 BottomRight;
+    } ClipD;
+    U032 Color1D;
+    U032 WidthHeightInD;
+    U032 WidthHeightOutD;
+    U032 PointD;
+    U032 MonochromeData1D;
+    U032 reserved07[(0x080)+120];
+    struct
+    {
+        U032 TopLeft;
+        U032 BottomRight;
+    } ClipE;
+    U032 Color0E;
+    U032 Color1E;
+    U032 WidthHeightInE;
+    U032 WidthHeightOutE;
+    U032 PointE;
+    U032 MonochromeData01E;
+*/
 } cmd_nv3_gdi_rectangle_text;
 
 typedef struct {
diff --git a/headers/private/graphics/nvidia/nv_macros.h b/headers/private/graphics/nvidia/nv_macros.h
index 42cb604fb7..e74bb7fb4e 100644
--- a/headers/private/graphics/nvidia/nv_macros.h
+++ b/headers/private/graphics/nvidia/nv_macros.h
@@ -442,12 +442,6 @@
 #define	NVACC_FIFO_CH6		0x0080c000
 #define	NVACC_FIFO_CH7		0x0080e000
 
-/* used bitmap registers */
-#define NV16_BMP_FIFOFREE	0x0080a010 /* little endian */
-#define NVACC_BMP_COLOR1A	0x0080a3fc /* 'mapped' from 0x006b03fc */
-#define NVACC_BMP_UCRECTL_0	0x0080a400 /* 'mapped' from 0x006b0400 */
-#define NVACC_BMP_UCRECSZ_0	0x0080a404 /* 'mapped' from 0x006b0404 */
-
 /* Nvidia PCI direct registers */
 #define NV32_PWRUPCTRL		0x00000200
 #define NV32_DUALHEAD_CTRL	0x000010f0//verify!!!