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completed experimental TVout support for singlehead cards using BT868/869, Conexant CX25870/CX25871 chips. As setups with laptop or DVI panels will probably mess up, it's still disabled apart from enabling a testimage. Now starting actual testing..

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14317 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-10-06 10:12:56 +00:00
parent c8c6353050
commit 0b36eea44d
2 changed files with 50 additions and 56 deletions
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src/add-ons/accelerants/nvidia/SetDisplayMode.c
+5
View File
@@ -90,6 +90,11 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* disable interrupts using the kernel driver */ /* disable interrupts using the kernel driver */
interrupt_enable(false); interrupt_enable(false);
/* disable TVout (set GPU CRTC to master mode) */
//fixme: testing on singlehead cards only for now...
//tmp disabled:
// if (!(si->ps.secondary_head)) BT_stop_tvout();
/* find current DPMS state, then turn off screen(s) */ /* find current DPMS state, then turn off screen(s) */
head1_dpms_fetch(&display, &h, &v); head1_dpms_fetch(&display, &h, &v);
head1_dpms(false, false, false); head1_dpms(false, false, false);
src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c
+45 -56
View File
@@ -1576,72 +1576,61 @@ status_t BT_stop_tvout(void)
//fixme: see if better DPMS state fetching can be setup for crtc.c (!) //fixme: see if better DPMS state fetching can be setup for crtc.c (!)
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x3f)); CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x3f));
//fixme: setup... //fixme: is this needed? does b5 have a special meaning in nvidia cards?
/* //normal in this driver is:
uint32 temp32; // SEQW(CLKMODE, 0x21);
unsigned char VertRetrace; //betvout:
SEQW(CLKMODE, 0x01);
//SEQ:
*(dev->pcio_base + 0x3c4) = 0x01;
*(dev->pcio_base + 0x3c5) = 0x01;
//wait for 1 image to be generated to make sure VGA has kicked in and is
//running OK before continuing...
//(Kick in will fail often if we do not wait here: You'll notice this most
// prominently in VESA 640x480 mode. Just try switching about 10 times and
// you'll probably see... (re-checked for PCI V0.20))
VertRetrace = 1;
//(make sure we are 'in' active VGA picture:)
do VertRetrace = (*(dev->pcio_base + 0x3da) & 0x08);
while (VertRetrace);
//(wait for vertical retrace start on VGA:)
do VertRetrace = (*(dev->pcio_base + 0x3da) & 0x08);
while (!VertRetrace);
//(make sure we are 'in' active VGA picture again:)
do VertRetrace = (*(dev->pcio_base + 0x3da) & 0x08);
while (VertRetrace);
//'update' PIXEL/TV: /* wait for one image to be generated to make sure VGA has kicked in and is
*(dev->pcio_base + AdresReg) = 0x28; * running OK before continuing...
*(dev->pcio_base + DataReg) &= 0x03; * (Kicking in will fail often if we do not wait here) */
/* make sure we are 'in' active VGA picture */
while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1);
/* wait for next vertical retrace start on VGA */
while (!(NV_REG8(NV8_INSTAT1) & 0x08)) snooze(1);
/* now wait until we are 'in' active VGA picture again */
while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1);
/* set CRTC to master mode (b7 = 0) and clear TVadjust (b3-5 = %000) */
//fixme:
//update this to take flatpanels into consideration..
CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03));
//fixme: checkout...
//CAUTION: //CAUTION:
//On the TNT1, these memadresses apparantly cannot be read (sometimes)!; //On the TNT1, these memadresses apparantly cannot be read (sometimes)!;
//write actions do succeed though... (tested on ISA...) //write actions do succeed though... (tested only on ISA bus yet..)
//($00680700 b1-23 and b25-31 apparantly are 'don't cares'...)
//SWITCH RIVA pixelclock to be RIVA's own (so: directly): /* setup TVencoder connection */
//MEMADR $00680700: /* b1-0 = %00: encoder type is SLAVE;
temp32 = (*(dev->regs + (0x00680700 >> 2)) & ~0x00000001); * b24 = 1: VIP datapos is b0-7 */
*(dev->regs + (0x00680700 >> 2)) = (temp32 | 0x01000000); //fixme: setup completely instead of relying on pre-init by BIOS..
DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000001) | 0x01000000));
//switch RIVA PLL phase-lock to lock to RIVA's own internal pixelclock: /* tell GPU to use pixelclock from internal source instead of using TVencoder */
//MEMADR $0068050c: PLLSEL: warning dualhead is killed here! (PLL2 shutoff) DACW(PLLSEL, 0x10000700);
*(dev->regs + (0x0068050c >> 2)) = 0x10000700; if (si->ps.secondary_head) DACW(PLLSEL, (DACR(PLLSEL) | 0x20000800));
//TREG: /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of
*(dev->pcio_base + AdresReg) = 0x3d; * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */
*(dev->pcio_base + DataReg) = 0x00; CRTCW(TREG, 0x00);
//make sure LCD is switched off: /* powerdown FPclock (not touching TMDS power) */
//MEMADR $00680880: //fixme: do we need this? might kill off panel support...
*(dev->regs + (0x00680880 >> 2)) |= 0x10000000; DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x10000000));
//LCD: /* select TV encoder, not panel encoder (b0 = 0).
*(dev->pcio_base + AdresReg) = 0x33; * Note:
*(dev->pcio_base + DataReg) &= 0xfc; * Both are devices using the CRTC in slaved mode. */
//fixme:
//update this to take flatpanels into consideration..
//Set overscan color to 'black': //fixme2:
//Disable this part if you're trying to center the output on TV, //probably better don't touch b1: it's used for powering ext. TMDS (or so) (?)
//you'll get blue overscan range color then. Use this as a guide-'line' ;-) CRTCW(LCD, (CRTCR(LCD) & 0xfc));
//(select index adress register:)
*(dev->pcio_base + 0x3da);
//(write index for 'overscan color' register:)
*(dev->pcio_base + 0x3c0) = 0x11;
//(write data for 'overscan color' register:)
*(dev->pcio_base + 0x3c0) = 0x00;
*/
/* fixme if needed: /* fixme if needed:
* a full encoder chip reset could be done here (so after decoupling crtc)... */ * a full encoder chip reset could be done here (so after decoupling crtc)... */