From 0cabd8891f31c96cf5766c104d0501a6cb7380d8 Mon Sep 17 00:00:00 2001 From: Adrien Destugues Date: Wed, 27 Oct 2021 14:43:21 +0200 Subject: [PATCH] intel_extreme: fix regression introduced in hrev55419. Apparently my comment about the width and height being swapped in this register was not visible enough, so I make it a bit more obvious by adding some uppercase. Change-Id: I27621032d071ed09f82aa109f37482178351db04 Reviewed-on: https://review.haiku-os.org/c/haiku/+/4664 Reviewed-by: waddlesplash --- src/add-ons/accelerants/intel_extreme/Pipes.cpp | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp b/src/add-ons/accelerants/intel_extreme/Pipes.cpp index 985e0f31d7..3ac2797688 100644 --- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp +++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp @@ -209,11 +209,13 @@ Pipe::ConfigureScalePos(display_mode* target) if (gInfo->shared_info->device_type.Generation() <= 4) { // This is "reserved" on G35 and GMA965, but needed on 945 (for which // there is no public documentation), and I assume earlier devices as - // well. Note that the height and width are swapped when compared to - // the other registers. + // well. + // + // IMPORTANT WARNING: height and width are swapped when compared to the other registers! + // Be careful when editing this code and don't accidentally swap them! write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset, - ((uint32)(target->timing.h_display - 1) << 16) - | ((uint32)target->timing.v_display - 1)); + ((uint32)(target->timing.v_display - 1) << 16) + | ((uint32)target->timing.h_display - 1)); } }