From 0caf23319cb4e9f9c8a2ecd30e133e98a1d2b989 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Wed, 4 Sep 2024 08:26:21 +0000 Subject: [PATCH] arm64: Use DEVICE_GRE memory when mapping MTR_WC. * This is the closest thing ARM has the semantics of write-combining MTR on x86. Change-Id: I12a1582e0af871e2ab729262e90695ffe928c85b Reviewed-on: https://review.haiku-os.org/c/haiku/+/8223 Tested-by: Commit checker robot Reviewed-by: waddlesplash --- headers/private/kernel/arch/arm64/arm_registers.h | 2 ++ src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp | 2 +- src/system/kernel/arch/arm64/arch_vm_translation_map.cpp | 7 ++++++- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/headers/private/kernel/arch/arm64/arm_registers.h b/headers/private/kernel/arch/arm64/arm_registers.h index 7bfd1bc911..ae6e84310e 100644 --- a/headers/private/kernel/arch/arm64/arm_registers.h +++ b/headers/private/kernel/arch/arm64/arm_registers.h @@ -501,6 +501,8 @@ #define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8)) #define MAIR_DEVICE_nGnRnE 0x00 #define MAIR_DEVICE_nGnRE 0x04 +#define MAIR_DEVICE_nGRE 0x08 +#define MAIR_DEVICE_GRE 0x0C #define MAIR_NORMAL_NC 0x44 #define MAIR_NORMAL_WT 0xbb #define MAIR_NORMAL_WB 0xff diff --git a/src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp b/src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp index b2bc9fec53..e0182a6fde 100644 --- a/src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp +++ b/src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp @@ -464,7 +464,7 @@ VMSAv8TranslationMap::GetMemoryAttr(uint32 attributes, uint32 memoryType, bool i type = MAIR_DEVICE_nGnRnE; break; case B_MTR_WC: - type = MAIR_NORMAL_NC; + type = MAIR_DEVICE_GRE; break; case B_MTR_WT: type = MAIR_NORMAL_WT; diff --git a/src/system/kernel/arch/arm64/arch_vm_translation_map.cpp b/src/system/kernel/arch/arm64/arch_vm_translation_map.cpp index d0d891b798..56d24a1d83 100644 --- a/src/system/kernel/arch/arm64/arch_vm_translation_map.cpp +++ b/src/system/kernel/arch/arm64/arch_vm_translation_map.cpp @@ -72,7 +72,6 @@ arch_vm_translation_map_init(kernel_args* args, VMPhysicalPageMapper** _physical uint32_t tg1 = (tcr >> 30) & 0x3; uint64_t ttbr0 = READ_SPECIALREG(TTBR0_EL1); uint64_t ttbr1 = READ_SPECIALREG(TTBR1_EL1); - uint64_t mair = READ_SPECIALREG(MAIR_EL1); uint64_t mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1); uint64_t mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1); uint64_t sctlr = READ_SPECIALREG(SCTLR_EL1); @@ -93,7 +92,13 @@ arch_vm_translation_map_init(kernel_args* args, VMPhysicalPageMapper** _physical VMSAv8TranslationMap::fHwFeature |= VMSAv8TranslationMap::HW_COMMON_NOT_PRIVATE; } + uint64_t mair = + (MAIR_DEVICE_nGnRnE) | // Uncached + (MAIR_DEVICE_GRE << 8) | // Write-combining + (MAIR_NORMAL_WT << 16) | // Write-through + (MAIR_NORMAL_WB << 24); // Write-back VMSAv8TranslationMap::fMair = mair; + WRITE_SPECIALREG(MAIR_EL1, mair); WRITE_SPECIALREG(TCR_EL1, tcr);