intel_extreme: add support for Alder Lake chipsets.

Added AlderLake-P and AlderLake-N variants to agp_gart bus
and intel_extreme driver. Tested and confirmed working.

Change-Id: I1ac1e04fbba222a2f9eef483d68575665561e837
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8840
Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Dru Satori
2025-01-20 17:17:43 +00:00
committed by waddlesplash
parent 04bf57110c
commit 0db74e1ae1
4 changed files with 13 additions and 2 deletions
@@ -55,6 +55,7 @@
#define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake #define INTEL_GROUP_CML (INTEL_FAMILY_LAKE | 0x0080) // CometLake
#define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake #define INTEL_GROUP_JSL (INTEL_FAMILY_LAKE | 0x0100) // JasperLake
#define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake #define INTEL_GROUP_TGL (INTEL_FAMILY_LAKE | 0x0200) // TigerLake
#define INTEL_GROUP_ALD (INTEL_FAMILY_LAKE | 0x0400) // AlderLake
// models // models
#define INTEL_TYPE_SERVER 0x0004 #define INTEL_TYPE_SERVER 0x0004
#define INTEL_TYPE_MOBILE 0x0008 #define INTEL_TYPE_MOBILE 0x0008
@@ -96,6 +97,7 @@
#define INTEL_MODEL_JSL (INTEL_GROUP_JSL) #define INTEL_MODEL_JSL (INTEL_GROUP_JSL)
#define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE) #define INTEL_MODEL_JSLM (INTEL_GROUP_JSL | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE) #define INTEL_MODEL_TGLM (INTEL_GROUP_TGL | INTEL_TYPE_MOBILE)
#define INTEL_MODEL_ALDM (INTEL_GROUP_ALD | INTEL_TYPE_MOBILE)
#define INTEL_PCH_DEVICE_ID_MASK 0xff80 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
#define INTEL_PCH_IBX_DEVICE_ID 0x3b00 #define INTEL_PCH_IBX_DEVICE_ID 0x3b00
@@ -124,6 +126,7 @@
#define INTEL_PCH_ADP2_DEVICE_ID 0x5180 #define INTEL_PCH_ADP2_DEVICE_ID 0x5180
#define INTEL_PCH_ADP3_DEVICE_ID 0x7a00 #define INTEL_PCH_ADP3_DEVICE_ID 0x7a00
#define INTEL_PCH_ADP4_DEVICE_ID 0x5480 #define INTEL_PCH_ADP4_DEVICE_ID 0x5480
#define INTEL_PCH_ADP5_DEVICE_ID 0x4600
#define INTEL_PCH_P2X_DEVICE_ID 0x7100 #define INTEL_PCH_P2X_DEVICE_ID 0x7100
#define INTEL_PCH_P3X_DEVICE_ID 0x7000 #define INTEL_PCH_P3X_DEVICE_ID 0x7000
@@ -233,7 +236,7 @@ struct DeviceType {
return 8; return 8;
if (InGroup(INTEL_GROUP_JSL)) if (InGroup(INTEL_GROUP_JSL))
return 11; return 11;
if (InGroup(INTEL_GROUP_TGL)) if (InGroup(INTEL_GROUP_TGL) || InGroup(INTEL_GROUP_ALD))
return 12; return 12;
if (InFamily(INTEL_FAMILY_LAKE)) if (InFamily(INTEL_FAMILY_LAKE))
return 9; return 9;
@@ -237,6 +237,9 @@ const struct supported_device {
{0x9a36, 0x9a68, INTEL_MODEL_TGLM, "TigerLake-LP GT1"}, {0x9a36, 0x9a68, INTEL_MODEL_TGLM, "TigerLake-LP GT1"},
{0x9a26, 0x9a60, INTEL_MODEL_TGLM, "TigerLake-LP GT1"}, {0x9a26, 0x9a60, INTEL_MODEL_TGLM, "TigerLake-LP GT1"},
{0x9a26, 0x9a68, INTEL_MODEL_TGLM, "TigerLake-LP GT1"}, {0x9a26, 0x9a68, INTEL_MODEL_TGLM, "TigerLake-LP GT1"},
{0x4621, 0x46a6, INTEL_MODEL_ALDM, "Alder Lake-P GT2"},
{0x4621, 0x46d1, INTEL_MODEL_ALDM, "Alder Lake-N GT2"},
}; };
struct intel_info { struct intel_info {
@@ -208,6 +208,10 @@ const struct supported_device {
{0x9a60, INTEL_MODEL_TGLM, "TigerLake"}, {0x9a60, INTEL_MODEL_TGLM, "TigerLake"},
{0x9a68, INTEL_MODEL_TGLM, "TigerLake"}, {0x9a68, INTEL_MODEL_TGLM, "TigerLake"},
{0x9a70, INTEL_MODEL_TGLM, "TigerLake"}, {0x9a70, INTEL_MODEL_TGLM, "TigerLake"},
{0x46a6, INTEL_MODEL_ALDM, "Alder Lake-P GT2"},
{0x46d1, INTEL_MODEL_ALDM, "Alder Lake-N"},
}; };
int32 api_version = B_CUR_DRIVER_API_VERSION; int32 api_version = B_CUR_DRIVER_API_VERSION;
@@ -323,6 +327,7 @@ detect_intel_pch()
case INTEL_PCH_ADP2_DEVICE_ID: case INTEL_PCH_ADP2_DEVICE_ID:
case INTEL_PCH_ADP3_DEVICE_ID: case INTEL_PCH_ADP3_DEVICE_ID:
case INTEL_PCH_ADP4_DEVICE_ID: case INTEL_PCH_ADP4_DEVICE_ID:
case INTEL_PCH_ADP5_DEVICE_ID:
ERROR("%s: Found Alder Lake PCH\n", __func__); ERROR("%s: Found Alder Lake PCH\n", __func__);
return INTEL_PCH_ADP; return INTEL_PCH_ADP;
} }
@@ -518,7 +518,7 @@ init_interrupt_handler(intel_info &info)
write32(info, GEN11_TBT_HOTPLUG_CTL, 0); write32(info, GEN11_TBT_HOTPLUG_CTL, 0);
if (info.shared_info->pch_info >= INTEL_PCH_ICP) { if (info.shared_info->pch_info >= INTEL_PCH_ICP) {
if (info.shared_info->pch_info <= INTEL_PCH_TGP) if (info.shared_info->pch_info <= INTEL_PCH_ADP)
write32(info, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); write32(info, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
read32(info, SDEIMR); read32(info, SDEIMR);
write32(info, SDEIMR, 0x3f023f07); write32(info, SDEIMR, 0x3f023f07);