radeon_hd: ss_probe reads the pixel clock; set before calling.

* CID 743876

src/add-ons/accelerants/radeon_hd/pll.cpp

@@ -1002,6 +1002,12 @@ pll_external_set(uint32 clock)
 }
 
 
+/**
+ * pll_external_init - Sets external default pll to sane value
+ *
+ * Takes the AtomBIOS ulDefaultDispEngineClkFreq and applies it
+ * back to the card's external PLL clock via SetPixelClock
+ */
 void
 pll_external_init()
 {
@@ -1012,15 +1018,18 @@ pll_external_init()
 	} else if (info.dceMajor >= 4) {
 		// Create our own pseudo pll
 		pll_info pll;
+		pll.pixelClock = gInfo->displayClockFrequency;
+
 		pll_asic_ss_probe(&pll, ASIC_INTERNAL_SS_ON_DCPLL);
 		if (pll.ssEnabled)
 			display_crtc_ss(&pll, ATOM_DISABLE);
-		pll_external_set(gInfo->displayClockFrequency);
+		pll_external_set(pll.pixelClock);
 		if (pll.ssEnabled)
 			display_crtc_ss(&pll, ATOM_ENABLE);
 	}
 }
 
+
 /**
  * pll_usage_mask - Calculate which PLL's are in use
  *