From 0ea662e5e968bd3c32adb299af3452ba0e226882 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Tue, 15 Dec 2015 07:23:21 -0600 Subject: [PATCH] intel_extreme: Correct panel control register on non-pch --- .../private/graphics/intel_extreme/intel_extreme.h | 3 ++- src/add-ons/accelerants/intel_extreme/Ports.cpp | 13 +++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index a111f84a8c..929c1702ab 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -448,12 +448,13 @@ struct intel_free_graphics_memory { #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors #define LVDS_POST2_RATE_FAST 7 +#define LVDS_B0B3_POWER_MASK (3 << 2) +#define LVDS_B0B3_POWER_UP (3 << 2) #define LVDS_CLKB_POWER_MASK (3 << 4) #define LVDS_CLKB_POWER_UP (3 << 4) #define LVDS_A3_POWER_MASK (3 << 6) #define LVDS_A3_POWER_UP (3 << 6) #define LVDS_A0A2_CLKA_POWER_UP (3 << 8) -#define LVDS_B0B3PAIRS_POWER_UP (3 << 2) #define LVDS_BORDER_ENABLE (1 << 15) #define LVDS_HSYNC_POLARITY (1 << 20) #define LVDS_VSYNC_POLARITY (1 << 21) diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp index 4dea0dc869..f5603e330c 100644 --- a/src/add-ons/accelerants/intel_extreme/Ports.cpp +++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp @@ -327,10 +327,10 @@ LVDSPort::LVDSPort() Port(INTEL_PORT_C, "LVDS") { // Always unlock LVDS port as soon as we start messing with it. - if (gInfo->shared_info->device_type.HasPlatformControlHub()) { - write32(PCH_PANEL_CONTROL, - read32(PCH_PANEL_CONTROL) | PANEL_REGISTER_UNLOCK); - } + uint32 panelControl = INTEL_PANEL_CONTROL; + if (gInfo->shared_info->device_type.HasPlatformControlHub()) + panelControl = PCH_PANEL_CONTROL; + write32(panelControl, read32(panelControl) | PANEL_REGISTER_UNLOCK); } @@ -525,9 +525,9 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode) // Set the B0-B3 data pairs corresponding to whether we're going to // set the DPLLs for dual-channel mode or not. if (divisors.post2_high) - lvds |= LVDS_B0B3PAIRS_POWER_UP | LVDS_CLKB_POWER_UP; + lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; else - lvds &= ~(LVDS_B0B3PAIRS_POWER_UP | LVDS_CLKB_POWER_UP); + lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); // Set LVDS sync polarity lvds &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); @@ -538,6 +538,7 @@ LVDSPort::SetDisplayMode(display_mode* target, uint32 colorMode) if ((target->timing.flags & B_POSITIVE_VSYNC) == 0) lvds |= LVDS_VSYNC_POLARITY; + TRACE("%s: LVDS Control: 0x%" B_PRIx32 "\n", __func__, lvds); write32(_PortRegister(), lvds); read32(_PortRegister());