arch: NX is initialized too early on non-boot CPUs

src/system/kernel/arch/x86/arch_cpu.cpp

@@ -747,6 +747,15 @@ arch_cpu_init_percpu(kernel_args* args, int cpu)
 		}
 	}
 
+	// If availalbe enable NX-bit (No eXecute). Boot CPU can not enable
+	// NX-bit here since PAE should be enabled first.
+	if (cpu != 0) {
+		if (x86_check_feature(IA32_FEATURE_AMD_EXT_NX, FEATURE_EXT_AMD)) {
+			x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
+				| IA32_MSR_EFER_NX);
+		}
+	}
+
 	return B_OK;
 }
 

src/system/kernel/arch/x86/paging/64bit/X86PagingMethod64Bit.cpp

@@ -59,9 +59,11 @@ X86PagingMethod64Bit::Init(kernel_args* args,
 	fKernelPhysicalPML4 = args->arch_args.phys_pgdir;
 	fKernelVirtualPML4 = (uint64*)(addr_t)args->arch_args.vir_pgdir;
 
-	// enable NX-bit on all CPUs
+	// if availalbe enable NX-bit (No eXecute)
-	if (x86_check_feature(IA32_FEATURE_AMD_EXT_NX, FEATURE_EXT_AMD))
+	if (x86_check_feature(IA32_FEATURE_AMD_EXT_NX, FEATURE_EXT_AMD)) {
-		call_all_cpus_sync(&_EnableExecutionDisable, NULL);
+		x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
+			| IA32_MSR_EFER_NX);
+	}
 
 	// Ensure that the user half of the address space is clear. This removes
 	// the temporary identity mapping made by the boot loader.
@@ -380,11 +382,3 @@ X86PagingMethod64Bit::PutPageTableEntryInTable(uint64* entry,
 	SetTableEntry(entry, page);
 }
 
-
-void
-X86PagingMethod64Bit::_EnableExecutionDisable(void* dummy, int cpu)
-{
-	x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
-		| IA32_MSR_EFER_NX);
-}
-

src/system/kernel/arch/x86/paging/pae/X86PagingMethodPAE.cpp

@@ -148,6 +148,12 @@ struct X86PagingMethodPAE::ToPAESwitcher {
 		// enable PAE on all CPUs
 		call_all_cpus_sync(&_EnablePAE, (void*)(addr_t)physicalPDPT);
 
+		// if availalbe enable NX-bit (No eXecute)
+		if (x86_check_feature(IA32_FEATURE_AMD_EXT_NX, FEATURE_EXT_AMD)) {
+			x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
+				| IA32_MSR_EFER_NX);
+		}
+
 		// set return values
 		_virtualPDPT = pdpt;
 		_physicalPDPT = physicalPDPT;
@@ -165,12 +171,6 @@ private:
 	{
 		x86_write_cr3((addr_t)physicalPDPT);
 		x86_write_cr4(x86_read_cr4() | IA32_CR4_PAE | IA32_CR4_GLOBAL_PAGES);
-
-		// if availalbe enable NX-bit (No eXecute)
-		if (x86_check_feature(IA32_FEATURE_AMD_EXT_NX, FEATURE_EXT_AMD)) {
-			x86_write_msr(IA32_MSR_EFER, x86_read_msr(IA32_MSR_EFER)
-				| IA32_MSR_EFER_NX);
-		}
 	}
 
 	void _TranslatePageTable(addr_t virtualBase)