Merge branch 'master' into x86_64
Conflicts: build/jam/FloppyBootImage build/jam/OptionalBuildFeatures build/jam/OptionalPackages headers/private/shared/cpu_type.h src/bin/ps.c src/bin/sysinfo.cpp src/kits/tracker/PoseView.cpp src/preferences/appearance/DecorSettingsView.cpp src/preferences/virtualmemory/Settings.cpp src/servers/input/AddOnManager.cpp src/servers/input/InputServer.cpp src/servers/input/InputServerMethod.cpp src/system/boot/Jamfile src/system/boot/platform/raspberrypi_arm/mmu.cpp src/system/boot/platform/u-boot/arch/arm/Jamfile src/system/kernel/arch/x86/arch_cpu.cpp src/system/kernel/arch/x86/arch_thread.cpp src/system/kernel/cache/block_cache.cpp src/system/kernel/vm/VMAnonymousCache.cpp
This commit is contained in:
Alex Smith
+47
-32
@@ -1,6 +1,6 @@
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/*
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* Copyright 2004-2008, Axel Dörfler, [email protected].
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* Copyright (c) 2002, Carlos Hasan, for Haiku.
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* Copyright 2004-2012, Axel Dörfler, [email protected].
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* Copyright 2002, Carlos Hasan.
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*
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* Distributed under the terms of the MIT license.
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*/
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@@ -15,8 +15,8 @@
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#include <cpu_type.h>
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// ToDo: -disable_cpu_sn option is not yet implemented
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// ToDo: most of this file should go into an architecture dependent source file
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// TODO: -disable_cpu_sn option is not yet implemented
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// TODO: most of this file should go into an architecture dependent source file
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#if defined(__INTEL__) || defined(__x86_64__)
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struct cache_description {
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@@ -196,8 +196,8 @@ print_intel_cache_descriptors(enum cpu_types type, cpuid_info *info)
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if (cacheDescriptors[i] == 0x40) {
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printf("\tNo integrated L%u cache\n",
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type >= B_CPU_INTEL_PENTIUM_IV
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&& (type & B_CPU_x86_VENDOR_MASK) == B_CPU_INTEL_x86 ?
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3 : 2);
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&& (type & B_CPU_x86_VENDOR_MASK) == B_CPU_INTEL_x86
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? 3 : 2);
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} else
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printf("\t%s\n", sIntelCacheDescriptions[j].description);
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break;
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@@ -242,7 +242,8 @@ print_level2_cache(uint32 reg, const char *name)
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{
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uint32 size = (reg >> 16) & 0xffff;
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uint32 ways = (reg >> 12) & 0xf;
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uint32 linesPerTag = (reg >> 8) & 0xf; // intel does not define this
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uint32 linesPerTag = (reg >> 8) & 0xf;
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// intel does not define this
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uint32 lineSize = reg & 0xff;
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printf("\t%s: %" B_PRIu32 " KB, ", name, size);
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@@ -297,12 +298,14 @@ print_cache_desc(int32 cpu)
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print_level2_cache(info.regs.ecx, "L2 cache");
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}
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static void
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print_intel_cache_desc(int32 cpu)
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{
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cpuid_info info;
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// A second parameters needs to be passed to CPUID which determines the cache level to query
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// A second parameters needs to be passed to CPUID which determines the
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// cache level to query
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get_cpuid(&info, 0x00000004, cpu);
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putchar('\n');
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@@ -462,26 +465,34 @@ print_features(uint32 features)
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#if defined(__INTEL__) || defined(__x86_64__)
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static void
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print_processor_signature(system_info *sys_info, cpuid_info *info, const char *prefix)
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print_processor_signature(system_info *sys_info, cpuid_info *info,
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const char *prefix)
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{
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if ((sys_info->cpu_type & B_CPU_x86_VENDOR_MASK) == B_CPU_AMD_x86) {
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printf("\t%s%sype %" B_PRIu32 ", family %" B_PRIu32 ", model %u, "
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"stepping %" B_PRIu32 ", features 0x%08" B_PRIx32 "\n",
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printf("\t%s%sype %" B_PRIu32 ", family %" B_PRIu32 ", model %" B_PRIu32
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", stepping %" B_PRIu32 ", features 0x%08" B_PRIx32 "\n",
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prefix ? prefix : "", prefix && prefix[0] ? "t" : "T",
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info->eax_1.type,
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info->eax_1.family + (info->eax_1.family == 0xf ? info->eax_1.extended_family : 0),
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info->eax_1.model + (info->eax_1.model == 0xf ? info->eax_1.extended_model << 4 : 0),
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info->eax_1.family + (info->eax_1.family == 0xf
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? info->eax_1.extended_family : 0),
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info->eax_1.model + (info->eax_1.model == 0xf
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? info->eax_1.extended_model << 4 : 0),
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info->eax_1.stepping,
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info->eax_1.features);
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} else if ((sys_info->cpu_type & B_CPU_x86_VENDOR_MASK) == B_CPU_INTEL_x86) {
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} else if ((sys_info->cpu_type & B_CPU_x86_VENDOR_MASK)
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== B_CPU_INTEL_x86) {
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// model calculation is different for INTEL
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printf("\t%s%sype %" B_PRIu32 ", family %" B_PRIu32 ", model %u, "
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"stepping %" B_PRIu32 ", features 0x%08" B_PRIx32 "\n",
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printf("\t%s%sype %" B_PRIu32 ", family %" B_PRIu32 ", model %" B_PRIu32
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", stepping %" B_PRIu32 ", features 0x%08" B_PRIx32 "\n",
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prefix ? prefix : "", prefix && prefix[0] ? "t" : "T",
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info->eax_1.type,
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info->eax_1.family + (info->eax_1.family == 0xf ? info->eax_1.extended_family : 0),
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info->eax_1.model + ((info->eax_1.family == 0xf || info->eax_1.family == 0x6) ? info->eax_1.extended_model << 4 : 0),
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info->eax_1.family + (info->eax_1.family == 0xf
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? info->eax_1.extended_family : 0),
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info->eax_1.model
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+ ((info->eax_1.family == 0xf || info->eax_1.family == 0x6)
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? info->eax_1.extended_model << 4 : 0),
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info->eax_1.stepping,
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info->eax_1.features);
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}
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@@ -505,12 +516,10 @@ dump_platform(system_info *info)
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static void
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dump_cpu(system_info *info, int32 cpu)
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{
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/* references:
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*
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* http://grafi.ii.pw.edu.pl/gbm/x86/cpuid.html
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* http://www.sandpile.org/ia32/cpuid.htm
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/TN13.pdf (Duron erratum)
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*/
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// References:
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// http://grafi.ii.pw.edu.pl/gbm/x86/cpuid.html
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// http://www.sandpile.org/ia32/cpuid.htm
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// http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/TN13.pdf (Duron erratum)
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cpuid_info baseInfo;
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if (get_cpuid(&baseInfo, 0, cpu) != B_OK) {
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@@ -519,15 +528,18 @@ dump_cpu(system_info *info, int32 cpu)
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}
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int32 maxStandardFunction = baseInfo.eax_0.max_eax;
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if (maxStandardFunction >= 500)
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maxStandardFunction = 0; /* old Pentium sample chips has cpu signature here */
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if (maxStandardFunction >= 500) {
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// old Pentium sample chips has cpu signature here
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maxStandardFunction = 0;
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}
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/* Extended cpuid */
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// Extended cpuid
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cpuid_info cpuInfo;
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get_cpuid(&cpuInfo, 0x80000000, cpu);
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// extended cpuid is only supported if max_eax is greater than the service id
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// Extended cpuid is only supported if max_eax is greater than the
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// service id
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int32 maxExtendedFunction = 0;
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if (cpuInfo.eax_0.max_eax > 0x80000000)
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maxExtendedFunction = cpuInfo.eax_0.max_eax & 0xff;
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@@ -591,7 +603,8 @@ dump_cpu(system_info *info, int32 cpu)
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get_cpuid(&cpuInfo, 0x80000007, cpu);
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print_amd_power_management_features(cpuInfo.regs.edx);
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}
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} else if ((info->cpu_type & B_CPU_x86_VENDOR_MASK) == B_CPU_TRANSMETA_x86)
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} else if ((info->cpu_type & B_CPU_x86_VENDOR_MASK)
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== B_CPU_TRANSMETA_x86)
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print_transmeta_features(cpuInfo.regs.edx);
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}
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@@ -600,7 +613,8 @@ dump_cpu(system_info *info, int32 cpu)
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if (!strncmp(baseInfo.eax_0.vendor_id, "CyrixInstead", 12)) {
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get_cpuid(&cpuInfo, 0x00000002, cpu);
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print_intel_cache_descriptors(info->cpu_type, &cpuInfo);
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} else if ((info->cpu_type & B_CPU_x86_VENDOR_MASK) == B_CPU_INTEL_x86) {
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} else if ((info->cpu_type & B_CPU_x86_VENDOR_MASK)
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== B_CPU_INTEL_x86) {
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// Intel does not support extended function 5 (but it does 6 hmm)
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print_intel_cache_desc(cpu);
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} else {
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@@ -626,7 +640,8 @@ dump_cpu(system_info *info, int32 cpu)
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get_cpuid(&cpuInfo, 3, cpu);
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printf("Serial number: %04" B_PRIx32 "-%04" B_PRIx32 "-%04" B_PRIx32
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"-%04" B_PRIx32 "-%04" B_PRIx32 "-%04" B_PRIx32 "\n",
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flagsInfo.eax_1.features >> 16, flagsInfo.eax_1.features & 0xffff,
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flagsInfo.eax_1.features >> 16,
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flagsInfo.eax_1.features & 0xffff,
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cpuInfo.regs.edx >> 16, cpuInfo.regs.edx & 0xffff,
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cpuInfo.regs.ecx >> 16, cpuInfo.regs.edx & 0xffff);
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}
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