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Ported PCI module to x86_64.

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Uses the x86 architecture code, made fixes to printf formats and a
couple of 64-bit fixes. Only potentially intrusive change is that I've
changed PCI.h to use uint32 rather than ulong. I don't see any way
this would cause any issues, though.
This commit is contained in:
Alex Smith
2012-07-20 12:00:20 +01:00
parent 9d4e925cf0
commit 12bd7812dd
9 changed files with 107 additions and 88 deletions
Download Patch File Download Diff File Expand all files Collapse all files
build/jam/FloppyBootImage
+2 -2
View File
@@ -54,7 +54,7 @@ SYSTEM_ADD_ONS_FILE_SYSTEMS = bfs iso9660 attribute_overlay write_overlay ;
if $(TARGET_ARCH) = x86_64 { if $(TARGET_ARCH) = x86_64 {
AddFilesToFloppyBootArchive system add-ons kernel bus_managers AddFilesToFloppyBootArchive system add-ons kernel bus_managers
: dpc ; : config_manager dpc pci ;
} else { } else {
# modules # modules
AddFilesToFloppyBootArchive system add-ons kernel bus_managers AddFilesToFloppyBootArchive system add-ons kernel bus_managers
@@ -126,7 +126,7 @@ if $(NET_BOOT) = 1 {
# boot module links # boot module links
if $(TARGET_ARCH) = x86_64 { if $(TARGET_ARCH) = x86_64 {
AddBootModuleSymlinksToFloppyBootArchive AddBootModuleSymlinksToFloppyBootArchive
dpc dpc config_manager pci
; ;
} else { } else {
AddBootModuleSymlinksToFloppyBootArchive AddBootModuleSymlinksToFloppyBootArchive
headers/os/drivers/PCI.h
+22 -22
View File
@@ -44,15 +44,15 @@ typedef struct pci_info {
uchar reserved; /* filler, for alignment */ uchar reserved; /* filler, for alignment */
union { union {
struct { struct {
ulong cardbus_cis; /* CardBus CIS pointer */ uint32 cardbus_cis; /* CardBus CIS pointer */
ushort subsystem_id; /* subsystem (add-in card) id */ ushort subsystem_id; /* subsystem (add-in card) id */
ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */ ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */
ulong rom_base; /* rom base address, viewed from host */ uint32 rom_base; /* rom base address, viewed from host */
ulong rom_base_pci; /* rom base addr, viewed from pci */ uint32 rom_base_pci; /* rom base addr, viewed from pci */
ulong rom_size; /* rom size */ uint32 rom_size; /* rom size */
ulong base_registers[6]; /* base registers, viewed from host */ uint32 base_registers[6]; /* base registers, viewed from host */
ulong base_registers_pci[6]; /* base registers, viewed from pci */ uint32 base_registers_pci[6]; /* base registers, viewed from pci */
ulong base_register_sizes[6]; /* size of what base regs point to */ uint32 base_register_sizes[6]; /* size of what base regs point to */
uchar base_register_flags[6]; /* flags from base address fields */ uchar base_register_flags[6]; /* flags from base address fields */
uchar interrupt_line; /* interrupt line */ uchar interrupt_line; /* interrupt line */
uchar interrupt_pin; /* interrupt pin */ uchar interrupt_pin; /* interrupt pin */
@@ -60,9 +60,9 @@ typedef struct pci_info {
uchar max_latency; /* how often PCI access needed */ uchar max_latency; /* how often PCI access needed */
} h0; } h0;
struct { struct {
ulong base_registers[2]; /* base registers, viewed from host */ uint32 base_registers[2]; /* base registers, viewed from host */
ulong base_registers_pci[2]; /* base registers, viewed from pci */ uint32 base_registers_pci[2]; /* base registers, viewed from pci */
ulong base_register_sizes[2]; /* size of what base regs point to */ uint32 base_register_sizes[2]; /* size of what base regs point to */
uchar base_register_flags[2]; /* flags from base address fields */ uchar base_register_flags[2]; /* flags from base address fields */
uchar primary_bus; uchar primary_bus;
uchar secondary_bus; uchar secondary_bus;
@@ -75,12 +75,12 @@ typedef struct pci_info {
ushort memory_limit; ushort memory_limit;
ushort prefetchable_memory_base; ushort prefetchable_memory_base;
ushort prefetchable_memory_limit; ushort prefetchable_memory_limit;
ulong prefetchable_memory_base_upper32; uint32 prefetchable_memory_base_upper32;
ulong prefetchable_memory_limit_upper32; uint32 prefetchable_memory_limit_upper32;
ushort io_base_upper16; ushort io_base_upper16;
ushort io_limit_upper16; ushort io_limit_upper16;
ulong rom_base; /* rom base address, viewed from host */ uint32 rom_base; /* rom base address, viewed from host */
ulong rom_base_pci; /* rom base addr, viewed from pci */ uint32 rom_base_pci; /* rom base addr, viewed from pci */
uchar interrupt_line; /* interrupt line */ uchar interrupt_line; /* interrupt line */
uchar interrupt_pin; /* interrupt pin */ uchar interrupt_pin; /* interrupt pin */
ushort bridge_control; ushort bridge_control;
@@ -98,14 +98,14 @@ typedef struct pci_info {
uchar subordinate_bus; uchar subordinate_bus;
uchar secondary_latency; uchar secondary_latency;
ushort reserved; ushort reserved;
ulong memory_base; uint32 memory_base;
ulong memory_limit; uint32 memory_limit;
ulong memory_base_upper32; uint32 memory_base_upper32;
ulong memory_limit_upper32; uint32 memory_limit_upper32;
ulong io_base; uint32 io_base;
ulong io_limit; uint32 io_limit;
ulong io_base_upper32; uint32 io_base_upper32;
ulong io_limit_upper32; uint32 io_limit_upper32;
ushort secondary_status; ushort secondary_status;
ushort bridge_control; ushort bridge_control;
#endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */ #endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */
src/add-ons/kernel/bus_managers/pci/Jamfile
+3 -2
View File
@@ -3,7 +3,7 @@ SubDir HAIKU_TOP src add-ons kernel bus_managers pci ;
UsePrivateKernelHeaders ; UsePrivateKernelHeaders ;
UsePrivateHeaders shared ; UsePrivateHeaders shared ;
UsePrivateHeaders [ FDirName kernel util ] ; UsePrivateHeaders [ FDirName kernel util ] ;
UseHeaders [ FDirName $(SUBDIR) arch $(TARGET_ARCH) ] ; UseHeaders [ FDirName $(SUBDIR) arch $(TARGET_KERNEL_ARCH) ] ;
KernelAddon pci : KernelAddon pci :
pci.cpp pci.cpp
@@ -20,4 +20,5 @@ ObjectHdrs [ FGristFiles pci_info$(SUFOBJ) ]
: [ FDirName $(TARGET_COMMON_DEBUG_OBJECT_DIR) apps devices ] ; : [ FDirName $(TARGET_COMMON_DEBUG_OBJECT_DIR) apps devices ] ;
Includes [ FGristFiles pci_info.cpp ] : <src!apps!devices>pcihdr.h ; Includes [ FGristFiles pci_info.cpp ] : <src!apps!devices>pcihdr.h ;
SubInclude HAIKU_TOP src add-ons kernel bus_managers pci arch $(TARGET_ARCH) ; SubInclude HAIKU_TOP src add-ons kernel bus_managers pci arch
$(TARGET_KERNEL_ARCH) ;
src/add-ons/kernel/bus_managers/pci/arch/x86/pci_msi.cpp
+1 -1
View File
@@ -163,7 +163,7 @@ pci_enable_msi(uint8 virtualBus, uint8 _device, uint8 function)
gPCI->WriteConfig(device, info->capability_offset + PCI_msi_control, 2, gPCI->WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
info->control_value); info->control_value);
dprintf("msi enabled: 0x%04lx\n", dprintf("msi enabled: 0x%04" B_PRIx32 "\n",
gPCI->ReadConfig(device, info->capability_offset + PCI_msi_control, 2)); gPCI->ReadConfig(device, info->capability_offset + PCI_msi_control, 2));
return B_OK; return B_OK;
} }
src/add-ons/kernel/bus_managers/pci/pci.cpp
+29 -20
View File
@@ -350,7 +350,7 @@ display_io(int argc, char **argv)
if (i != 0) if (i != 0)
kprintf("\n"); kprintf("\n");
kprintf("[0x%lx] ", address + i * itemSize); kprintf("[0x%" B_PRIx32 "] ", address + i * itemSize);
if (num > displayWidth) { if (num > displayWidth) {
// make sure the spacing in the last line is correct // make sure the spacing in the last line is correct
@@ -362,13 +362,13 @@ display_io(int argc, char **argv)
switch (itemSize) { switch (itemSize) {
case 1: case 1:
kprintf(" %02x", pci_read_io_8(address + i * itemSize)); kprintf(" %02" B_PRIx8, pci_read_io_8(address + i * itemSize));
break; break;
case 2: case 2:
kprintf(" %04x", pci_read_io_16(address + i * itemSize)); kprintf(" %04" B_PRIx16, pci_read_io_16(address + i * itemSize));
break; break;
case 4: case 4:
kprintf(" %08lx", pci_read_io_32(address + i * itemSize)); kprintf(" %08" B_PRIx32, pci_read_io_32(address + i * itemSize));
break; break;
} }
} }
@@ -569,7 +569,7 @@ PCI::~PCI()
status_t status_t
PCI::_CreateVirtualBus(int domain, uint8 bus, uint8 *virtualBus) PCI::_CreateVirtualBus(int domain, uint8 bus, uint8 *virtualBus)
{ {
#if defined(__INTEL__) #if defined(__INTEL__) || defined(__x86_64__)
// IA32 doesn't use domains // IA32 doesn't use domains
if (domain) if (domain)
@@ -607,7 +607,7 @@ PCI::_CreateVirtualBus(int domain, uint8 bus, uint8 *virtualBus)
status_t status_t
PCI::ResolveVirtualBus(uint8 virtualBus, int *domain, uint8 *bus) PCI::ResolveVirtualBus(uint8 virtualBus, int *domain, uint8 *bus)
{ {
#if defined(__INTEL__) #if defined(__INTEL__) || defined(__x86_64__)
// IA32 doesn't use domains // IA32 doesn't use domains
*bus = virtualBus; *bus = virtualBus;
@@ -739,8 +739,11 @@ PCI::_EnumerateBus(int domain, uint8 bus, uint8 *subordinateBus)
if (baseClass != PCI_bridge || subClass != PCI_pci) if (baseClass != PCI_bridge || subClass != PCI_pci)
continue; continue;
TRACE(("PCI: found PCI-PCI bridge: domain %u, bus %u, dev %u, func %u\n", domain, bus, dev, function)); TRACE(("PCI: found PCI-PCI bridge: domain %u, bus %u, dev %u, func %u\n",
TRACE(("PCI: original settings: pcicmd %04lx, primary-bus %lu, secondary-bus %lu, subordinate-bus %lu\n", domain, bus, dev, function));
TRACE(("PCI: original settings: pcicmd %04" B_PRIx32 ", primary-bus "
"%" B_PRIu32 ", secondary-bus %" B_PRIu32 ", subordinate-bus "
"%" B_PRIu32 "\n",
ReadConfig(domain, bus, dev, function, PCI_command, 2), ReadConfig(domain, bus, dev, function, PCI_command, 2),
ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
@@ -758,7 +761,9 @@ PCI::_EnumerateBus(int domain, uint8 bus, uint8 *subordinateBus)
WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1, 0); WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1, 0);
WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 0); WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 0);
TRACE(("PCI: disabled settings: pcicmd %04lx, primary-bus %lu, secondary-bus %lu, subordinate-bus %lu\n", TRACE(("PCI: disabled settings: pcicmd %04" B_PRIx32 ", primary-bus "
"%" B_PRIu32 ", secondary-bus %" B_PRIu32 ", subordinate-bus "
"%" B_PRIu32 "\n",
ReadConfig(domain, bus, dev, function, PCI_command, 2), ReadConfig(domain, bus, dev, function, PCI_command, 2),
ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
@@ -803,7 +808,9 @@ PCI::_EnumerateBus(int domain, uint8 bus, uint8 *subordinateBus)
pcicmd |= PCI_command_io | PCI_command_memory | PCI_command_master; pcicmd |= PCI_command_io | PCI_command_memory | PCI_command_master;
WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd); WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd);
TRACE(("PCI: probing settings: pcicmd %04lx, primary-bus %lu, secondary-bus %lu, subordinate-bus %lu\n", TRACE(("PCI: probing settings: pcicmd %04" B_PRIx32 ", primary-bus "
"%" B_PRIu32 ", secondary-bus %" B_PRIu32 ", subordinate-bus "
"%" B_PRIu32 "\n",
ReadConfig(domain, bus, dev, function, PCI_command, 2), ReadConfig(domain, bus, dev, function, PCI_command, 2),
ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
@@ -815,7 +822,9 @@ PCI::_EnumerateBus(int domain, uint8 bus, uint8 *subordinateBus)
// close Scheunentor // close Scheunentor
WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, lastUsedBusNumber); WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, lastUsedBusNumber);
TRACE(("PCI: configured settings: pcicmd %04lx, primary-bus %lu, secondary-bus %lu, subordinate-bus %lu\n", TRACE(("PCI: configured settings: pcicmd %04" B_PRIx32 ", primary-bus "
"%" B_PRIu32 ", secondary-bus %" B_PRIu32 ", subordinate-bus "
"%" B_PRIu32 "\n",
ReadConfig(domain, bus, dev, function, PCI_command, 2), ReadConfig(domain, bus, dev, function, PCI_command, 2),
ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_primary_bus, 1),
ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1), ReadConfig(domain, bus, dev, function, PCI_secondary_bus, 1),
@@ -1236,11 +1245,11 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
PCI_command, 2, pcicmd); PCI_command, 2, pcicmd);
dev->info.u.h0.rom_base = (ulong)pci_ram_address( dev->info.u.h0.rom_base = (addr_t)pci_ram_address(
(void *)dev->info.u.h0.rom_base_pci); (void *)(addr_t)dev->info.u.h0.rom_base_pci);
for (int i = 0; i < 6; i++) { for (int i = 0; i < 6; i++) {
dev->info.u.h0.base_registers[i] = (ulong)pci_ram_address( dev->info.u.h0.base_registers[i] = (addr_t)pci_ram_address(
(void *)dev->info.u.h0.base_registers_pci[i]); (void *)(addr_t)dev->info.u.h0.base_registers_pci[i]);
} }
dev->info.u.h0.cardbus_cis = ReadConfig(dev->domain, dev->bus, dev->info.u.h0.cardbus_cis = ReadConfig(dev->domain, dev->bus,
@@ -1282,11 +1291,11 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
PCI_command, 2, pcicmd); PCI_command, 2, pcicmd);
dev->info.u.h1.rom_base = (ulong)pci_ram_address( dev->info.u.h1.rom_base = (addr_t)pci_ram_address(
(void *)dev->info.u.h1.rom_base_pci); (void *)(addr_t)dev->info.u.h1.rom_base_pci);
for (int i = 0; i < 2; i++) { for (int i = 0; i < 2; i++) {
dev->info.u.h1.base_registers[i] = (ulong)pci_ram_address( dev->info.u.h1.base_registers[i] = (addr_t)pci_ram_address(
(void *)dev->info.u.h1.base_registers_pci[i]); (void *)(addr_t)dev->info.u.h1.base_registers_pci[i]);
} }
dev->info.u.h1.primary_bus = ReadConfig(dev->domain, dev->bus, dev->info.u.h1.primary_bus = ReadConfig(dev->domain, dev->bus,
@@ -1397,7 +1406,7 @@ PCI::_RefreshDeviceInfo(PCIBus *bus)
for (PCIDev *dev = bus->child; dev; dev = dev->next) { for (PCIDev *dev = bus->child; dev; dev = dev->next) {
_ReadBasicInfo(dev); _ReadBasicInfo(dev);
_ReadHeaderInfo(dev); _ReadHeaderInfo(dev);
#ifdef __INTEL__ #if defined(__INTEL__) || defined(__x86_64__)
pci_read_arch_info(dev); pci_read_arch_info(dev);
#endif #endif
if (dev->child) if (dev->child)
src/add-ons/kernel/bus_managers/pci/pci.h
+2 -2
View File
@@ -15,7 +15,7 @@
#include "pci_controller.h" #include "pci_controller.h"
#ifdef __INTEL__ #if defined(__INTEL__) || defined(__x86_64__)
#include "pci_arch_info.h" #include "pci_arch_info.h"
#endif #endif
@@ -47,7 +47,7 @@ struct PCIDev {
uint8 device; uint8 device;
uint8 function; uint8 function;
pci_info info; pci_info info;
#ifdef __INTEL__ #if defined(__INTEL__) || defined(__x86_64__)
pci_arch_info arch_info; pci_arch_info arch_info;
#endif #endif
}; };
src/add-ons/kernel/bus_managers/pci/pci_fixup.cpp
+11 -11
View File
@@ -44,7 +44,7 @@ jmicron_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device,
// Read controller control register (0x40). // Read controller control register (0x40).
uint32 val = pci->ReadConfig(domain, bus, device, function, 0x40, 4); uint32 val = pci->ReadConfig(domain, bus, device, function, 0x40, 4);
dprintf("jmicron_fixup_ahci: Register 0x40 : 0x%08lx\n", val); dprintf("jmicron_fixup_ahci: Register 0x40 : 0x%08" B_PRIx32 "\n", val);
// Clear bits. // Clear bits.
val &= ~(1 << 1); val &= ~(1 << 1);
@@ -67,7 +67,7 @@ jmicron_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device,
val |= (1 << 14); val |= (1 << 14);
val |= (1 << 23); val |= (1 << 23);
dprintf("jmicron_fixup_ahci: Register 0x40 : 0x%08lx\n", val); dprintf("jmicron_fixup_ahci: Register 0x40 : 0x%08" B_PRIx32 "\n", val);
pci->WriteConfig(domain, bus, device, function, 0x40, 4, val); pci->WriteConfig(domain, bus, device, function, 0x40, 4, val);
// Read IRQ from controller at function 0 and assign this IRQ to the // Read IRQ from controller at function 0 and assign this IRQ to the
@@ -108,9 +108,9 @@ intel_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function,
dprintf("intel_fixup_ahci: domain %u, bus %u, device %u, function %u, " dprintf("intel_fixup_ahci: domain %u, bus %u, device %u, function %u, "
"deviceId 0x%04x\n", domain, bus, device, function, deviceId); "deviceId 0x%04x\n", domain, bus, device, function, deviceId);
dprintf("intel_fixup_ahci: 0x24: 0x%08lx\n", dprintf("intel_fixup_ahci: 0x24: 0x%08" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x24, 4)); pci->ReadConfig(domain, bus, device, function, 0x24, 4));
dprintf("intel_fixup_ahci: 0x90: 0x%02lx\n", dprintf("intel_fixup_ahci: 0x90: 0x%02" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x90, 1)); pci->ReadConfig(domain, bus, device, function, 0x90, 1));
uint8 map = pci->ReadConfig(domain, bus, device, function, 0x90, 1); uint8 map = pci->ReadConfig(domain, bus, device, function, 0x90, 1);
@@ -125,10 +125,10 @@ intel_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function,
pcicmd & ~(PCI_command_io | PCI_command_memory)); pcicmd & ~(PCI_command_io | PCI_command_memory));
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff); pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
dprintf("intel_fixup_ahci: ide-bar5 bits-1: 0x%08lx\n", dprintf("intel_fixup_ahci: ide-bar5 bits-1: 0x%08" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x24, 4)); pci->ReadConfig(domain, bus, device, function, 0x24, 4));
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0); pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0);
dprintf("intel_fixup_ahci: ide-bar5 bits-0: 0x%08lx\n", dprintf("intel_fixup_ahci: ide-bar5 bits-0: 0x%08" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x24, 4)); pci->ReadConfig(domain, bus, device, function, 0x24, 4));
map &= ~0x03; map &= ~0x03;
@@ -136,10 +136,10 @@ intel_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function,
pci->WriteConfig(domain, bus, device, function, 0x90, 1, map); pci->WriteConfig(domain, bus, device, function, 0x90, 1, map);
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff); pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
dprintf("intel_fixup_ahci: ahci-bar5 bits-1: 0x%08lx\n", dprintf("intel_fixup_ahci: ahci-bar5 bits-1: 0x%08" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x24, 4)); pci->ReadConfig(domain, bus, device, function, 0x24, 4));
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0); pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0);
dprintf("intel_fixup_ahci: ahci-bar5 bits-0: 0x%08lx\n", dprintf("intel_fixup_ahci: ahci-bar5 bits-0: 0x%08" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x24, 4)); pci->ReadConfig(domain, bus, device, function, 0x24, 4));
if (deviceId == 0x27c0 || deviceId == 0x27c4) // restore on ICH7 if (deviceId == 0x27c0 || deviceId == 0x27c4) // restore on ICH7
@@ -148,9 +148,9 @@ intel_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function,
pci->WriteConfig(domain, bus, device, function, PCI_command, 2, pcicmd); pci->WriteConfig(domain, bus, device, function, PCI_command, 2, pcicmd);
} }
dprintf("intel_fixup_ahci: 0x24: 0x%08lx\n", dprintf("intel_fixup_ahci: 0x24: 0x%08" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x24, 4)); pci->ReadConfig(domain, bus, device, function, 0x24, 4));
dprintf("intel_fixup_ahci: 0x90: 0x%02lx\n", dprintf("intel_fixup_ahci: 0x90: 0x%02" B_PRIx32 "\n",
pci->ReadConfig(domain, bus, device, function, 0x90, 1)); pci->ReadConfig(domain, bus, device, function, 0x90, 1));
} }
@@ -158,7 +158,7 @@ intel_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function,
static void static void
ati_fixup_ixp(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function, uint16 deviceId) ati_fixup_ixp(PCI *pci, int domain, uint8 bus, uint8 device, uint8 function, uint16 deviceId)
{ {
#ifdef __INTEL__ #if defined(__INTEL__) || defined(__x86_64__)
/* ATI Technologies Inc, IXP chipset: /* ATI Technologies Inc, IXP chipset:
* This chipset seems broken, at least on my laptop I must force * This chipset seems broken, at least on my laptop I must force
* the timer IRQ trigger mode, else no interrupt comes in. * the timer IRQ trigger mode, else no interrupt comes in.
src/add-ons/kernel/bus_managers/pci/pci_info.cpp
+36 -27
View File
@@ -13,7 +13,7 @@
#include "pci.h" #include "pci.h"
#define PCI_VERBOSE 1 #define PCI_VERBOSE 1
#ifdef __INTEL__ #if defined(__INTEL__) || defined(__x86_64__)
// enabling it makes the pci bus_manager binary about 1MB // enabling it makes the pci bus_manager binary about 1MB
// some other platforms have issues with floppy image size... // some other platforms have issues with floppy image size...
// TODO: Move this define to BuildSetup? // TODO: Move this define to BuildSetup?
@@ -42,11 +42,13 @@ print_pci2pci_bridge_info(const pci_info *info, bool verbose)
uint32 io_limit = (((uint32)info->u.h1.io_limit & 0xf0) << 8) + 0xfff; uint32 io_limit = (((uint32)info->u.h1.io_limit & 0xf0) << 8) + 0xfff;
if (info->u.h1.io_limit & 1) if (info->u.h1.io_limit & 1)
io_limit += info->u.h1.io_limit_upper16 << 16; io_limit += info->u.h1.io_limit_upper16 << 16;
TRACE(("PCI: I/O window %04lx-%04lx\n", io_base, io_limit)); TRACE(("PCI: I/O window %04" B_PRIx32 "-%04" B_PRIx32 "\n", io_base,
io_limit));
uint32 memory_base = ((uint32)info->u.h1.memory_base & 0xfff0) << 16; uint32 memory_base = ((uint32)info->u.h1.memory_base & 0xfff0) << 16;
uint32 memory_limit = (((uint32)info->u.h1.memory_limit & 0xfff0) << 16) uint32 memory_limit = (((uint32)info->u.h1.memory_limit & 0xfff0) << 16)
+ 0xfffff; + 0xfffff;
TRACE(("PCI: memory window %04lx-%04lx\n", memory_base, memory_limit)); TRACE(("PCI: memory window %04" B_PRIx32 "-%04" B_PRIx32 "\n",
memory_base, memory_limit));
uint64 prefetchable_memory_base = uint64 prefetchable_memory_base =
((uint32)info->u.h1.prefetchable_memory_base & 0xfff0) << 16; ((uint32)info->u.h1.prefetchable_memory_base & 0xfff0) << 16;
if (info->u.h1.prefetchable_memory_base & 1) { if (info->u.h1.prefetchable_memory_base & 1) {
@@ -60,18 +62,19 @@ print_pci2pci_bridge_info(const pci_info *info, bool verbose)
prefetchable_memory_limit += prefetchable_memory_limit +=
(uint64)info->u.h1.prefetchable_memory_limit_upper32 << 32; (uint64)info->u.h1.prefetchable_memory_limit_upper32 << 32;
} }
TRACE(("PCI: prefetchable memory window %016llx-%016llx\n", TRACE(("PCI: prefetchable memory window %016" B_PRIx64 "-%016" B_PRIx64 "\n",
prefetchable_memory_base, prefetchable_memory_limit)); prefetchable_memory_base, prefetchable_memory_limit));
TRACE(("PCI: bridge_control %04x, secondary_status %04x\n", TRACE(("PCI: bridge_control %04x, secondary_status %04x\n",
info->u.h1.bridge_control, info->u.h1.secondary_status)); info->u.h1.bridge_control, info->u.h1.secondary_status));
TRACE(("PCI: interrupt_line %02x, interrupt_pin %02x\n", TRACE(("PCI: interrupt_line %02x, interrupt_pin %02x\n",
info->u.h1.interrupt_line, info->u.h1.interrupt_pin)); info->u.h1.interrupt_line, info->u.h1.interrupt_pin));
TRACE(("PCI: ROM base host %08lx, pci %08lx, size ??\n", TRACE(("PCI: ROM base host %08" B_PRIx32 ", pci %08" B_PRIx32 ", size ??\n",
info->u.h1.rom_base, info->u.h1.rom_base_pci)); info->u.h1.rom_base, info->u.h1.rom_base_pci));
for (int i = 0; i < 2; i++) for (int i = 0; i < 2; i++)
TRACE(("PCI: base reg %d: host %08lx, pci %08lx, size %08lx, flags %02x\n", TRACE(("PCI: base reg %d: host %08" B_PRIx32 ", pci %08" B_PRIx32 ", "
i, info->u.h1.base_registers[i], info->u.h1.base_registers_pci[i], "size %08" B_PRIx32 ", flags %02x\n", i, info->u.h1.base_registers[i],
info->u.h1.base_register_sizes[i], info->u.h1.base_register_flags[i])); info->u.h1.base_registers_pci[i], info->u.h1.base_register_sizes[i],
info->u.h1.base_register_flags[i]));
} }
@@ -79,18 +82,20 @@ static void
print_pci2cardbus_bridge_info(const pci_info *info, bool verbose) print_pci2cardbus_bridge_info(const pci_info *info, bool verbose)
{ {
TRACE(("PCI: subsystem_id %04x, subsystem_vendor_id %04x\n", TRACE(("PCI: subsystem_id %04x, subsystem_vendor_id %04x\n",
info->u.h2.subsystem_id, info->u.h2.subsystem_vendor_id)); info->u.h2.subsystem_id, info->u.h2.subsystem_vendor_id));
TRACE(("PCI: primary_bus %02x, secondary_bus %02x, subordinate_bus %02x, secondary_latency %02x\n", TRACE(("PCI: primary_bus %02x, secondary_bus %02x, subordinate_bus %02x, "
info->u.h2.primary_bus, info->u.h2.secondary_bus, info->u.h2.subordinate_bus, info->u.h2.secondary_latency)); "secondary_latency %02x\n", info->u.h2.primary_bus,
info->u.h2.secondary_bus, info->u.h2.subordinate_bus,
info->u.h2.secondary_latency));
TRACE(("PCI: bridge_control %04x, secondary_status %04x\n", TRACE(("PCI: bridge_control %04x, secondary_status %04x\n",
info->u.h2.bridge_control, info->u.h2.secondary_status)); info->u.h2.bridge_control, info->u.h2.secondary_status));
TRACE(("PCI: memory_base_upper32 %08lx, memory_base %08lx\n", TRACE(("PCI: memory_base_upper32 %08" B_PRIx32 ", memory_base %08"
info->u.h2.memory_base_upper32, info->u.h2.memory_base)); B_PRIx32 "\n", info->u.h2.memory_base_upper32, info->u.h2.memory_base));
TRACE(("PCI: memory_limit_upper32 %08lx, memory_limit %08lx\n", TRACE(("PCI: memory_limit_upper32 %08" B_PRIx32 ", memory_limit %08"
info->u.h2.memory_limit_upper32, info->u.h2.memory_limit)); B_PRIx32 "\n", info->u.h2.memory_limit_upper32, info->u.h2.memory_limit));
TRACE(("PCI: io_base_upper32 %08lx, io_base %08lx\n", TRACE(("PCI: io_base_upper32 %08" B_PRIx32 ", io_base %08" B_PRIx32 "\n",
info->u.h2.io_base_upper32, info->u.h2.io_base)); info->u.h2.io_base_upper32, info->u.h2.io_base));
TRACE(("PCI: io_limit_upper32 %08lx, io_limit %08lx\n", TRACE(("PCI: io_limit_upper32 %08" B_PRIx32 ", io_limit %08" B_PRIx32 "\n",
info->u.h2.io_limit_upper32, info->u.h2.io_limit)); info->u.h2.io_limit_upper32, info->u.h2.io_limit));
} }
@@ -98,16 +103,20 @@ print_pci2cardbus_bridge_info(const pci_info *info, bool verbose)
static void static void
print_generic_info(const pci_info *info, bool verbose) print_generic_info(const pci_info *info, bool verbose)
{ {
TRACE(("PCI: ROM base host %08lx, pci %08lx, size %08lx\n", TRACE(("PCI: ROM base host %08" B_PRIx32 ", pci %08" B_PRIx32 ", size "
info->u.h0.rom_base, info->u.h0.rom_base_pci, info->u.h0.rom_size)); "%08" B_PRIx32 "\n", info->u.h0.rom_base, info->u.h0.rom_base_pci,
TRACE(("PCI: cardbus_CIS %08lx, subsystem_id %04x, subsystem_vendor_id %04x\n", info->u.h0.rom_size));
info->u.h0.cardbus_cis, info->u.h0.subsystem_id, info->u.h0.subsystem_vendor_id)); TRACE(("PCI: cardbus_CIS %08" B_PRIx32 ", subsystem_id %04x, "
TRACE(("PCI: interrupt_line %02x, interrupt_pin %02x, min_grant %02x, max_latency %02x\n", "subsystem_vendor_id %04x\n", info->u.h0.cardbus_cis,
info->u.h0.interrupt_line, info->u.h0.interrupt_pin, info->u.h0.min_grant, info->u.h0.max_latency)); info->u.h0.subsystem_id, info->u.h0.subsystem_vendor_id));
TRACE(("PCI: interrupt_line %02x, interrupt_pin %02x, min_grant %02x, "
"max_latency %02x\n", info->u.h0.interrupt_line, info->u.h0.interrupt_pin,
info->u.h0.min_grant, info->u.h0.max_latency));
for (int i = 0; i < 6; i++) for (int i = 0; i < 6; i++)
TRACE(("PCI: base reg %d: host %08lx, pci %08lx, size %08lx, flags %02x\n", TRACE(("PCI: base reg %d: host %08" B_PRIx32 ", pci %08" B_PRIx32 ", "
i, info->u.h0.base_registers[i], info->u.h0.base_registers_pci[i], "size %08" B_PRIx32 ", flags %02x\n", i, info->u.h0.base_registers[i],
info->u.h0.base_register_sizes[i], info->u.h0.base_register_flags[i])); info->u.h0.base_registers_pci[i], info->u.h0.base_register_sizes[i],
info->u.h0.base_register_flags[i]));
} }
src/add-ons/kernel/bus_managers/pci/pci_module.cpp
+1 -1
View File
@@ -89,7 +89,7 @@ module_info *modules[] = {
(module_info *)&gPCIRootModule, (module_info *)&gPCIRootModule,
(module_info *)&gPCIDeviceModule, (module_info *)&gPCIDeviceModule,
(module_info *)&gPCILegacyDriverModule, (module_info *)&gPCILegacyDriverModule,
#ifdef __INTEL__ #if defined(__INTEL__) || defined(__x86_64__)
// add platforms when they provide an arch specific module // add platforms when they provide an arch specific module
(module_info *)&gPCIArchModule, (module_info *)&gPCIArchModule,
#endif #endif