From 148077d71e26aed0e0f1d014c08a9939a9663979 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Sun, 6 Sep 2009 10:20:42 +0000 Subject: [PATCH] the previous commit shifted the PLLsel problem from digitally connected screens to analog connected screens apparantly. That is now fixed and both should work OK. Bumped version to 1.01. +alphabranch. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32958 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- headers/private/graphics/nvidia/nv_macros.h | 1 + src/add-ons/accelerants/nvidia/engine/nv_dac.c | 6 ++++-- src/add-ons/accelerants/nvidia/engine/nv_dac2.c | 10 ++++------ src/add-ons/accelerants/nvidia/engine/nv_general.c | 2 +- src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html | 2 +- 5 files changed, 11 insertions(+), 10 deletions(-) diff --git a/headers/private/graphics/nvidia/nv_macros.h b/headers/private/graphics/nvidia/nv_macros.h index b5bc4450e3..40af20ccd3 100644 --- a/headers/private/graphics/nvidia/nv_macros.h +++ b/headers/private/graphics/nvidia/nv_macros.h @@ -651,6 +651,7 @@ #define NVDAC_PLLSEL 0x0068050c #define NVDAC_OUTPUT 0x0068052c #define NVDAC_PIXPLLC2 0x00680578 +#define NVDAC_NV40_PLLSEL2 0x00680580 #define NVDAC_GENCTRL 0x00680600 #define NVDAC_TSTCTRL 0x00680608 #define NVDAC_TSTDATA 0x00680610 diff --git a/src/add-ons/accelerants/nvidia/engine/nv_dac.c b/src/add-ons/accelerants/nvidia/engine/nv_dac.c index 7c788c3f46..6b7a5f75a8 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_dac.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_dac.c @@ -206,10 +206,12 @@ status_t nv_dac_set_pix_pll(display_mode target) /* note: * setup PLL assignment _after_ programming PLL */ if (si->ps.secondary_head) { - if (si->ps.card_arch < NV40A) + if (si->ps.card_arch < NV40A) { DACW(PLLSEL, 0x30000f00); - else + } else { + DACW(NV40_PLLSEL2, (DACR(NV40_PLLSEL2) & ~0x10000100)); DACW(PLLSEL, 0x30000f04); + } } else { DACW(PLLSEL, 0x10000700); } diff --git a/src/add-ons/accelerants/nvidia/engine/nv_dac2.c b/src/add-ons/accelerants/nvidia/engine/nv_dac2.c index 063750fafd..1f5adeb334 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_dac2.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_dac2.c @@ -208,13 +208,11 @@ status_t nv_dac2_set_pix_pll(display_mode target) /* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */ /* note: * setup PLL assignment _after_ programming PLL */ - if (si->ps.secondary_head) { - if (si->ps.card_arch < NV40A) - DACW(PLLSEL, 0x30000f00); - else - DACW(PLLSEL, 0x30000f04); + if (si->ps.card_arch < NV40A) { + DACW(PLLSEL, 0x30000f00); } else { - DACW(PLLSEL, 0x10000700); + DACW(NV40_PLLSEL2, (DACR(NV40_PLLSEL2) & ~0x10000100)); + DACW(PLLSEL, 0x30000f04); } LOG(2,("DAC2: PIX PLL frequency should be locked now...\n")); diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c index 2c806fc00b..3506a5fe31 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_general.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c @@ -92,7 +92,7 @@ status_t nv_general_powerup() { status_t status; - LOG(1,("POWERUP: Haiku nVidia Accelerant 1.00 running.\n")); + LOG(1,("POWERUP: Haiku nVidia Accelerant 1.01 running.\n")); /* log VBLANK INT usability status */ if (si->ps.int_assigned) diff --git a/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html b/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html index 0b46a467e7..85ae3a6b12 100644 --- a/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html +++ b/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html @@ -4,7 +4,7 @@

Changes done for each driverversion:

-

head (SVN 1.00, Rudolf)

+

head (SVN 1.01, Rudolf)