From 14943b5b8bd02664ed24734ffabefaa20cb65c7b Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Tue, 14 Aug 2012 12:30:14 -0500 Subject: [PATCH] radeon_hd: cleanup some logic; no functional change --- src/add-ons/accelerants/radeon_hd/display.cpp | 2 ++ src/add-ons/accelerants/radeon_hd/encoder.cpp | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/src/add-ons/accelerants/radeon_hd/display.cpp b/src/add-ons/accelerants/radeon_hd/display.cpp index 41b4b828ce..1d9d10ffbd 100644 --- a/src/add-ons/accelerants/radeon_hd/display.cpp +++ b/src/add-ons/accelerants/radeon_hd/display.cpp @@ -272,6 +272,8 @@ detect_displays() encoder_external_setup(id, 23860, EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); gDisplay[displayIndex]->attached = true; + + // TODO: DDC Router switching for DisplayPort (and others?) } else if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) { #endif if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) { diff --git a/src/add-ons/accelerants/radeon_hd/encoder.cpp b/src/add-ons/accelerants/radeon_hd/encoder.cpp index e9a7fb5751..77f4560fe4 100644 --- a/src/add-ons/accelerants/radeon_hd/encoder.cpp +++ b/src/add-ons/accelerants/radeon_hd/encoder.cpp @@ -1351,9 +1351,11 @@ transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock, // Select the PLL for the PHY // DP PHY to be clocked from external src if possible + + // DCE4 has external DCPLL clock for DP if (isDP && gInfo->dpExternalClock) { - // use external clock source - args.v3.acConfig.ucRefClkSource = ATOM_DCPLL; + // use external clock source (id'ed to 2 on DCE4) + args.v3.acConfig.ucRefClkSource = 2; // EXT clock } else args.v3.acConfig.ucRefClkSource = pll->id; @@ -1417,6 +1419,7 @@ transmitter_dig_setup(uint32 connectorIndex, uint32 pixelClock, // Select the PLL for the PHY // DP PHY to be clocked from external src if possible + // DCE5, DCPLL usually generates the DP ref clock if (isDP) { if (gInfo->dpExternalClock > 0) { args.v4.acConfig.ucRefClkSource