From 1607b8e50319953c52fa9404b0d5c9989289881f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Axel=20D=C3=B6rfler?= Date: Sun, 16 Dec 2007 10:56:30 +0000 Subject: [PATCH] * Added Broadcom BCM570x driver from FreeBSD (bge). Does not compile yet, needs a bit more work on the compatibility layer. * Added nVidia nForce MCP driver (nfe) from FreeBSD. Compiles and might even work - please test. It would also be nice to know if your PHY is detected correctly (see syslog output). git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@23124 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/kernel/drivers/network/Jamfile | 4 +- .../drivers/network/broadcom_bcm570x/Jamfile | 3 + .../network/broadcom_bcm570x/dev/Jamfile | 4 + .../network/broadcom_bcm570x/dev/bge/Jamfile | 18 + .../network/broadcom_bcm570x/dev/bge/glue.c | 27 + .../network/broadcom_bcm570x/dev/bge/if_bge.c | 4539 +++++++++++++++++ .../broadcom_bcm570x/dev/bge/if_bgereg.h | 2516 +++++++++ .../network/broadcom_bcm570x/dev/mii/Jamfile | 15 + .../broadcom_bcm570x/dev/mii/brgphyreg.h | 364 ++ .../broadcom_bcm570x/dev/mii/miidevs.h | 12 + .../network/broadcom_bcm570x/dev/mii/ukphy.c | 220 + .../broadcom_bcm570x/dev/mii/ukphy_subr.c | 129 + .../kernel/drivers/network/nforce/Jamfile | 3 + .../kernel/drivers/network/nforce/dev/Jamfile | 4 + .../drivers/network/nforce/dev/mii/Jamfile | 15 + .../drivers/network/nforce/dev/mii/ciphy.c | 424 ++ .../drivers/network/nforce/dev/mii/ciphyreg.h | 361 ++ .../drivers/network/nforce/dev/mii/miidevs.h | 21 + .../drivers/network/nforce/dev/mii/ukphy.c | 220 + .../network/nforce/dev/mii/ukphy_subr.c | 129 + .../drivers/network/nforce/dev/nfe/Jamfile | 15 + .../drivers/network/nforce/dev/nfe/glue.c | 31 + .../drivers/network/nforce/dev/nfe/if_nfe.c | 3218 ++++++++++++ .../network/nforce/dev/nfe/if_nfereg.h | 322 ++ .../network/nforce/dev/nfe/if_nfevar.h | 138 + 25 files changed, 12751 insertions(+), 1 deletion(-) create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/glue.c create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bge.c create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bgereg.h create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/brgphyreg.h create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/miidevs.h create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy.c create mode 100644 src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy_subr.c create mode 100644 src/add-ons/kernel/drivers/network/nforce/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/mii/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphy.c create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphyreg.h create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/mii/miidevs.h create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy.c create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy_subr.c create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/nfe/Jamfile create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/nfe/glue.c create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h create mode 100644 src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfevar.h diff --git a/src/add-ons/kernel/drivers/network/Jamfile b/src/add-ons/kernel/drivers/network/Jamfile index 7f63c74865..5039fabb6d 100644 --- a/src/add-ons/kernel/drivers/network/Jamfile +++ b/src/add-ons/kernel/drivers/network/Jamfile @@ -12,10 +12,12 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network via_rhine ; SubInclude HAIKU_TOP src add-ons kernel drivers network vlance ; SubInclude HAIKU_TOP src add-ons kernel drivers network wb840 ; -# FreeBSD 6.2 drivers +# FreeBSD 7 drivers SubInclude HAIKU_TOP src add-ons kernel drivers network 3com ; +SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x ; SubInclude HAIKU_TOP src add-ons kernel drivers network ipro100 ; SubInclude HAIKU_TOP src add-ons kernel drivers network marvell_yukon ; +SubInclude HAIKU_TOP src add-ons kernel drivers network nforce ; SubInclude HAIKU_TOP src add-ons kernel drivers network pcnet ; SubIncludeGPL HAIKU_TOP src add-ons kernel drivers network bcm440x ; diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/Jamfile b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/Jamfile new file mode 100644 index 0000000000..c4cef2d7b1 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/Jamfile @@ -0,0 +1,3 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x ; + +SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev ; diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/Jamfile b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/Jamfile new file mode 100644 index 0000000000..29f51f6702 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/Jamfile @@ -0,0 +1,4 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev ; + +SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev bge ; +SubInclude HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev mii ; diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/Jamfile b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/Jamfile new file mode 100644 index 0000000000..79833bdf21 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/Jamfile @@ -0,0 +1,18 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev bge ; + +SubDirCcFlags -Wall ; + +UsePrivateHeaders kernel net ; + +UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ; +UseHeaders [ FDirName $(SUBDIR) .. mii ] : true ; +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ; + +KernelAddon broadcom_bcm570x : + if_bge.c + glue.c + : libfreebsd_network.a broadcom_bcm570x_mii.a + ; + diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/glue.c b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/glue.c new file mode 100644 index 0000000000..6d6bbc03d1 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/glue.c @@ -0,0 +1,27 @@ +/* + * Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved. + * Distributed under the terms of the MIT License. + */ + + +#include + + +HAIKU_FBSD_DRIVER_GLUE(broadcom_bcm570x, bge, pci); +HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_SWI_TASKQUEUE); + + +extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus); + + +driver_t * +__haiku_select_miibus_driver(device_t dev) +{ + driver_t *drivers[] = { + DRIVER_MODULE_NAME(ukphy, miibus), + NULL + }; + + return __haiku_probe_miibus(dev, drivers); +} + diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bge.c b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bge.c new file mode 100644 index 0000000000..928bd0fe50 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bge.c @@ -0,0 +1,4539 @@ +/*- + * Copyright (c) 2001 Wind River Systems + * Copyright (c) 1997, 1998, 1999, 2001 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.198 2007/09/30 11:05:14 marius Exp $"); + +/* + * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. + * + * The Broadcom BCM5700 is based on technology originally developed by + * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet + * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has + * two on-board MIPS R4000 CPUs and can have as much as 16MB of external + * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo + * frames, highly configurable RX filtering, and 16 RX and TX queues + * (which, along with RX filter rules, can be used for QOS applications). + * Other features, such as TCP segmentation, may be available as part + * of value-added firmware updates. Unlike the Tigon I and Tigon II, + * firmware images can be stored in hardware and need not be compiled + * into the driver. + * + * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will + * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. + * + * The BCM5701 is a single-chip solution incorporating both the BCM5700 + * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 + * does not support external SSRAM. + * + * Broadcom also produces a variation of the BCM5700 under the "Altima" + * brand name, which is functionally similar but lacks PCI-X support. + * + * Without external SSRAM, you can only have at most 4 TX rings, + * and the use of the mini RX ring is disabled. This seems to imply + * that these features are simply not available on the BCM5701. As a + * result, this driver does not implement any support for the mini RX + * ring. + */ + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include "opt_device_polling.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include "miidevs.h" +#include + +#ifdef __sparc64__ +#include +#include +#include +#include +#endif + +#include +#include + +#include + +#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) +#define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ + +MODULE_DEPEND(bge, pci, 1, 1, 1); +MODULE_DEPEND(bge, ether, 1, 1, 1); +MODULE_DEPEND(bge, miibus, 1, 1, 1); + +/* "device miibus" required. See GENERIC if you get errors here. */ +#include "miibus_if.h" + +/* + * Various supported device vendors/types and their names. Note: the + * spec seems to indicate that the hardware still has Alteon's vendor + * ID burned into it, though it will always be overriden by the vendor + * ID in the EEPROM. Just to be safe, we cover all possibilities. + */ +static struct bge_type { + uint16_t bge_vid; + uint16_t bge_did; +} bge_devs[] = { + { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, + { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, + + { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, + { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, + { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, + + { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, + + { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, + { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, + + { SK_VENDORID, SK_DEVICEID_ALTIMA }, + + { TC_VENDORID, TC_DEVICEID_3C996 }, + + { 0, 0 } +}; + +static const struct bge_vendor { + uint16_t v_id; + const char *v_name; +} bge_vendors[] = { + { ALTEON_VENDORID, "Alteon" }, + { ALTIMA_VENDORID, "Altima" }, + { APPLE_VENDORID, "Apple" }, + { BCOM_VENDORID, "Broadcom" }, + { SK_VENDORID, "SysKonnect" }, + { TC_VENDORID, "3Com" }, + + { 0, NULL } +}; + +static const struct bge_revision { + uint32_t br_chipid; + const char *br_name; +} bge_revisions[] = { + { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, + { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, + { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, + { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, + { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, + { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, + { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, + { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, + { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, + { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, + { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, + { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, + { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, + { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, + { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, + { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, + { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, + { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, + { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, + { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, + { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, + { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, + { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, + { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, + { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, + { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, + { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, + { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, + { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, + { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, + { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, + { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, + { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, + { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, + { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, + { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, + { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, + { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, + { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, + { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, + { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, + { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, + { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, + { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, + { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, + { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, + /* 5754 and 5787 share the same ASIC ID */ + { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, + { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, + { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, + + { 0, NULL } +}; + +/* + * Some defaults for major revisions, so that newer steppings + * that we don't know about have a shot at working. + */ +static const struct bge_revision bge_majorrevs[] = { + { BGE_ASICREV_BCM5700, "unknown BCM5700" }, + { BGE_ASICREV_BCM5701, "unknown BCM5701" }, + { BGE_ASICREV_BCM5703, "unknown BCM5703" }, + { BGE_ASICREV_BCM5704, "unknown BCM5704" }, + { BGE_ASICREV_BCM5705, "unknown BCM5705" }, + { BGE_ASICREV_BCM5750, "unknown BCM5750" }, + { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, + { BGE_ASICREV_BCM5752, "unknown BCM5752" }, + { BGE_ASICREV_BCM5780, "unknown BCM5780" }, + { BGE_ASICREV_BCM5714, "unknown BCM5714" }, + { BGE_ASICREV_BCM5755, "unknown BCM5755" }, + /* 5754 and 5787 share the same ASIC ID */ + { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, + + { 0, NULL } +}; + +#define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) +#define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) +#define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) +#define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) +#define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) + +const struct bge_revision * bge_lookup_rev(uint32_t); +const struct bge_vendor * bge_lookup_vendor(uint16_t); +static int bge_probe(device_t); +static int bge_attach(device_t); +static int bge_detach(device_t); +static int bge_suspend(device_t); +static int bge_resume(device_t); +static void bge_release_resources(struct bge_softc *); +static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); +static int bge_dma_alloc(device_t); +static void bge_dma_free(struct bge_softc *); + +static void bge_txeof(struct bge_softc *); +static void bge_rxeof(struct bge_softc *); + +static void bge_asf_driver_up (struct bge_softc *); +static void bge_tick(void *); +static void bge_stats_update(struct bge_softc *); +static void bge_stats_update_regs(struct bge_softc *); +static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); + +static void bge_intr(void *); +static void bge_start_locked(struct ifnet *); +static void bge_start(struct ifnet *); +static int bge_ioctl(struct ifnet *, u_long, caddr_t); +static void bge_init_locked(struct bge_softc *); +static void bge_init(void *); +static void bge_stop(struct bge_softc *); +static void bge_watchdog(struct bge_softc *); +static void bge_shutdown(device_t); +static int bge_ifmedia_upd_locked(struct ifnet *); +static int bge_ifmedia_upd(struct ifnet *); +static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); + +static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); +static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); + +static void bge_setpromisc(struct bge_softc *); +static void bge_setmulti(struct bge_softc *); +static void bge_setvlan(struct bge_softc *); + +static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); +static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); +static int bge_init_rx_ring_std(struct bge_softc *); +static void bge_free_rx_ring_std(struct bge_softc *); +static int bge_init_rx_ring_jumbo(struct bge_softc *); +static void bge_free_rx_ring_jumbo(struct bge_softc *); +static void bge_free_tx_ring(struct bge_softc *); +static int bge_init_tx_ring(struct bge_softc *); + +static int bge_chipinit(struct bge_softc *); +static int bge_blockinit(struct bge_softc *); + +static int bge_has_eeprom(struct bge_softc *); +static uint32_t bge_readmem_ind(struct bge_softc *, int); +static void bge_writemem_ind(struct bge_softc *, int, int); +#ifdef notdef +static uint32_t bge_readreg_ind(struct bge_softc *, int); +#endif +static void bge_writemem_direct(struct bge_softc *, int, int); +static void bge_writereg_ind(struct bge_softc *, int, int); + +static int bge_miibus_readreg(device_t, int, int); +static int bge_miibus_writereg(device_t, int, int, int); +static void bge_miibus_statchg(device_t); +#ifdef DEVICE_POLLING +static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); +#endif + +#define BGE_RESET_START 1 +#define BGE_RESET_STOP 2 +static void bge_sig_post_reset(struct bge_softc *, int); +static void bge_sig_legacy(struct bge_softc *, int); +static void bge_sig_pre_reset(struct bge_softc *, int); +static int bge_reset(struct bge_softc *); +static void bge_link_upd(struct bge_softc *); + +/* + * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may + * leak information to untrusted users. It is also known to cause alignment + * traps on certain architectures. + */ +#ifdef BGE_REGISTER_DEBUG +static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); +static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); +static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); +#endif +static void bge_add_sysctls(struct bge_softc *); +static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); + +static device_method_t bge_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, bge_probe), + DEVMETHOD(device_attach, bge_attach), + DEVMETHOD(device_detach, bge_detach), + DEVMETHOD(device_shutdown, bge_shutdown), + DEVMETHOD(device_suspend, bge_suspend), + DEVMETHOD(device_resume, bge_resume), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, bge_miibus_readreg), + DEVMETHOD(miibus_writereg, bge_miibus_writereg), + DEVMETHOD(miibus_statchg, bge_miibus_statchg), + + { 0, 0 } +}; + +static driver_t bge_driver = { + "bge", + bge_methods, + sizeof(struct bge_softc) +}; + +static devclass_t bge_devclass; + +DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); +DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); + +static int bge_allow_asf = 1; + +TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); + +SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); +SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, + "Allow ASF mode if available"); + +#define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" +#define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" +#define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" +#define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" +#define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" + +static int +bge_has_eeprom(struct bge_softc *sc) +{ +#ifdef __sparc64__ + char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; + device_t dev; + uint32_t subvendor; + + dev = sc->bge_dev; + + /* + * The on-board BGEs found in sun4u machines aren't fitted with + * an EEPROM which means that we have to obtain the MAC address + * via OFW and that some tests will always fail. We distinguish + * such BGEs by the subvendor ID, which also has to be obtained + * from OFW instead of the PCI configuration space as the latter + * indicates Broadcom as the subvendor of the netboot interface. + * For early Blade 1500 and 2500 we even have to check the OFW + * device path as the subvendor ID always defaults to Broadcom + * there. + */ + if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, + &subvendor, sizeof(subvendor)) == sizeof(subvendor) && + subvendor == SUN_VENDORID) + return (0); + memset(buf, 0, sizeof(buf)); + if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { + if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && + strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) + return (0); + if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && + strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) + return (0); + } +#endif + return (1); +} + +static uint32_t +bge_readmem_ind(struct bge_softc *sc, int off) +{ + device_t dev; + uint32_t val; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); + val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); + return (val); +} + +static void +bge_writemem_ind(struct bge_softc *sc, int off, int val) +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); + pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); + pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); +} + +#ifdef notdef +static uint32_t +bge_readreg_ind(struct bge_softc *sc, int off) +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); + return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); +} +#endif + +static void +bge_writereg_ind(struct bge_softc *sc, int off, int val) +{ + device_t dev; + + dev = sc->bge_dev; + + pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); + pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); +} + +static void +bge_writemem_direct(struct bge_softc *sc, int off, int val) +{ + CSR_WRITE_4(sc, off, val); +} + +/* + * Map a single buffer address. + */ + +static void +bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct bge_dmamap_arg *ctx; + + if (error) + return; + + ctx = arg; + + if (nseg > ctx->bge_maxsegs) { + ctx->bge_maxsegs = 0; + return; + } + + ctx->bge_busaddr = segs->ds_addr; +} + +/* + * Read a byte of data stored in the EEPROM at address 'addr.' The + * BCM570x supports both the traditional bitbang interface and an + * auto access interface for reading the EEPROM. We use the auto + * access method. + */ +static uint8_t +bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) +{ + int i; + uint32_t byte = 0; + + /* + * Enable use of auto EEPROM access so we can avoid + * having to use the bitbang method. + */ + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); + + /* Reset the EEPROM, load the clock period. */ + CSR_WRITE_4(sc, BGE_EE_ADDR, + BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); + DELAY(20); + + /* Issue the read EEPROM command. */ + CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); + + /* Wait for completion */ + for(i = 0; i < BGE_TIMEOUT * 10; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) + break; + } + + if (i == BGE_TIMEOUT * 10) { + device_printf(sc->bge_dev, "EEPROM read timed out\n"); + return (1); + } + + /* Get result. */ + byte = CSR_READ_4(sc, BGE_EE_DATA); + + *dest = (byte >> ((addr % 4) * 8)) & 0xFF; + + return (0); +} + +/* + * Read a sequence of bytes from the EEPROM. + */ +static int +bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) +{ + int i, error = 0; + uint8_t byte = 0; + + for (i = 0; i < cnt; i++) { + error = bge_eeprom_getbyte(sc, off + i, &byte); + if (error) + break; + *(dest + i) = byte; + } + + return (error ? 1 : 0); +} + +static int +bge_miibus_readreg(device_t dev, int phy, int reg) +{ + struct bge_softc *sc; + uint32_t val, autopoll; + int i; + + sc = device_get_softc(dev); + + /* + * Broadcom's own driver always assumes the internal + * PHY is at GMII address 1. On some chips, the PHY responds + * to accesses at all addresses, which could cause us to + * bogusly attach the PHY 32 times at probe type. Always + * restricting the lookup to address 1 is simpler than + * trying to figure out which chips revisions should be + * special-cased. + */ + if (phy != 1) + return (0); + + /* Reading with autopolling on may trigger PCI errors */ + autopoll = CSR_READ_4(sc, BGE_MI_MODE); + if (autopoll & BGE_MIMODE_AUTOPOLL) { + BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); + DELAY(40); + } + + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | + BGE_MIPHY(phy) | BGE_MIREG(reg)); + + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + val = CSR_READ_4(sc, BGE_MI_COMM); + if (!(val & BGE_MICOMM_BUSY)) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, "PHY read timed out\n"); + val = 0; + goto done; + } + + val = CSR_READ_4(sc, BGE_MI_COMM); + +done: + if (autopoll & BGE_MIMODE_AUTOPOLL) { + BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); + DELAY(40); + } + + if (val & BGE_MICOMM_READFAIL) + return (0); + + return (val & 0xFFFF); +} + +static int +bge_miibus_writereg(device_t dev, int phy, int reg, int val) +{ + struct bge_softc *sc; + uint32_t autopoll; + int i; + + sc = device_get_softc(dev); + + /* Reading with autopolling on may trigger PCI errors */ + autopoll = CSR_READ_4(sc, BGE_MI_MODE); + if (autopoll & BGE_MIMODE_AUTOPOLL) { + BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); + DELAY(40); + } + + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | + BGE_MIPHY(phy) | BGE_MIREG(reg) | val); + + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, "PHY write timed out\n"); + return (0); + } + + if (autopoll & BGE_MIMODE_AUTOPOLL) { + BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); + DELAY(40); + } + + return (0); +} + +static void +bge_miibus_statchg(device_t dev) +{ + struct bge_softc *sc; + struct mii_data *mii; + sc = device_get_softc(dev); + mii = device_get_softc(sc->bge_miibus); + + BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); + else + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); + + if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) + BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); + else + BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); +} + +/* + * Intialize a standard receive ring descriptor. + */ +static int +bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) +{ + struct mbuf *m_new = NULL; + struct bge_rx_bd *r; + struct bge_dmamap_arg ctx; + int error; + + if (m == NULL) { + m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m_new == NULL) + return (ENOBUFS); + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + } else { + m_new = m; + m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; + m_new->m_data = m_new->m_ext.ext_buf; + } + + if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) + m_adj(m_new, ETHER_ALIGN); + sc->bge_cdata.bge_rx_std_chain[i] = m_new; + r = &sc->bge_ldata.bge_rx_std_ring[i]; + ctx.bge_maxsegs = 1; + ctx.sc = sc; + error = bus_dmamap_load(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), + m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); + if (error || ctx.bge_maxsegs == 0) { + if (m == NULL) { + sc->bge_cdata.bge_rx_std_chain[i] = NULL; + m_freem(m_new); + } + return (ENOMEM); + } + r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); + r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); + r->bge_flags = BGE_RXBDFLAG_END; + r->bge_len = m_new->m_len; + r->bge_idx = i; + + bus_dmamap_sync(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i], + BUS_DMASYNC_PREREAD); + + return (0); +} + +/* + * Initialize a jumbo receive ring descriptor. This allocates + * a jumbo buffer from the pool managed internally by the driver. + */ +static int +bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) +{ + bus_dma_segment_t segs[BGE_NSEG_JUMBO]; + struct bge_extrx_bd *r; + struct mbuf *m_new = NULL; + int nsegs; + int error; + + if (m == NULL) { + MGETHDR(m_new, M_DONTWAIT, MT_DATA); + if (m_new == NULL) + return (ENOBUFS); + + m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); + if (!(m_new->m_flags & M_EXT)) { + m_freem(m_new); + return (ENOBUFS); + } + m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; + } else { + m_new = m; + m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; + m_new->m_data = m_new->m_ext.ext_buf; + } + + if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) + m_adj(m_new, ETHER_ALIGN); + + error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i], + m_new, segs, &nsegs, BUS_DMA_NOWAIT); + if (error) { + if (m == NULL) + m_freem(m_new); + return (error); + } + sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; + + /* + * Fill in the extended RX buffer descriptor. + */ + r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; + r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; + r->bge_idx = i; + r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; + switch (nsegs) { + case 4: + r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); + r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); + r->bge_len3 = segs[3].ds_len; + case 3: + r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); + r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); + r->bge_len2 = segs[2].ds_len; + case 2: + r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); + r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); + r->bge_len1 = segs[1].ds_len; + case 1: + r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); + r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); + r->bge_len0 = segs[0].ds_len; + break; + default: + panic("%s: %d segments\n", __func__, nsegs); + } + + bus_dmamap_sync(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_jumbo_dmamap[i], + BUS_DMASYNC_PREREAD); + + return (0); +} + +/* + * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, + * that's 1MB or memory, which is a lot. For now, we fill only the first + * 256 ring entries and hope that our CPU is fast enough to keep up with + * the NIC. + */ +static int +bge_init_rx_ring_std(struct bge_softc *sc) +{ + int i; + + for (i = 0; i < BGE_SSLOTS; i++) { + if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) + return (ENOBUFS); + }; + + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + sc->bge_std = i - 1; + CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); + + return (0); +} + +static void +bge_free_rx_ring_std(struct bge_softc *sc) +{ + int i; + + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i]); + m_freem(sc->bge_cdata.bge_rx_std_chain[i]); + sc->bge_cdata.bge_rx_std_chain[i] = NULL; + } + bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], + sizeof(struct bge_rx_bd)); + } +} + +static int +bge_init_rx_ring_jumbo(struct bge_softc *sc) +{ + struct bge_rcb *rcb; + int i; + + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) + return (ENOBUFS); + }; + + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + sc->bge_jumbo = i - 1; + + rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; + rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, + BGE_RCB_FLAG_USE_EXT_RX_BD); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); + + CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); + + return (0); +} + +static void +bge_free_rx_ring_jumbo(struct bge_softc *sc) +{ + int i; + + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i]); + m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); + sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; + } + bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], + sizeof(struct bge_extrx_bd)); + } +} + +static void +bge_free_tx_ring(struct bge_softc *sc) +{ + int i; + + if (sc->bge_ldata.bge_tx_ring == NULL) + return; + + for (i = 0; i < BGE_TX_RING_CNT; i++) { + if (sc->bge_cdata.bge_tx_chain[i] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_tx_dmamap[i], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_tx_dmamap[i]); + m_freem(sc->bge_cdata.bge_tx_chain[i]); + sc->bge_cdata.bge_tx_chain[i] = NULL; + } + bzero((char *)&sc->bge_ldata.bge_tx_ring[i], + sizeof(struct bge_tx_bd)); + } +} + +static int +bge_init_tx_ring(struct bge_softc *sc) +{ + sc->bge_txcnt = 0; + sc->bge_tx_saved_considx = 0; + + /* Initialize transmit producer index for host-memory send ring. */ + sc->bge_tx_prodidx = 0; + CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); + + /* 5700 b2 errata */ + if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) + CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); + + /* NIC-memory send ring not used; initialize to zero. */ + CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); + /* 5700 b2 errata */ + if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) + CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); + + return (0); +} + +static void +bge_setpromisc(struct bge_softc *sc) +{ + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + /* Enable or disable promiscuous mode as needed. */ + if (ifp->if_flags & IFF_PROMISC) + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); + else + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); +} + +static void +bge_setmulti(struct bge_softc *sc) +{ + struct ifnet *ifp; + struct ifmultiaddr *ifma; + uint32_t hashes[4] = { 0, 0, 0, 0 }; + int h, i; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); + return; + } + + /* First, zot all the existing filters. */ + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); + + /* Now program new ones. */ + IF_ADDR_LOCK(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + h = ether_crc32_le(LLADDR((struct sockaddr_dl *) + ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; + hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); + } + IF_ADDR_UNLOCK(ifp); + + for (i = 0; i < 4; i++) + CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); +} + +static void +bge_setvlan(struct bge_softc *sc) +{ + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + /* Enable or disable VLAN tag stripping as needed. */ + if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); + else + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); +} + +static void +bge_sig_pre_reset(sc, type) + struct bge_softc *sc; + int type; +{ + /* + * Some chips don't like this so only do this if ASF is enabled + */ + if (sc->bge_asf_mode) + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); + + if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { + switch (type) { + case BGE_RESET_START: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ + break; + case BGE_RESET_STOP: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ + break; + } + } +} + +static void +bge_sig_post_reset(sc, type) + struct bge_softc *sc; + int type; +{ + if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { + switch (type) { + case BGE_RESET_START: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); + /* START DONE */ + break; + case BGE_RESET_STOP: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); + break; + } + } +} + +static void +bge_sig_legacy(sc, type) + struct bge_softc *sc; + int type; +{ + if (sc->bge_asf_mode) { + switch (type) { + case BGE_RESET_START: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ + break; + case BGE_RESET_STOP: + bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ + break; + } + } +} + +void bge_stop_fw(struct bge_softc *); +void +bge_stop_fw(sc) + struct bge_softc *sc; +{ + int i; + + if (sc->bge_asf_mode) { + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); + CSR_WRITE_4(sc, BGE_CPU_EVENT, + CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); + + for (i = 0; i < 100; i++ ) { + if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) + break; + DELAY(10); + } + } +} + +/* + * Do endian, PCI and DMA initialization. Also check the on-board ROM + * self-test results. + */ +static int +bge_chipinit(struct bge_softc *sc) +{ + uint32_t dma_rw_ctl; + int i; + + /* Set endianness before we access any non-PCI registers. */ + pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); + + /* + * Check the 'ROM failed' bit on the RX CPU to see if + * self-tests passed. Skip this check when there's no + * EEPROM fitted, since in that case it will always + * fail. + */ + if ((sc->bge_flags & BGE_FLAG_EEPROM) && + CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { + device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); + return (ENODEV); + } + + /* Clear the MAC control register */ + CSR_WRITE_4(sc, BGE_MAC_MODE, 0); + + /* + * Clear the MAC statistics block in the NIC's + * internal memory. + */ + for (i = BGE_STATS_BLOCK; + i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) + BGE_MEMWIN_WRITE(sc, i, 0); + + for (i = BGE_STATUS_BLOCK; + i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) + BGE_MEMWIN_WRITE(sc, i, 0); + + /* + * Set up the PCI DMA control register. + */ + dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | + BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); + if (sc->bge_flags & BGE_FLAG_PCIE) { + /* Read watermark not used, 128 bytes for write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); + } else if (sc->bge_flags & BGE_FLAG_PCIX) { + if (BGE_IS_5714_FAMILY(sc)) { + /* 256 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); + dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? + BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : + BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { + /* 1536 bytes for read, 384 bytes for write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); + } else { + /* 384 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | + 0x0F; + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || + sc->bge_asicrev == BGE_ASICREV_BCM5704) { + uint32_t tmp; + + /* Set ONE_DMA_AT_ONCE for hardware workaround. */ + tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; + if (tmp == 6 || tmp == 7) + dma_rw_ctl |= + BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; + + /* Set PCI-X DMA write workaround. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; + } + } else { + /* Conventional PCI bus: 256 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); + + if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && + sc->bge_asicrev != BGE_ASICREV_BCM5750) + dma_rw_ctl |= 0x0F; + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || + sc->bge_asicrev == BGE_ASICREV_BCM5701) + dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | + BGE_PCIDMARWCTL_ASRT_ALL_BE; + if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || + sc->bge_asicrev == BGE_ASICREV_BCM5704) + dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; + pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); + + /* + * Set up general mode register. + */ + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | + BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | + BGE_MODECTL_TX_NO_PHDR_CSUM); + + /* + * Tell the firmware the driver is running + */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + /* + * Disable memory write invalidate. Apparently it is not supported + * properly by these devices. + */ + PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); + + /* Set the timer prescaler (always 66Mhz) */ + CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); + + return (0); +} + +static int +bge_blockinit(struct bge_softc *sc) +{ + struct bge_rcb *rcb; + bus_size_t vrcb; + bge_hostaddr taddr; + uint32_t val; + int i; + + /* + * Initialize the memory window pointer register so that + * we can access the first 32K of internal NIC RAM. This will + * allow us to set up the TX send ring RCBs and the RX return + * ring RCBs, plus other things which live in NIC memory. + */ + CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); + + /* Note: the BCM5704 has a smaller mbuf space than other chips. */ + + if (!(BGE_IS_5705_PLUS(sc))) { + /* Configure mbuf memory pool */ + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); + if (sc->bge_asicrev == BGE_ASICREV_BCM5704) + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); + else + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); + + /* Configure DMA resource pool */ + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, + BGE_DMA_DESCRIPTORS); + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); + } + + /* Configure mbuf pool watermarks */ + if (!(BGE_IS_5705_PLUS(sc))) { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); + } else { + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); + } + CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); + + /* Configure DMA resource watermarks */ + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); + CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); + + /* Enable buffer manager */ + if (!(BGE_IS_5705_PLUS(sc))) { + CSR_WRITE_4(sc, BGE_BMAN_MODE, + BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); + + /* Poll for buffer manager start indication */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, + "buffer manager failed to start\n"); + return (ENXIO); + } + } + + /* Enable flow-through queues */ + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); + + /* Wait until queue initialization is complete */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, "flow-through queue init failed\n"); + return (ENXIO); + } + + /* Initialize the standard RX ring control block */ + rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; + rcb->bge_hostaddr.bge_addr_lo = + BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); + rcb->bge_hostaddr.bge_addr_hi = + BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); + if (BGE_IS_5705_PLUS(sc)) + rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); + else + rcb->bge_maxlen_flags = + BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); + rcb->bge_nicaddr = BGE_STD_RX_RINGS; + CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); + + CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); + CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); + + /* + * Initialize the jumbo RX ring control block + * We set the 'ring disabled' bit in the flags + * field until we're actually ready to start + * using this ring (i.e. once we set the MTU + * high enough to require it). + */ + if (BGE_IS_JUMBO_CAPABLE(sc)) { + rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; + + rcb->bge_hostaddr.bge_addr_lo = + BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); + rcb->bge_hostaddr.bge_addr_hi = + BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, + BUS_DMASYNC_PREREAD); + rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, + BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); + rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, + rcb->bge_hostaddr.bge_addr_hi); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, + rcb->bge_hostaddr.bge_addr_lo); + + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, + rcb->bge_maxlen_flags); + CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); + + /* Set up dummy disabled mini ring RCB */ + rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; + rcb->bge_maxlen_flags = + BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); + CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, + rcb->bge_maxlen_flags); + } + + /* + * Set the BD ring replentish thresholds. The recommended + * values are 1/8th the number of descriptors allocated to + * each ring. + * XXX The 5754 requires a lower threshold, so it might be a + * requirement of all 575x family chips. The Linux driver sets + * the lower threshold for all 5705 family chips as well, but there + * are reports that it might not need to be so strict. + */ + if (BGE_IS_5705_PLUS(sc)) + val = 8; + else + val = BGE_STD_RX_RING_CNT / 8; + CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); + CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); + + /* + * Disable all unused send rings by setting the 'ring disabled' + * bit in the flags field of all the TX send ring control blocks. + * These are located in NIC memory. + */ + vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; + for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); + RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); + vrcb += sizeof(struct bge_rcb); + } + + /* Configure TX RCB 0 (we use only the first ring) */ + vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; + BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); + RCB_WRITE_4(sc, vrcb, bge_nicaddr, + BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); + if (!(BGE_IS_5705_PLUS(sc))) + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); + + /* Disable all unused RX return rings */ + vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; + for (i = 0; i < BGE_RX_RINGS_MAX; i++) { + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, + BGE_RCB_FLAG_RING_DISABLED)); + RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); + CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + + (i * (sizeof(uint64_t))), 0); + vrcb += sizeof(struct bge_rcb); + } + + /* Initialize RX ring indexes */ + CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); + CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); + CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); + + /* + * Set up RX return ring 0 + * Note that the NIC address for RX return rings is 0x00000000. + * The return rings live entirely within the host, so the + * nicaddr field in the RCB isn't used. + */ + vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; + BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); + RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); + RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); + RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, + BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); + + /* Set random backoff seed for TX */ + CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, + IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + + IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + + IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + + BGE_TX_BACKOFF_SEED_MASK); + + /* Set inter-packet gap */ + CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); + + /* + * Specify which ring to use for packets that don't match + * any RX rules. + */ + CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); + + /* + * Configure number of RX lists. One interrupt distribution + * list, sixteen active lists, one bad frames class. + */ + CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); + + /* Inialize RX list placement stats mask. */ + CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); + CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); + + /* Disable host coalescing until we get it set up */ + CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); + + /* Poll to make sure it's shut down. */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) + break; + } + + if (i == BGE_TIMEOUT) { + device_printf(sc->bge_dev, + "host coalescing engine failed to idle\n"); + return (ENXIO); + } + + /* Set up host coalescing defaults */ + CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); + CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); + CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); + CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); + if (!(BGE_IS_5705_PLUS(sc))) { + CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); + CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); + } + CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); + CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); + + /* Set up address of statistics block */ + if (!(BGE_IS_5705_PLUS(sc))) { + CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, + BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); + CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, + BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); + CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); + CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); + } + + /* Set up address of status block */ + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, + BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); + CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, + BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); + sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; + sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; + + /* Turn on host coalescing state machine */ + CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); + + /* Turn on RX BD completion state machine and enable attentions */ + CSR_WRITE_4(sc, BGE_RBDC_MODE, + BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); + + /* Turn on RX list placement state machine */ + CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); + + /* Turn on RX list selector state machine. */ + if (!(BGE_IS_5705_PLUS(sc))) + CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); + + /* Turn on DMA, clear stats */ + CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | + BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | + BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | + BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | + ((sc->bge_flags & BGE_FLAG_TBI) ? + BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); + + /* Set misc. local control, enable interrupts on attentions */ + CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); + +#ifdef notdef + /* Assert GPIO pins for PHY reset */ + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | + BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | + BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); +#endif + + /* Turn on DMA completion state machine */ + if (!(BGE_IS_5705_PLUS(sc))) + CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); + + val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; + + /* Enable host coalescing bug fix. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || + sc->bge_asicrev == BGE_ASICREV_BCM5787) + val |= 1 << 29; + + /* Turn on write DMA state machine */ + CSR_WRITE_4(sc, BGE_WDMA_MODE, val); + + /* Turn on read DMA state machine */ + CSR_WRITE_4(sc, BGE_RDMA_MODE, + BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); + + /* Turn on RX data completion state machine */ + CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); + + /* Turn on RX BD initiator state machine */ + CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); + + /* Turn on RX data and RX BD initiator state machine */ + CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); + + /* Turn on Mbuf cluster free state machine */ + if (!(BGE_IS_5705_PLUS(sc))) + CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); + + /* Turn on send BD completion state machine */ + CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); + + /* Turn on send data completion state machine */ + CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); + + /* Turn on send data initiator state machine */ + CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); + + /* Turn on send BD initiator state machine */ + CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); + + /* Turn on send BD selector state machine */ + CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); + + CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); + CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, + BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); + + /* ack/clear link change events */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | + BGE_MACSTAT_LINK_CHANGED); + CSR_WRITE_4(sc, BGE_MI_STS, 0); + + /* Enable PHY auto polling (for MII/GMII only) */ + if (sc->bge_flags & BGE_FLAG_TBI) { + CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); + } else { + BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) + CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, + BGE_EVTENB_MI_INTERRUPT); + } + + /* + * Clear any pending link state attention. + * Otherwise some link state change events may be lost until attention + * is cleared by bge_intr() -> bge_link_upd() sequence. + * It's not necessary on newer BCM chips - perhaps enabling link + * state change attentions implies clearing pending attention. + */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | + BGE_MACSTAT_LINK_CHANGED); + + /* Enable link state change attentions. */ + BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); + + return (0); +} + +const struct bge_revision * +bge_lookup_rev(uint32_t chipid) +{ + const struct bge_revision *br; + + for (br = bge_revisions; br->br_name != NULL; br++) { + if (br->br_chipid == chipid) + return (br); + } + + for (br = bge_majorrevs; br->br_name != NULL; br++) { + if (br->br_chipid == BGE_ASICREV(chipid)) + return (br); + } + + return (NULL); +} + +const struct bge_vendor * +bge_lookup_vendor(uint16_t vid) +{ + const struct bge_vendor *v; + + for (v = bge_vendors; v->v_name != NULL; v++) + if (v->v_id == vid) + return (v); + + panic("%s: unknown vendor %d", __func__, vid); + return (NULL); +} + +/* + * Probe for a Broadcom chip. Check the PCI vendor and device IDs + * against our list and return its name if we find a match. + * + * Note that since the Broadcom controller contains VPD support, we + * try to get the device name string from the controller itself instead + * of the compiled-in string. It guarantees we'll always announce the + * right product name. We fall back to the compiled-in string when + * VPD is unavailable or corrupt. + */ +static int +bge_probe(device_t dev) +{ + struct bge_type *t = bge_devs; + struct bge_softc *sc = device_get_softc(dev); + uint16_t vid, did; + + sc->bge_dev = dev; + vid = pci_get_vendor(dev); + did = pci_get_device(dev); + while(t->bge_vid != 0) { + if ((vid == t->bge_vid) && (did == t->bge_did)) { + char model[64], buf[96]; + const struct bge_revision *br; + const struct bge_vendor *v; + uint32_t id; + + id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & + BGE_PCIMISCCTL_ASICREV; + br = bge_lookup_rev(id); + v = bge_lookup_vendor(vid); + { +#if __FreeBSD_version > 700024 + const char *pname; + + if (pci_get_vpd_ident(dev, &pname) == 0) + snprintf(model, 64, "%s", pname); + else +#endif + snprintf(model, 64, "%s %s", + v->v_name, + br != NULL ? br->br_name : + "NetXtreme Ethernet Controller"); + } + snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, + br != NULL ? "" : "unknown ", id >> 16); + device_set_desc_copy(dev, buf); + if (pci_get_subvendor(dev) == DELL_VENDORID) + sc->bge_flags |= BGE_FLAG_NO_3LED; + if (did == BCOM_DEVICEID_BCM5755M) + sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; + return (0); + } + t++; + } + + return (ENXIO); +} + +static void +bge_dma_free(struct bge_softc *sc) +{ + int i; + + /* Destroy DMA maps for RX buffers. */ + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_std_dmamap[i]) + bus_dmamap_destroy(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_std_dmamap[i]); + } + + /* Destroy DMA maps for jumbo RX buffers. */ + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) + bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[i]); + } + + /* Destroy DMA maps for TX buffers. */ + for (i = 0; i < BGE_TX_RING_CNT; i++) { + if (sc->bge_cdata.bge_tx_dmamap[i]) + bus_dmamap_destroy(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_tx_dmamap[i]); + } + + if (sc->bge_cdata.bge_mtag) + bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); + + + /* Destroy standard RX ring. */ + if (sc->bge_cdata.bge_rx_std_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map); + if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) + bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_ldata.bge_rx_std_ring, + sc->bge_cdata.bge_rx_std_ring_map); + + if (sc->bge_cdata.bge_rx_std_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); + + /* Destroy jumbo RX ring. */ + if (sc->bge_cdata.bge_rx_jumbo_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map); + + if (sc->bge_cdata.bge_rx_jumbo_ring_map && + sc->bge_ldata.bge_rx_jumbo_ring) + bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_ldata.bge_rx_jumbo_ring, + sc->bge_cdata.bge_rx_jumbo_ring_map); + + if (sc->bge_cdata.bge_rx_jumbo_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); + + /* Destroy RX return ring. */ + if (sc->bge_cdata.bge_rx_return_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_cdata.bge_rx_return_ring_map); + + if (sc->bge_cdata.bge_rx_return_ring_map && + sc->bge_ldata.bge_rx_return_ring) + bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_ldata.bge_rx_return_ring, + sc->bge_cdata.bge_rx_return_ring_map); + + if (sc->bge_cdata.bge_rx_return_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); + + /* Destroy TX ring. */ + if (sc->bge_cdata.bge_tx_ring_map) + bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_cdata.bge_tx_ring_map); + + if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) + bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_ldata.bge_tx_ring, + sc->bge_cdata.bge_tx_ring_map); + + if (sc->bge_cdata.bge_tx_ring_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); + + /* Destroy status block. */ + if (sc->bge_cdata.bge_status_map) + bus_dmamap_unload(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map); + + if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) + bus_dmamem_free(sc->bge_cdata.bge_status_tag, + sc->bge_ldata.bge_status_block, + sc->bge_cdata.bge_status_map); + + if (sc->bge_cdata.bge_status_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); + + /* Destroy statistics block. */ + if (sc->bge_cdata.bge_stats_map) + bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, + sc->bge_cdata.bge_stats_map); + + if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) + bus_dmamem_free(sc->bge_cdata.bge_stats_tag, + sc->bge_ldata.bge_stats, + sc->bge_cdata.bge_stats_map); + + if (sc->bge_cdata.bge_stats_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); + + /* Destroy the parent tag. */ + if (sc->bge_cdata.bge_parent_tag) + bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); +} + +static int +bge_dma_alloc(device_t dev) +{ + struct bge_dmamap_arg ctx; + struct bge_softc *sc; + int i, error; + + sc = device_get_softc(dev); + + /* + * Allocate the parent bus DMA tag appropriate for PCI. + */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */ + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->bge_cdata.bge_parent_tag); + + if (error != 0) { + device_printf(sc->bge_dev, + "could not allocate parent dma tag\n"); + return (ENOMEM); + } + + /* + * Create tag for RX mbufs. + */ + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, + 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, + BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate dma tag\n"); + return (ENOMEM); + } + + /* Create DMA maps for RX buffers. */ + for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { + error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, + &sc->bge_cdata.bge_rx_std_dmamap[i]); + if (error) { + device_printf(sc->bge_dev, + "can't create DMA map for RX\n"); + return (ENOMEM); + } + } + + /* Create DMA maps for TX buffers. */ + for (i = 0; i < BGE_TX_RING_CNT; i++) { + error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, + &sc->bge_cdata.bge_tx_dmamap[i]); + if (error) { + device_printf(sc->bge_dev, + "can't create DMA map for RX\n"); + return (ENOMEM); + } + } + + /* Create tag for standard RX ring. */ + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, + NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate dma tag\n"); + return (ENOMEM); + } + + /* Allocate DMA'able memory for standard RX ring. */ + error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, + (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, + &sc->bge_cdata.bge_rx_std_ring_map); + if (error) + return (ENOMEM); + + bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); + + /* Load the address of the standard RX ring. */ + ctx.bge_maxsegs = 1; + ctx.sc = sc; + + error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, + BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); + + if (error) + return (ENOMEM); + + sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; + + /* Create tags for jumbo mbufs. */ + if (BGE_IS_JUMBO_CAPABLE(sc)) { + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, + 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); + if (error) { + device_printf(sc->bge_dev, + "could not allocate jumbo dma tag\n"); + return (ENOMEM); + } + + /* Create tag for jumbo RX ring. */ + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, + NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); + + if (error) { + device_printf(sc->bge_dev, + "could not allocate jumbo ring dma tag\n"); + return (ENOMEM); + } + + /* Allocate DMA'able memory for jumbo RX ring. */ + error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, + (void **)&sc->bge_ldata.bge_rx_jumbo_ring, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, + &sc->bge_cdata.bge_rx_jumbo_ring_map); + if (error) + return (ENOMEM); + + /* Load the address of the jumbo RX ring. */ + ctx.bge_maxsegs = 1; + ctx.sc = sc; + + error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, + sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, + bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); + + if (error) + return (ENOMEM); + + sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; + + /* Create DMA maps for jumbo RX buffers. */ + for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { + error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, + 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); + if (error) { + device_printf(sc->bge_dev, + "can't create DMA map for jumbo RX\n"); + return (ENOMEM); + } + } + + } + + /* Create tag for RX return ring. */ + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, + NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate dma tag\n"); + return (ENOMEM); + } + + /* Allocate DMA'able memory for RX return ring. */ + error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, + (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, + &sc->bge_cdata.bge_rx_return_ring_map); + if (error) + return (ENOMEM); + + bzero((char *)sc->bge_ldata.bge_rx_return_ring, + BGE_RX_RTN_RING_SZ(sc)); + + /* Load the address of the RX return ring. */ + ctx.bge_maxsegs = 1; + ctx.sc = sc; + + error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_cdata.bge_rx_return_ring_map, + sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), + bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); + + if (error) + return (ENOMEM); + + sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; + + /* Create tag for TX ring. */ + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, + &sc->bge_cdata.bge_tx_ring_tag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate dma tag\n"); + return (ENOMEM); + } + + /* Allocate DMA'able memory for TX ring. */ + error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, + (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, + &sc->bge_cdata.bge_tx_ring_map); + if (error) + return (ENOMEM); + + bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); + + /* Load the address of the TX ring. */ + ctx.bge_maxsegs = 1; + ctx.sc = sc; + + error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, + BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); + + if (error) + return (ENOMEM); + + sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; + + /* Create tag for status block. */ + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, + NULL, NULL, &sc->bge_cdata.bge_status_tag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate dma tag\n"); + return (ENOMEM); + } + + /* Allocate DMA'able memory for status block. */ + error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, + (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, + &sc->bge_cdata.bge_status_map); + if (error) + return (ENOMEM); + + bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); + + /* Load the address of the status block. */ + ctx.sc = sc; + ctx.bge_maxsegs = 1; + + error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, + BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); + + if (error) + return (ENOMEM); + + sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; + + /* Create tag for statistics block. */ + error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, + PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, + NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, + &sc->bge_cdata.bge_stats_tag); + + if (error) { + device_printf(sc->bge_dev, "could not allocate dma tag\n"); + return (ENOMEM); + } + + /* Allocate DMA'able memory for statistics block. */ + error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, + (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, + &sc->bge_cdata.bge_stats_map); + if (error) + return (ENOMEM); + + bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); + + /* Load the address of the statstics block. */ + ctx.sc = sc; + ctx.bge_maxsegs = 1; + + error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, + sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, + BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); + + if (error) + return (ENOMEM); + + sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; + + return (0); +} + +#if __FreeBSD_version > 602105 +/* + * Return true if this device has more than one port. + */ +static int +bge_has_multiple_ports(struct bge_softc *sc) +{ + device_t dev = sc->bge_dev; + u_int b, d, f, fscan, s; + + d = pci_get_domain(dev); + b = pci_get_bus(dev); + s = pci_get_slot(dev); + f = pci_get_function(dev); + for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) + if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) + return (1); + return (0); +} + +/* + * Return true if MSI can be used with this device. + */ +static int +bge_can_use_msi(struct bge_softc *sc) +{ + int can_use_msi = 0; + + switch (sc->bge_asicrev) { + case BGE_ASICREV_BCM5714: + /* + * Apparently, MSI doesn't work when this chip is configured + * in single-port mode. + */ + if (bge_has_multiple_ports(sc)) + can_use_msi = 1; + break; + case BGE_ASICREV_BCM5750: + if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && + sc->bge_chiprev != BGE_CHIPREV_5750_BX) + can_use_msi = 1; + break; + case BGE_ASICREV_BCM5752: + case BGE_ASICREV_BCM5780: + can_use_msi = 1; + break; + } + return (can_use_msi); +} +#endif + +static int +bge_attach(device_t dev) +{ + struct ifnet *ifp; + struct bge_softc *sc; + uint32_t hwcfg = 0; + uint32_t mac_tmp = 0; + u_char eaddr[ETHER_ADDR_LEN]; + int error, reg, rid, trys; + + sc = device_get_softc(dev); + sc->bge_dev = dev; + + /* + * Map control/status registers. + */ + pci_enable_busmaster(dev); + + rid = BGE_PCI_BAR0; + sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE | PCI_RF_DENSE); + + if (sc->bge_res == NULL) { + device_printf (sc->bge_dev, "couldn't map memory\n"); + error = ENXIO; + goto fail; + } + + sc->bge_btag = rman_get_bustag(sc->bge_res); + sc->bge_bhandle = rman_get_bushandle(sc->bge_res); + + /* Save ASIC rev. */ + + sc->bge_chipid = + pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & + BGE_PCIMISCCTL_ASICREV; + sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); + sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); + + if (bge_has_eeprom(sc)) + sc->bge_flags |= BGE_FLAG_EEPROM; + + /* Save chipset family. */ + switch (sc->bge_asicrev) { + case BGE_ASICREV_BCM5700: + case BGE_ASICREV_BCM5701: + case BGE_ASICREV_BCM5703: + case BGE_ASICREV_BCM5704: + sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; + break; + case BGE_ASICREV_BCM5714_A0: + case BGE_ASICREV_BCM5780: + case BGE_ASICREV_BCM5714: + sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; + /* FALLTHRU */ + case BGE_ASICREV_BCM5750: + case BGE_ASICREV_BCM5752: + case BGE_ASICREV_BCM5755: + case BGE_ASICREV_BCM5787: + sc->bge_flags |= BGE_FLAG_575X_PLUS; + /* FALLTHRU */ + case BGE_ASICREV_BCM5705: + sc->bge_flags |= BGE_FLAG_5705_PLUS; + break; + } + + /* Set various bug flags. */ + if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || + sc->bge_chipid == BGE_CHIPID_BCM5701_B0) + sc->bge_flags |= BGE_FLAG_CRC_BUG; + if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || + sc->bge_chiprev == BGE_CHIPREV_5704_AX) + sc->bge_flags |= BGE_FLAG_ADC_BUG; + if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) + sc->bge_flags |= BGE_FLAG_5704_A0_BUG; + if (BGE_IS_5705_PLUS(sc) && + !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { + if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || + sc->bge_asicrev == BGE_ASICREV_BCM5787) + sc->bge_flags |= BGE_FLAG_JITTER_BUG; + else + sc->bge_flags |= BGE_FLAG_BER_BUG; + } + + /* + * Check if this is a PCI-X or PCI Express device. + */ +#if __FreeBSD_version > 602101 + if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + /* + * Found a PCI Express capabilities register, this + * must be a PCI Express device. + */ + if (reg != 0) + sc->bge_flags |= BGE_FLAG_PCIE; + } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { + if (reg != 0) + sc->bge_flags |= BGE_FLAG_PCIX; + } + +#else + if (BGE_IS_5705_PLUS(sc)) { + reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); + if ((reg & 0xFF) == BGE_PCIE_CAPID) + sc->bge_flags |= BGE_FLAG_PCIE; + } else { + /* + * Check if the device is in PCI-X Mode. + * (This bit is not valid on PCI Express controllers.) + */ + if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & + BGE_PCISTATE_PCI_BUSMODE) == 0) + sc->bge_flags |= BGE_FLAG_PCIX; + } +#endif + +#if __FreeBSD_version > 602105 + { + int msicount; + + /* + * Allocate the interrupt, using MSI if possible. These devices + * support 8 MSI messages, but only the first one is used in + * normal operation. + */ + if (bge_can_use_msi(sc)) { + msicount = pci_msi_count(dev); + if (msicount > 1) + msicount = 1; + } else + msicount = 0; + if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { + rid = 1; + sc->bge_flags |= BGE_FLAG_MSI; + } else + rid = 0; + } +#else + rid = 0; +#endif + + sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + + if (sc->bge_irq == NULL) { + device_printf(sc->bge_dev, "couldn't map interrupt\n"); + error = ENXIO; + goto fail; + } + + BGE_LOCK_INIT(sc, device_get_nameunit(dev)); + + /* Try to reset the chip. */ + if (bge_reset(sc)) { + device_printf(sc->bge_dev, "chip reset failed\n"); + error = ENXIO; + goto fail; + } + + sc->bge_asf_mode = 0; + if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) + == BGE_MAGIC_NUMBER)) { + if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) + & BGE_HWCFG_ASF) { + sc->bge_asf_mode |= ASF_ENABLE; + sc->bge_asf_mode |= ASF_STACKUP; + if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { + sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; + } + } + } + + /* Try to reset the chip again the nice way. */ + bge_stop_fw(sc); + bge_sig_pre_reset(sc, BGE_RESET_STOP); + if (bge_reset(sc)) { + device_printf(sc->bge_dev, "chip reset failed\n"); + error = ENXIO; + goto fail; + } + + bge_sig_legacy(sc, BGE_RESET_STOP); + bge_sig_post_reset(sc, BGE_RESET_STOP); + + if (bge_chipinit(sc)) { + device_printf(sc->bge_dev, "chip initialization failed\n"); + error = ENXIO; + goto fail; + } + +#ifdef __sparc64__ + if ((sc->bge_flags & BGE_FLAG_EEPROM) == 0) + OF_getetheraddr(dev, eaddr); + else +#endif + { + mac_tmp = bge_readmem_ind(sc, 0x0C14); + if ((mac_tmp >> 16) == 0x484B) { + eaddr[0] = (u_char)(mac_tmp >> 8); + eaddr[1] = (u_char)mac_tmp; + mac_tmp = bge_readmem_ind(sc, 0x0C18); + eaddr[2] = (u_char)(mac_tmp >> 24); + eaddr[3] = (u_char)(mac_tmp >> 16); + eaddr[4] = (u_char)(mac_tmp >> 8); + eaddr[5] = (u_char)mac_tmp; + } else if (bge_read_eeprom(sc, eaddr, + BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { + device_printf(sc->bge_dev, + "failed to read station address\n"); + error = ENXIO; + goto fail; + } + } + + /* 5705 limits RX return ring to 512 entries. */ + if (BGE_IS_5705_PLUS(sc)) + sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; + else + sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; + + if (bge_dma_alloc(dev)) { + device_printf(sc->bge_dev, + "failed to allocate DMA resources\n"); + error = ENXIO; + goto fail; + } + + /* Set default tuneable values. */ + sc->bge_stat_ticks = BGE_TICKS_PER_SEC; + sc->bge_rx_coal_ticks = 150; + sc->bge_tx_coal_ticks = 150; + sc->bge_rx_max_coal_bds = 10; + sc->bge_tx_max_coal_bds = 10; + + /* Set up ifnet structure */ + ifp = sc->bge_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(sc->bge_dev, "failed to if_alloc()\n"); + error = ENXIO; + goto fail; + } + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = bge_ioctl; + ifp->if_start = bge_start; + ifp->if_init = bge_init; + ifp->if_mtu = ETHERMTU; + ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; + IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); + IFQ_SET_READY(&ifp->if_snd); + ifp->if_hwassist = BGE_CSUM_FEATURES; + ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | + IFCAP_VLAN_MTU; +#ifdef IFCAP_VLAN_HWCSUM + ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; +#endif + ifp->if_capenable = ifp->if_capabilities; +#ifdef DEVICE_POLLING + ifp->if_capabilities |= IFCAP_POLLING; +#endif + + /* + * 5700 B0 chips do not support checksumming correctly due + * to hardware bugs. + */ + if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { + ifp->if_capabilities &= ~IFCAP_HWCSUM; + ifp->if_capenable &= IFCAP_HWCSUM; + ifp->if_hwassist = 0; + } + + /* + * Figure out what sort of media we have by checking the + * hardware config word in the first 32k of NIC internal memory, + * or fall back to examining the EEPROM if necessary. + * Note: on some BCM5700 cards, this value appears to be unset. + * If that's the case, we have to rely on identifying the NIC + * by its PCI subsystem ID, as we do below for the SysKonnect + * SK-9D41. + */ + if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) + hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); + else if (sc->bge_flags & BGE_FLAG_EEPROM) { + if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, + sizeof(hwcfg))) { + device_printf(sc->bge_dev, "failed to read EEPROM\n"); + error = ENXIO; + goto fail; + } + hwcfg = ntohl(hwcfg); + } + + if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) + sc->bge_flags |= BGE_FLAG_TBI; + + /* The SysKonnect SK-9D41 is a 1000baseSX card. */ + if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) + sc->bge_flags |= BGE_FLAG_TBI; + + if (sc->bge_flags & BGE_FLAG_TBI) { + ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, + bge_ifmedia_sts); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, + 0, NULL); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); + ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); + sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; + } else { + /* + * Do transceiver setup and tell the firmware the + * driver is down so we can try to get access the + * probe if ASF is running. Retry a couple of times + * if we get a conflict with the ASF firmware accessing + * the PHY. + */ + BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); +again: + bge_asf_driver_up(sc); + + trys = 0; + if (mii_phy_probe(dev, &sc->bge_miibus, + bge_ifmedia_upd, bge_ifmedia_sts)) { + if (trys++ < 4) { + device_printf(sc->bge_dev, "Try again\n"); + bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, + BMCR_RESET); + goto again; + } + + device_printf(sc->bge_dev, "MII without any PHY!\n"); + error = ENXIO; + goto fail; + } + + /* + * Now tell the firmware we are going up after probing the PHY + */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + } + + /* + * When using the BCM5701 in PCI-X mode, data corruption has + * been observed in the first few bytes of some received packets. + * Aligning the packet buffer in memory eliminates the corruption. + * Unfortunately, this misaligns the packet payloads. On platforms + * which do not support unaligned accesses, we will realign the + * payloads by copying the received packets. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && + sc->bge_flags & BGE_FLAG_PCIX) + sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; + + /* + * Call MI attach routine. + */ + ether_ifattach(ifp, eaddr); + callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); + + /* + * Hookup IRQ last. + */ +#if __FreeBSD_version > 700030 + error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, bge_intr, sc, &sc->bge_intrhand); +#else + error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, + bge_intr, sc, &sc->bge_intrhand); +#endif + + if (error) { + bge_detach(dev); + device_printf(sc->bge_dev, "couldn't set up irq\n"); + } + + bge_add_sysctls(sc); + + return (0); + +fail: + bge_release_resources(sc); + + return (error); +} + +static int +bge_detach(device_t dev) +{ + struct bge_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + ifp = sc->bge_ifp; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) + ether_poll_deregister(ifp); +#endif + + BGE_LOCK(sc); + bge_stop(sc); + bge_reset(sc); + BGE_UNLOCK(sc); + + callout_drain(&sc->bge_stat_ch); + + ether_ifdetach(ifp); + + if (sc->bge_flags & BGE_FLAG_TBI) { + ifmedia_removeall(&sc->bge_ifmedia); + } else { + bus_generic_detach(dev); + device_delete_child(dev, sc->bge_miibus); + } + + bge_release_resources(sc); + + return (0); +} + +static void +bge_release_resources(struct bge_softc *sc) +{ + device_t dev; + + dev = sc->bge_dev; + + if (sc->bge_intrhand != NULL) + bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); + + if (sc->bge_irq != NULL) + bus_release_resource(dev, SYS_RES_IRQ, + sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); + +#if __FreeBSD_version > 602105 + if (sc->bge_flags & BGE_FLAG_MSI) + pci_release_msi(dev); +#endif + + if (sc->bge_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, + BGE_PCI_BAR0, sc->bge_res); + + if (sc->bge_ifp != NULL) + if_free(sc->bge_ifp); + + bge_dma_free(sc); + + if (mtx_initialized(&sc->bge_mtx)) /* XXX */ + BGE_LOCK_DESTROY(sc); +} + +static int +bge_reset(struct bge_softc *sc) +{ + device_t dev; + uint32_t cachesize, command, pcistate, reset; + void (*write_op)(struct bge_softc *, int, int); + int i, val = 0; + + dev = sc->bge_dev; + + if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) { + if (sc->bge_flags & BGE_FLAG_PCIE) + write_op = bge_writemem_direct; + else + write_op = bge_writemem_ind; + } else + write_op = bge_writereg_ind; + + /* Save some important PCI state. */ + cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); + command = pci_read_config(dev, BGE_PCI_CMD, 4); + pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); + + pci_write_config(dev, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | + BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); + + /* Disable fastboot on controllers that support it. */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || + sc->bge_asicrev == BGE_ASICREV_BCM5755 || + sc->bge_asicrev == BGE_ASICREV_BCM5787) { + if (bootverbose) + device_printf(sc->bge_dev, "Disabling fastboot\n"); + CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); + } + + /* + * Write the magic number to SRAM at offset 0xB50. + * When firmware finishes its initialization it will + * write ~BGE_MAGIC_NUMBER to the same location. + */ + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); + + reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; + + /* XXX: Broadcom Linux driver. */ + if (sc->bge_flags & BGE_FLAG_PCIE) { + if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ + CSR_WRITE_4(sc, 0x7E2C, 0x20); + if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { + /* Prevent PCIE link training during global reset */ + CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); + reset |= 1 << 29; + } + } + + /* + * Set GPHY Power Down Override to leave GPHY + * powered up in D0 uninitialized. + */ + if (BGE_IS_5705_PLUS(sc)) + reset |= 0x04000000; + + /* Issue global reset */ + write_op(sc, BGE_MISC_CFG, reset); + + DELAY(1000); + + /* XXX: Broadcom Linux driver. */ + if (sc->bge_flags & BGE_FLAG_PCIE) { + if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { + uint32_t v; + + DELAY(500000); /* wait for link training to complete */ + v = pci_read_config(dev, 0xC4, 4); + pci_write_config(dev, 0xC4, v | (1 << 15), 4); + } + /* + * Set PCIE max payload size to 128 bytes and clear error + * status. + */ + pci_write_config(dev, 0xD8, 0xF5000, 4); + } + + /* Reset some of the PCI state that got zapped by reset. */ + pci_write_config(dev, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | + BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); + pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); + pci_write_config(dev, BGE_PCI_CMD, command, 4); + write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); + + /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ + if (BGE_IS_5714_FAMILY(sc)) { + uint32_t val; + + /* This chip disables MSI on reset. */ + if (sc->bge_flags & BGE_FLAG_MSI) { + val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); + pci_write_config(dev, BGE_PCI_MSI_CTL, + val | PCIM_MSICTRL_MSI_ENABLE, 2); + val = CSR_READ_4(sc, BGE_MSI_MODE); + CSR_WRITE_4(sc, BGE_MSI_MODE, + val | BGE_MSIMODE_ENABLE); + } + val = CSR_READ_4(sc, BGE_MARB_MODE); + CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); + } else + CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); + + /* + * Poll until we see the 1's complement of the magic number. + * This indicates that the firmware initialization is complete. + * We expect this to fail if no EEPROM is fitted though. + */ + for (i = 0; i < BGE_TIMEOUT; i++) { + DELAY(10); + val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); + if (val == ~BGE_MAGIC_NUMBER) + break; + } + + if ((sc->bge_flags & BGE_FLAG_EEPROM) && i == BGE_TIMEOUT) + device_printf(sc->bge_dev, "firmware handshake timed out, " + "found 0x%08x\n", val); + + /* + * XXX Wait for the value of the PCISTATE register to + * return to its original pre-reset state. This is a + * fairly good indicator of reset completion. If we don't + * wait for the reset to fully complete, trying to read + * from the device's non-PCI registers may yield garbage + * results. + */ + for (i = 0; i < BGE_TIMEOUT; i++) { + if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) + break; + DELAY(10); + } + + if (sc->bge_flags & BGE_FLAG_PCIE) { + reset = bge_readmem_ind(sc, 0x7C00); + bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); + } + + /* Fix up byte swapping. */ + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | + BGE_MODECTL_BYTESWAP_DATA); + + /* Tell the ASF firmware we are up */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + CSR_WRITE_4(sc, BGE_MAC_MODE, 0); + + /* + * The 5704 in TBI mode apparently needs some special + * adjustment to insure the SERDES drive level is set + * to 1.2V. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && + sc->bge_flags & BGE_FLAG_TBI) { + uint32_t serdescfg; + + serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); + serdescfg = (serdescfg & ~0xFFF) | 0x880; + CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); + } + + /* XXX: Broadcom Linux driver. */ + if (sc->bge_flags & BGE_FLAG_PCIE && + sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { + uint32_t v; + + v = CSR_READ_4(sc, 0x7C00); + CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); + } + DELAY(10000); + + return(0); +} + +/* + * Frame reception handling. This is called if there's a frame + * on the receive return list. + * + * Note: we have to be able to handle two possibilities here: + * 1) the frame is from the jumbo receive ring + * 2) the frame is from the standard receive ring + */ + +static void +bge_rxeof(struct bge_softc *sc) +{ + struct ifnet *ifp; + int stdcnt = 0, jumbocnt = 0; + + BGE_LOCK_ASSERT(sc); + + /* Nothing to do. */ + if (sc->bge_rx_saved_considx == + sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) + return; + + ifp = sc->bge_ifp; + + bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, + sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); + if (BGE_IS_JUMBO_CAPABLE(sc)) + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); + + while(sc->bge_rx_saved_considx != + sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { + struct bge_rx_bd *cur_rx; + uint32_t rxidx; + struct mbuf *m = NULL; + uint16_t vlan_tag = 0; + int have_tag = 0; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + if (sc->rxcycles <= 0) + break; + sc->rxcycles--; + } +#endif + + cur_rx = + &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; + + rxidx = cur_rx->bge_idx; + BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); + + if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && + cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { + have_tag = 1; + vlan_tag = cur_rx->bge_vlan_tag; + } + + if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { + BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); + bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, + sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); + m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; + sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; + jumbocnt++; + if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { + ifp->if_ierrors++; + bge_newbuf_jumbo(sc, sc->bge_jumbo, m); + continue; + } + if (bge_newbuf_jumbo(sc, + sc->bge_jumbo, NULL) == ENOBUFS) { + ifp->if_ierrors++; + bge_newbuf_jumbo(sc, sc->bge_jumbo, m); + continue; + } + } else { + BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); + bus_dmamap_sync(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_std_dmamap[rxidx], + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_rx_std_dmamap[rxidx]); + m = sc->bge_cdata.bge_rx_std_chain[rxidx]; + sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; + stdcnt++; + if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { + ifp->if_ierrors++; + bge_newbuf_std(sc, sc->bge_std, m); + continue; + } + if (bge_newbuf_std(sc, sc->bge_std, + NULL) == ENOBUFS) { + ifp->if_ierrors++; + bge_newbuf_std(sc, sc->bge_std, m); + continue; + } + } + + ifp->if_ipackets++; +#ifndef __NO_STRICT_ALIGNMENT + /* + * For architectures with strict alignment we must make sure + * the payload is aligned. + */ + if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { + bcopy(m->m_data, m->m_data + ETHER_ALIGN, + cur_rx->bge_len); + m->m_data += ETHER_ALIGN; + } +#endif + m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; + m->m_pkthdr.rcvif = ifp; + + if (ifp->if_capenable & IFCAP_RXCSUM) { + if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + } + if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && + m->m_pkthdr.len >= ETHER_MIN_NOPAD) { + m->m_pkthdr.csum_data = + cur_rx->bge_tcp_udp_csum; + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID | CSUM_PSEUDO_HDR; + } + } + + /* + * If we received a packet with a vlan tag, + * attach that information to the packet. + */ + if (have_tag) { +#if __FreeBSD_version > 700022 + m->m_pkthdr.ether_vtag = vlan_tag; + m->m_flags |= M_VLANTAG; +#else + VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); + if (m == NULL) + continue; +#endif + } + + BGE_UNLOCK(sc); + (*ifp->if_input)(ifp, m); + BGE_LOCK(sc); + } + + if (stdcnt > 0) + bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, + sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); + + if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) + bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, + sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); + + CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); + if (stdcnt) + CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); + if (jumbocnt) + CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); +#ifdef notyet + /* + * This register wraps very quickly under heavy packet drops. + * If you need correct statistics, you can enable this check. + */ + if (BGE_IS_5705_PLUS(sc)) + ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); +#endif +} + +static void +bge_txeof(struct bge_softc *sc) +{ + struct bge_tx_bd *cur_tx = NULL; + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + /* Nothing to do. */ + if (sc->bge_tx_saved_considx == + sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) + return; + + ifp = sc->bge_ifp; + + bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, + sc->bge_cdata.bge_tx_ring_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + /* + * Go through our tx ring and free mbufs for those + * frames that have been sent. + */ + while (sc->bge_tx_saved_considx != + sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { + uint32_t idx = 0; + + idx = sc->bge_tx_saved_considx; + cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; + if (cur_tx->bge_flags & BGE_TXBDFLAG_END) + ifp->if_opackets++; + if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { + bus_dmamap_sync(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_tx_dmamap[idx], + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bge_cdata.bge_mtag, + sc->bge_cdata.bge_tx_dmamap[idx]); + m_freem(sc->bge_cdata.bge_tx_chain[idx]); + sc->bge_cdata.bge_tx_chain[idx] = NULL; + } + sc->bge_txcnt--; + BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); + } + + if (cur_tx != NULL) + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if (sc->bge_txcnt == 0) + sc->bge_timer = 0; +} + +#ifdef DEVICE_POLLING +static void +bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) +{ + struct bge_softc *sc = ifp->if_softc; + uint32_t statusword; + + BGE_LOCK(sc); + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + BGE_UNLOCK(sc); + return; + } + + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); + + statusword = atomic_readandclear_32( + &sc->bge_ldata.bge_status_block->bge_status); + + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); + + /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ + if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) + sc->bge_link_evt++; + + if (cmd == POLL_AND_CHECK_STATUS) + if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || + sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) + bge_link_upd(sc); + + sc->rxcycles = count; + bge_rxeof(sc); + bge_txeof(sc); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bge_start_locked(ifp); + + BGE_UNLOCK(sc); +} +#endif /* DEVICE_POLLING */ + +static void +bge_intr(void *xsc) +{ + struct bge_softc *sc; + struct ifnet *ifp; + uint32_t statusword; + + sc = xsc; + + BGE_LOCK(sc); + + ifp = sc->bge_ifp; + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + BGE_UNLOCK(sc); + return; + } +#endif + + /* + * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't + * disable interrupts by writing nonzero like we used to, since with + * our current organization this just gives complications and + * pessimizations for re-enabling interrupts. We used to have races + * instead of the necessary complications. Disabling interrupts + * would just reduce the chance of a status update while we are + * running (by switching to the interrupt-mode coalescence + * parameters), but this chance is already very low so it is more + * efficient to get another interrupt than prevent it. + * + * We do the ack first to ensure another interrupt if there is a + * status update after the ack. We don't check for the status + * changing later because it is more efficient to get another + * interrupt than prevent it, not quite as above (not checking is + * a smaller optimization than not toggling the interrupt enable, + * since checking doesn't involve PCI accesses and toggling require + * the status check). So toggling would probably be a pessimization + * even with MSI. It would only be needed for using a task queue. + */ + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); + + /* + * Do the mandatory PCI flush as well as get the link status. + */ + statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; + + /* Make sure the descriptor ring indexes are coherent. */ + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); + bus_dmamap_sync(sc->bge_cdata.bge_status_tag, + sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); + + if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || + statusword || sc->bge_link_evt) + bge_link_upd(sc); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + /* Check RX return ring producer/consumer. */ + bge_rxeof(sc); + + /* Check TX ring producer/consumer. */ + bge_txeof(sc); + } + + if (ifp->if_drv_flags & IFF_DRV_RUNNING && + !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + bge_start_locked(ifp); + + BGE_UNLOCK(sc); +} + +static void +bge_asf_driver_up(struct bge_softc *sc) +{ + if (sc->bge_asf_mode & ASF_STACKUP) { + /* Send ASF heartbeat aprox. every 2s */ + if (sc->bge_asf_count) + sc->bge_asf_count --; + else { + sc->bge_asf_count = 5; + bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, + BGE_FW_DRV_ALIVE); + bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); + bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); + CSR_WRITE_4(sc, BGE_CPU_EVENT, + CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); + } + } +} + +static void +bge_tick(void *xsc) +{ + struct bge_softc *sc = xsc; + struct mii_data *mii = NULL; + + BGE_LOCK_ASSERT(sc); + + /* Synchronize with possible callout reset/stop. */ + if (callout_pending(&sc->bge_stat_ch) || + !callout_active(&sc->bge_stat_ch)) + return; + + if (BGE_IS_5705_PLUS(sc)) + bge_stats_update_regs(sc); + else + bge_stats_update(sc); + + if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { + mii = device_get_softc(sc->bge_miibus); + /* Don't mess with the PHY in IPMI/ASF mode */ + if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link))) + mii_tick(mii); + } else { + /* + * Since in TBI mode auto-polling can't be used we should poll + * link status manually. Here we register pending link event + * and trigger interrupt. + */ +#ifdef DEVICE_POLLING + /* In polling mode we poll link state in bge_poll(). */ + if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) +#endif + { + sc->bge_link_evt++; + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); + } + } + + bge_asf_driver_up(sc); + bge_watchdog(sc); + + callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); +} + +static void +bge_stats_update_regs(struct bge_softc *sc) +{ + struct ifnet *ifp; + + ifp = sc->bge_ifp; + + ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + + offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); + + ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); +} + +static void +bge_stats_update(struct bge_softc *sc) +{ + struct ifnet *ifp; + bus_size_t stats; + uint32_t cnt; /* current register value */ + + ifp = sc->bge_ifp; + + stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; + +#define READ_STAT(sc, stats, stat) \ + CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) + + cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); + ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); + sc->bge_tx_collisions = cnt; + + cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); + ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); + sc->bge_rx_discards = cnt; + + cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); + ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); + sc->bge_tx_discards = cnt; + +#undef READ_STAT +} + +/* + * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. + * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, + * but when such padded frames employ the bge IP/TCP checksum offload, + * the hardware checksum assist gives incorrect results (possibly + * from incorporating its own padding into the UDP/TCP checksum; who knows). + * If we pad such runts with zeros, the onboard checksum comes out correct. + */ +static __inline int +bge_cksum_pad(struct mbuf *m) +{ + int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; + struct mbuf *last; + + /* If there's only the packet-header and we can pad there, use it. */ + if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && + M_TRAILINGSPACE(m) >= padlen) { + last = m; + } else { + /* + * Walk packet chain to find last mbuf. We will either + * pad there, or append a new mbuf and pad it. + */ + for (last = m; last->m_next != NULL; last = last->m_next); + if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { + /* Allocate new empty mbuf, pad it. Compact later. */ + struct mbuf *n; + + MGET(n, M_DONTWAIT, MT_DATA); + if (n == NULL) + return (ENOBUFS); + n->m_len = 0; + last->m_next = n; + last = n; + } + } + + /* Now zero the pad area, to avoid the bge cksum-assist bug. */ + memset(mtod(last, caddr_t) + last->m_len, 0, padlen); + last->m_len += padlen; + m->m_pkthdr.len += padlen; + + return (0); +} + +/* + * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data + * pointers to descriptors. + */ +static int +bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) +{ + bus_dma_segment_t segs[BGE_NSEG_NEW]; + bus_dmamap_t map; + struct bge_tx_bd *d; + struct mbuf *m = *m_head; + uint32_t idx = *txidx; + uint16_t csum_flags; + int nsegs, i, error; + + csum_flags = 0; + if (m->m_pkthdr.csum_flags) { + if (m->m_pkthdr.csum_flags & CSUM_IP) + csum_flags |= BGE_TXBDFLAG_IP_CSUM; + if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { + csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; + if (m->m_pkthdr.len < ETHER_MIN_NOPAD && + (error = bge_cksum_pad(m)) != 0) { + m_freem(m); + *m_head = NULL; + return (error); + } + } + if (m->m_flags & M_LASTFRAG) + csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; + else if (m->m_flags & M_FRAG) + csum_flags |= BGE_TXBDFLAG_IP_FRAG; + } + + map = sc->bge_cdata.bge_tx_dmamap[idx]; + error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, + &nsegs, BUS_DMA_NOWAIT); + if (error == EFBIG) { + m = m_defrag(m, M_DONTWAIT); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, + segs, &nsegs, BUS_DMA_NOWAIT); + if (error) { + m_freem(m); + *m_head = NULL; + return (error); + } + } else if (error != 0) + return (error); + + /* + * Sanity check: avoid coming within 16 descriptors + * of the end of the ring. + */ + if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { + bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); + return (ENOBUFS); + } + + bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); + + for (i = 0; ; i++) { + d = &sc->bge_ldata.bge_tx_ring[idx]; + d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); + d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); + d->bge_len = segs[i].ds_len; + d->bge_flags = csum_flags; + if (i == nsegs - 1) + break; + BGE_INC(idx, BGE_TX_RING_CNT); + } + + /* Mark the last segment as end of packet... */ + d->bge_flags |= BGE_TXBDFLAG_END; + + /* ... and put VLAN tag into first segment. */ + d = &sc->bge_ldata.bge_tx_ring[*txidx]; +#if __FreeBSD_version > 700022 + if (m->m_flags & M_VLANTAG) { + d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; + d->bge_vlan_tag = m->m_pkthdr.ether_vtag; + } else + d->bge_vlan_tag = 0; +#else + { + struct m_tag *mtag; + + if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { + d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; + d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); + } else + d->bge_vlan_tag = 0; + } +#endif + + /* + * Insure that the map for this transmission + * is placed at the array index of the last descriptor + * in this chain. + */ + sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; + sc->bge_cdata.bge_tx_dmamap[idx] = map; + sc->bge_cdata.bge_tx_chain[idx] = m; + sc->bge_txcnt += nsegs; + + BGE_INC(idx, BGE_TX_RING_CNT); + *txidx = idx; + + return (0); +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit descriptors. + */ +static void +bge_start_locked(struct ifnet *ifp) +{ + struct bge_softc *sc; + struct mbuf *m_head = NULL; + uint32_t prodidx; + int count = 0; + + sc = ifp->if_softc; + + if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + return; + + prodidx = sc->bge_tx_prodidx; + + while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); + if (m_head == NULL) + break; + + /* + * XXX + * The code inside the if() block is never reached since we + * must mark CSUM_IP_FRAGS in our if_hwassist to start getting + * requests to checksum TCP/UDP in a fragmented packet. + * + * XXX + * safety overkill. If this is a fragmented packet chain + * with delayed TCP/UDP checksums, then only encapsulate + * it if we have enough descriptors to handle the entire + * chain at once. + * (paranoia -- may not actually be needed) + */ + if (m_head->m_flags & M_FIRSTFRAG && + m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { + if ((BGE_TX_RING_CNT - sc->bge_txcnt) < + m_head->m_pkthdr.csum_data + 16) { + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + } + + /* + * Pack the data into the transmit ring. If we + * don't have room, set the OACTIVE flag and wait + * for the NIC to drain the ring. + */ + if (bge_encap(sc, &m_head, &prodidx)) { + if (m_head == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + ++count; + + /* + * If there's a BPF listener, bounce a copy of this frame + * to him. + */ +#ifdef ETHER_BPF_MTAP + ETHER_BPF_MTAP(ifp, m_head); +#else + BPF_MTAP(ifp, m_head); +#endif + } + + if (count == 0) + /* No packets were dequeued. */ + return; + + /* Transmit. */ + CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); + /* 5700 b2 errata */ + if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) + CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); + + sc->bge_tx_prodidx = prodidx; + + /* + * Set a timeout in case the chip goes out to lunch. + */ + sc->bge_timer = 5; +} + +/* + * Main transmit routine. To avoid having to do mbuf copies, we put pointers + * to the mbuf data regions directly in the transmit descriptors. + */ +static void +bge_start(struct ifnet *ifp) +{ + struct bge_softc *sc; + + sc = ifp->if_softc; + BGE_LOCK(sc); + bge_start_locked(ifp); + BGE_UNLOCK(sc); +} + +static void +bge_init_locked(struct bge_softc *sc) +{ + struct ifnet *ifp; + uint16_t *m; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + return; + + /* Cancel pending I/O and flush buffers. */ + bge_stop(sc); + + bge_stop_fw(sc); + bge_sig_pre_reset(sc, BGE_RESET_START); + bge_reset(sc); + bge_sig_legacy(sc, BGE_RESET_START); + bge_sig_post_reset(sc, BGE_RESET_START); + + bge_chipinit(sc); + + /* + * Init the various state machines, ring + * control blocks and firmware. + */ + if (bge_blockinit(sc)) { + device_printf(sc->bge_dev, "initialization failure\n"); + return; + } + + ifp = sc->bge_ifp; + + /* Specify MTU. */ + CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + + ETHER_HDR_LEN + ETHER_CRC_LEN + + (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); + + /* Load our MAC address. */ + m = (uint16_t *)IF_LLADDR(sc->bge_ifp); + CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); + CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); + + /* Program promiscuous mode. */ + bge_setpromisc(sc); + + /* Program multicast filter. */ + bge_setmulti(sc); + + /* Program VLAN tag stripping. */ + bge_setvlan(sc); + + /* Init RX ring. */ + bge_init_rx_ring_std(sc); + + /* + * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's + * memory to insure that the chip has in fact read the first + * entry of the ring. + */ + if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { + uint32_t v, i; + for (i = 0; i < 10; i++) { + DELAY(20); + v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); + if (v == (MCLBYTES - ETHER_ALIGN)) + break; + } + if (i == 10) + device_printf (sc->bge_dev, + "5705 A0 chip failed to load RX ring\n"); + } + + /* Init jumbo RX ring. */ + if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) + bge_init_rx_ring_jumbo(sc); + + /* Init our RX return ring index. */ + sc->bge_rx_saved_considx = 0; + + /* Init our RX/TX stat counters. */ + sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; + + /* Init TX ring. */ + bge_init_tx_ring(sc); + + /* Turn on transmitter. */ + BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); + + /* Turn on receiver. */ + BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); + + /* Tell firmware we're alive. */ + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + +#ifdef DEVICE_POLLING + /* Disable interrupts if we are polling. */ + if (ifp->if_capenable & IFCAP_POLLING) { + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_MASK_PCI_INTR); + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); + } else +#endif + + /* Enable host interrupts. */ + { + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); + BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); + } + + bge_ifmedia_upd_locked(ifp); + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); +} + +static void +bge_init(void *xsc) +{ + struct bge_softc *sc = xsc; + + BGE_LOCK(sc); + bge_init_locked(sc); + BGE_UNLOCK(sc); +} + +/* + * Set media options. + */ +static int +bge_ifmedia_upd(struct ifnet *ifp) +{ + struct bge_softc *sc = ifp->if_softc; + int res; + + BGE_LOCK(sc); + res = bge_ifmedia_upd_locked(ifp); + BGE_UNLOCK(sc); + + return (res); +} + +static int +bge_ifmedia_upd_locked(struct ifnet *ifp) +{ + struct bge_softc *sc = ifp->if_softc; + struct mii_data *mii; + struct ifmedia *ifm; + + BGE_LOCK_ASSERT(sc); + + ifm = &sc->bge_ifmedia; + + /* If this is a 1000baseX NIC, enable the TBI port. */ + if (sc->bge_flags & BGE_FLAG_TBI) { + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return (EINVAL); + switch(IFM_SUBTYPE(ifm->ifm_media)) { + case IFM_AUTO: + /* + * The BCM5704 ASIC appears to have a special + * mechanism for programming the autoneg + * advertisement registers in TBI mode. + */ + if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { + uint32_t sgdig; + sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); + if (sgdig & BGE_SGDIGSTS_DONE) { + CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); + sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); + sgdig |= BGE_SGDIGCFG_AUTO | + BGE_SGDIGCFG_PAUSE_CAP | + BGE_SGDIGCFG_ASYM_PAUSE; + CSR_WRITE_4(sc, BGE_SGDIG_CFG, + sgdig | BGE_SGDIGCFG_SEND); + DELAY(5); + CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); + } + } + break; + case IFM_1000_SX: + if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { + BGE_CLRBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_HALF_DUPLEX); + } else { + BGE_SETBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_HALF_DUPLEX); + } + break; + default: + return (EINVAL); + } + return (0); + } + + sc->bge_link_evt++; + mii = device_get_softc(sc->bge_miibus); + if (mii->mii_instance) { + struct mii_softc *miisc; + for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; + miisc = LIST_NEXT(miisc, mii_list)) + mii_phy_reset(miisc); + } + mii_mediachg(mii); + + return (0); +} + +/* + * Report current media status. + */ +static void +bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct bge_softc *sc = ifp->if_softc; + struct mii_data *mii; + + BGE_LOCK(sc); + + if (sc->bge_flags & BGE_FLAG_TBI) { + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_active = IFM_ETHER; + if (CSR_READ_4(sc, BGE_MAC_STS) & + BGE_MACSTAT_TBI_PCS_SYNCHED) + ifmr->ifm_status |= IFM_ACTIVE; + else { + ifmr->ifm_active |= IFM_NONE; + BGE_UNLOCK(sc); + return; + } + ifmr->ifm_active |= IFM_1000_SX; + if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) + ifmr->ifm_active |= IFM_HDX; + else + ifmr->ifm_active |= IFM_FDX; + BGE_UNLOCK(sc); + return; + } + + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; + + BGE_UNLOCK(sc); +} + +static int +bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) +{ + struct bge_softc *sc = ifp->if_softc; + struct ifreq *ifr = (struct ifreq *) data; + struct mii_data *mii; + int flags, mask, error = 0; + + switch (command) { + case SIOCSIFMTU: + if (ifr->ifr_mtu < ETHERMIN || + ((BGE_IS_JUMBO_CAPABLE(sc)) && + ifr->ifr_mtu > BGE_JUMBO_MTU) || + ((!BGE_IS_JUMBO_CAPABLE(sc)) && + ifr->ifr_mtu > ETHERMTU)) + error = EINVAL; + else if (ifp->if_mtu != ifr->ifr_mtu) { + ifp->if_mtu = ifr->ifr_mtu; + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bge_init(sc); + } + break; + case SIOCSIFFLAGS: + BGE_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + /* + * If only the state of the PROMISC flag changed, + * then just use the 'set promisc mode' command + * instead of reinitializing the entire NIC. Doing + * a full re-init means reloading the firmware and + * waiting for it to start up, which may take a + * second or two. Similarly for ALLMULTI. + */ + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + flags = ifp->if_flags ^ sc->bge_if_flags; + if (flags & IFF_PROMISC) + bge_setpromisc(sc); + if (flags & IFF_ALLMULTI) + bge_setmulti(sc); + } else + bge_init_locked(sc); + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + bge_stop(sc); + } + } + sc->bge_if_flags = ifp->if_flags; + BGE_UNLOCK(sc); + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + BGE_LOCK(sc); + bge_setmulti(sc); + BGE_UNLOCK(sc); + error = 0; + } + break; + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + if (sc->bge_flags & BGE_FLAG_TBI) { + error = ifmedia_ioctl(ifp, ifr, + &sc->bge_ifmedia, command); + } else { + mii = device_get_softc(sc->bge_miibus); + error = ifmedia_ioctl(ifp, ifr, + &mii->mii_media, command); + } + break; + case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; +#ifdef DEVICE_POLLING + if (mask & IFCAP_POLLING) { + if (ifr->ifr_reqcap & IFCAP_POLLING) { + error = ether_poll_register(bge_poll, ifp); + if (error) + return (error); + BGE_LOCK(sc); + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_MASK_PCI_INTR); + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); + ifp->if_capenable |= IFCAP_POLLING; + BGE_UNLOCK(sc); + } else { + error = ether_poll_deregister(ifp); + /* Enable interrupt even in error case */ + BGE_LOCK(sc); + BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, + BGE_PCIMISCCTL_MASK_PCI_INTR); + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); + ifp->if_capenable &= ~IFCAP_POLLING; + BGE_UNLOCK(sc); + } + } +#endif + if (mask & IFCAP_HWCSUM) { + ifp->if_capenable ^= IFCAP_HWCSUM; + if (IFCAP_HWCSUM & ifp->if_capenable && + IFCAP_HWCSUM & ifp->if_capabilities) + ifp->if_hwassist = BGE_CSUM_FEATURES; + else + ifp->if_hwassist = 0; +#ifdef VLAN_CAPABILITIES + VLAN_CAPABILITIES(ifp); +#endif + } + + if (mask & IFCAP_VLAN_MTU) { + ifp->if_capenable ^= IFCAP_VLAN_MTU; + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bge_init(sc); + } + + if (mask & IFCAP_VLAN_HWTAGGING) { + ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; + BGE_LOCK(sc); + bge_setvlan(sc); + BGE_UNLOCK(sc); +#ifdef VLAN_CAPABILITIES + VLAN_CAPABILITIES(ifp); +#endif + } + + break; + default: + error = ether_ioctl(ifp, command, data); + break; + } + + return (error); +} + +static void +bge_watchdog(struct bge_softc *sc) +{ + struct ifnet *ifp; + + BGE_LOCK_ASSERT(sc); + + if (sc->bge_timer == 0 || --sc->bge_timer) + return; + + ifp = sc->bge_ifp; + + if_printf(ifp, "watchdog timeout -- resetting\n"); + + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + bge_init_locked(sc); + + ifp->if_oerrors++; +} + +/* + * Stop the adapter and free any mbufs allocated to the + * RX and TX lists. + */ +static void +bge_stop(struct bge_softc *sc) +{ + struct ifnet *ifp; + struct ifmedia_entry *ifm; + struct mii_data *mii = NULL; + int mtmp, itmp; + + BGE_LOCK_ASSERT(sc); + + ifp = sc->bge_ifp; + + if ((sc->bge_flags & BGE_FLAG_TBI) == 0) + mii = device_get_softc(sc->bge_miibus); + + callout_stop(&sc->bge_stat_ch); + + /* + * Disable all of the receiver blocks. + */ + BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); + if (!(BGE_IS_5705_PLUS(sc))) + BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); + + /* + * Disable all of the transmit blocks. + */ + BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); + BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); + if (!(BGE_IS_5705_PLUS(sc))) + BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); + BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); + + /* + * Shut down all of the memory managers and related + * state machines. + */ + BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); + BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); + if (!(BGE_IS_5705_PLUS(sc))) + BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); + CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); + if (!(BGE_IS_5705_PLUS(sc))) { + BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); + BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); + } + + /* Disable host interrupts. */ + BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); + CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); + + /* + * Tell firmware we're shutting down. + */ + + bge_stop_fw(sc); + bge_sig_pre_reset(sc, BGE_RESET_STOP); + bge_reset(sc); + bge_sig_legacy(sc, BGE_RESET_STOP); + bge_sig_post_reset(sc, BGE_RESET_STOP); + + /* + * Keep the ASF firmware running if up. + */ + if (sc->bge_asf_mode & ASF_STACKUP) + BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + else + BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); + + /* Free the RX lists. */ + bge_free_rx_ring_std(sc); + + /* Free jumbo RX list. */ + if (BGE_IS_JUMBO_CAPABLE(sc)) + bge_free_rx_ring_jumbo(sc); + + /* Free TX buffers. */ + bge_free_tx_ring(sc); + + /* + * Isolate/power down the PHY, but leave the media selection + * unchanged so that things will be put back to normal when + * we bring the interface back up. + */ + if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { + itmp = ifp->if_flags; + ifp->if_flags |= IFF_UP; + /* + * If we are called from bge_detach(), mii is already NULL. + */ + if (mii != NULL) { + ifm = mii->mii_media.ifm_cur; + mtmp = ifm->ifm_media; + ifm->ifm_media = IFM_ETHER | IFM_NONE; + mii_mediachg(mii); + ifm->ifm_media = mtmp; + } + ifp->if_flags = itmp; + } + + sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; + + /* Clear MAC's link state (PHY may still have link UP). */ + if (bootverbose && sc->bge_link) + if_printf(sc->bge_ifp, "link DOWN\n"); + sc->bge_link = 0; + + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); +} + +/* + * Stop all chip I/O so that the kernel's probe routines don't + * get confused by errant DMAs when rebooting. + */ +static void +bge_shutdown(device_t dev) +{ + struct bge_softc *sc; + + sc = device_get_softc(dev); + + BGE_LOCK(sc); + bge_stop(sc); + bge_reset(sc); + BGE_UNLOCK(sc); +} + +static int +bge_suspend(device_t dev) +{ + struct bge_softc *sc; + + sc = device_get_softc(dev); + BGE_LOCK(sc); + bge_stop(sc); + BGE_UNLOCK(sc); + + return (0); +} + +static int +bge_resume(device_t dev) +{ + struct bge_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + BGE_LOCK(sc); + ifp = sc->bge_ifp; + if (ifp->if_flags & IFF_UP) { + bge_init_locked(sc); + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + bge_start_locked(ifp); + } + BGE_UNLOCK(sc); + + return (0); +} + +static void +bge_link_upd(struct bge_softc *sc) +{ + struct mii_data *mii; + uint32_t link, status; + + BGE_LOCK_ASSERT(sc); + + /* Clear 'pending link event' flag. */ + sc->bge_link_evt = 0; + + /* + * Process link state changes. + * Grrr. The link status word in the status block does + * not work correctly on the BCM5700 rev AX and BX chips, + * according to all available information. Hence, we have + * to enable MII interrupts in order to properly obtain + * async link changes. Unfortunately, this also means that + * we have to read the MAC status register to detect link + * changes, thereby adding an additional register access to + * the interrupt handler. + * + * XXX: perhaps link state detection procedure used for + * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. + */ + + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && + sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { + status = CSR_READ_4(sc, BGE_MAC_STS); + if (status & BGE_MACSTAT_MI_INTERRUPT) { + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + if (!sc->bge_link && + mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->bge_link++; + if (bootverbose) + if_printf(sc->bge_ifp, "link UP\n"); + } else if (sc->bge_link && + (!(mii->mii_media_status & IFM_ACTIVE) || + IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { + sc->bge_link = 0; + if (bootverbose) + if_printf(sc->bge_ifp, "link DOWN\n"); + } + + /* Clear the interrupt. */ + CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, + BGE_EVTENB_MI_INTERRUPT); + bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); + bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, + BRGPHY_INTRS); + } + return; + } + + if (sc->bge_flags & BGE_FLAG_TBI) { + status = CSR_READ_4(sc, BGE_MAC_STS); + if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { + if (!sc->bge_link) { + sc->bge_link++; + if (sc->bge_asicrev == BGE_ASICREV_BCM5704) + BGE_CLRBIT(sc, BGE_MAC_MODE, + BGE_MACMODE_TBI_SEND_CFGS); + CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); + if (bootverbose) + if_printf(sc->bge_ifp, "link UP\n"); + if_link_state_change(sc->bge_ifp, + LINK_STATE_UP); + } + } else if (sc->bge_link) { + sc->bge_link = 0; + if (bootverbose) + if_printf(sc->bge_ifp, "link DOWN\n"); + if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); + } + } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { + /* + * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit + * in status word always set. Workaround this bug by reading + * PHY link status directly. + */ + link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; + + if (link != sc->bge_link || + sc->bge_asicrev == BGE_ASICREV_BCM5700) { + mii = device_get_softc(sc->bge_miibus); + mii_pollstat(mii); + if (!sc->bge_link && + mii->mii_media_status & IFM_ACTIVE && + IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { + sc->bge_link++; + if (bootverbose) + if_printf(sc->bge_ifp, "link UP\n"); + } else if (sc->bge_link && + (!(mii->mii_media_status & IFM_ACTIVE) || + IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { + sc->bge_link = 0; + if (bootverbose) + if_printf(sc->bge_ifp, "link DOWN\n"); + } + } + } else { + /* + * Discard link events for MII/GMII controllers + * if MI auto-polling is disabled. + */ + } + + /* Clear the attention. */ + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | + BGE_MACSTAT_LINK_CHANGED); +} + +#define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ + SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ + sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ + desc) + +static void +bge_add_sysctls(struct bge_softc *sc) +{ + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *children, *schildren; + struct sysctl_oid *tree; + + ctx = device_get_sysctl_ctx(sc->bge_dev); + children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); + +#ifdef BGE_REGISTER_DEBUG + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", + CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", + "Debug Information"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", + CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", + "Register Read"); + + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", + CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", + "Memory Read"); + +#endif + + tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, + NULL, "BGE Statistics"); + schildren = children = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", + children, COSFramesDroppedDueToFilters, + "FramesDroppedDueToFilters"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", + children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", + children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", + children, nicNoMoreRxBDs, "NoMoreRxBDs"); + BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", + children, ifInDiscards, "InputDiscards"); + BGE_SYSCTL_STAT(sc, ctx, "Input Errors", + children, ifInErrors, "InputErrors"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", + children, nicRecvThresholdHit, "RecvThresholdHit"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", + children, nicDmaReadQueueFull, "DmaReadQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", + children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", + children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", + children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", + children, nicRingStatusUpdate, "RingStatusUpdate"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", + children, nicInterrupts, "Interrupts"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", + children, nicAvoidedInterrupts, "AvoidedInterrupts"); + BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", + children, nicSendThresholdHit, "SendThresholdHit"); + + tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, + NULL, "BGE RX Statistics"); + children = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", + children, rxstats.ifHCInOctets, "Octets"); + BGE_SYSCTL_STAT(sc, ctx, "Fragments", + children, rxstats.etherStatsFragments, "Fragments"); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", + children, rxstats.ifHCInUcastPkts, "UcastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", + children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", + children, rxstats.dot3StatsFCSErrors, "FCSErrors"); + BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", + children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); + BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", + children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); + BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", + children, rxstats.xoffPauseFramesReceived, + "xoffPauseFramesReceived"); + BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", + children, rxstats.macControlFramesReceived, + "ControlFramesReceived"); + BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", + children, rxstats.xoffStateEntered, "xoffStateEntered"); + BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", + children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); + BGE_SYSCTL_STAT(sc, ctx, "Jabbers", + children, rxstats.etherStatsJabbers, "Jabbers"); + BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", + children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); + BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", + children, rxstats.inRangeLengthError, "inRangeLengthError"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", + children, rxstats.outRangeLengthError, "outRangeLengthError"); + + tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, + NULL, "BGE TX Statistics"); + children = SYSCTL_CHILDREN(tree); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", + children, txstats.ifHCOutOctets, "Octets"); + BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", + children, txstats.etherStatsCollisions, "Collisions"); + BGE_SYSCTL_STAT(sc, ctx, "XON Sent", + children, txstats.outXonSent, "XonSent"); + BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", + children, txstats.outXoffSent, "XoffSent"); + BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", + children, txstats.flowControlDone, "flowControlDone"); + BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", + children, txstats.dot3StatsInternalMacTransmitErrors, + "InternalMacTransmitErrors"); + BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", + children, txstats.dot3StatsSingleCollisionFrames, + "SingleCollisionFrames"); + BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", + children, txstats.dot3StatsMultipleCollisionFrames, + "MultipleCollisionFrames"); + BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", + children, txstats.dot3StatsDeferredTransmissions, + "DeferredTransmissions"); + BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", + children, txstats.dot3StatsExcessiveCollisions, + "ExcessiveCollisions"); + BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", + children, txstats.dot3StatsLateCollisions, + "LateCollisions"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", + children, txstats.ifHCOutUcastPkts, "UcastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", + children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", + children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); + BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", + children, txstats.dot3StatsCarrierSenseErrors, + "CarrierSenseErrors"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", + children, txstats.ifOutDiscards, "Discards"); + BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", + children, txstats.ifOutErrors, "Errors"); +} + +static int +bge_sysctl_stats(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + uint32_t result; + int base, offset; + + sc = (struct bge_softc *)arg1; + offset = arg2; + if (BGE_IS_5705_PLUS(sc)) + base = BGE_MAC_STATS; + else + base = BGE_MEMWIN_START + BGE_STATS_BLOCK; + result = CSR_READ_4(sc, base + offset + offsetof(bge_hostaddr, + bge_addr_lo)); + return (sysctl_handle_int(oidp, &result, 0, req)); +} + +#ifdef BGE_REGISTER_DEBUG +static int +bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + uint16_t *sbdata; + int error; + int result; + int i, j; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + if (result == 1) { + sc = (struct bge_softc *)arg1; + + sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; + printf("Status Block:\n"); + for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { + printf("%06x:", i); + for (j = 0; j < 8; j++) { + printf(" %04x", sbdata[i]); + i += 4; + } + printf("\n"); + } + + printf("Registers:\n"); + for (i = 0x800; i < 0xA00; ) { + printf("%06x:", i); + for (j = 0; j < 8; j++) { + printf(" %08x", CSR_READ_4(sc, i)); + i += 4; + } + printf("\n"); + } + + printf("Hardware Flags:\n"); + if (BGE_IS_575X_PLUS(sc)) + printf(" - 575X Plus\n"); + if (BGE_IS_5705_PLUS(sc)) + printf(" - 5705 Plus\n"); + if (BGE_IS_5714_FAMILY(sc)) + printf(" - 5714 Family\n"); + if (BGE_IS_5700_FAMILY(sc)) + printf(" - 5700 Family\n"); + if (sc->bge_flags & BGE_FLAG_JUMBO) + printf(" - Supports Jumbo Frames\n"); + if (sc->bge_flags & BGE_FLAG_PCIX) + printf(" - PCI-X Bus\n"); + if (sc->bge_flags & BGE_FLAG_PCIE) + printf(" - PCI Express Bus\n"); + if (sc->bge_flags & BGE_FLAG_NO_3LED) + printf(" - No 3 LEDs\n"); + if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) + printf(" - RX Alignment Bug\n"); + } + + return (error); +} + +static int +bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + int error; + uint16_t result; + uint32_t val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + if (result < 0x8000) { + sc = (struct bge_softc *)arg1; + val = CSR_READ_4(sc, result); + printf("reg 0x%06X = 0x%08X\n", result, val); + } + + return (error); +} + +static int +bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) +{ + struct bge_softc *sc; + int error; + uint16_t result; + uint32_t val; + + result = -1; + error = sysctl_handle_int(oidp, &result, 0, req); + if (error || (req->newptr == NULL)) + return (error); + + if (result < 0x8000) { + sc = (struct bge_softc *)arg1; + val = bge_readmem_ind(sc, result); + printf("mem 0x%06X = 0x%08X\n", result, val); + } + + return (error); +} +#endif diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bgereg.h b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bgereg.h new file mode 100644 index 0000000000..8566489de3 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/bge/if_bgereg.h @@ -0,0 +1,2516 @@ +/*- + * Copyright (c) 2001 Wind River Systems + * Copyright (c) 1997, 1998, 1999, 2001 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.73 2007/05/22 19:22:58 jkim Exp $ + */ + +/* + * BCM570x memory map. The internal memory layout varies somewhat + * depending on whether or not we have external SSRAM attached. + * The BCM5700 can have up to 16MB of external memory. The BCM5701 + * is apparently not designed to use external SSRAM. The mappings + * up to the first 4 send rings are the same for both internal and + * external memory configurations. Note that mini RX ring space is + * only available with external SSRAM configurations, which means + * the mini RX ring is not supported on the BCM5701. + * + * The NIC's memory can be accessed by the host in one of 3 ways: + * + * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA + * registers in PCI config space can be used to read any 32-bit + * address within the NIC's memory. + * + * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config + * space can be used in conjunction with the memory window in the + * device register space at offset 0x8000 to read any 32K chunk + * of NIC memory. + * + * 3) Flat mode. If the 'flat mode' bit in the PCI state register is + * set, the device I/O mapping consumes 32MB of host address space, + * allowing all of the registers and internal NIC memory to be + * accessed directly. NIC memory addresses are offset by 0x01000000. + * Flat mode consumes so much host address space that it is not + * recommended. + */ +#define BGE_PAGE_ZERO 0x00000000 +#define BGE_PAGE_ZERO_END 0x000000FF +#define BGE_SEND_RING_RCB 0x00000100 +#define BGE_SEND_RING_RCB_END 0x000001FF +#define BGE_RX_RETURN_RING_RCB 0x00000200 +#define BGE_RX_RETURN_RING_RCB_END 0x000002FF +#define BGE_STATS_BLOCK 0x00000300 +#define BGE_STATS_BLOCK_END 0x00000AFF +#define BGE_STATUS_BLOCK 0x00000B00 +#define BGE_STATUS_BLOCK_END 0x00000B4F +#define BGE_SOFTWARE_GENCOMM 0x00000B50 +#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 +#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 +#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 +#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C +#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 +#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF +#define BGE_UNMAPPED 0x00001000 +#define BGE_UNMAPPED_END 0x00001FFF +#define BGE_DMA_DESCRIPTORS 0x00002000 +#define BGE_DMA_DESCRIPTORS_END 0x00003FFF +#define BGE_SEND_RING_1_TO_4 0x00004000 +#define BGE_SEND_RING_1_TO_4_END 0x00005FFF + +/* Firmware interface */ +#define BGE_FW_DRV_ALIVE 0x00000001 +#define BGE_FW_PAUSE 0x00000002 + +/* Mappings for internal memory configuration */ +#define BGE_STD_RX_RINGS 0x00006000 +#define BGE_STD_RX_RINGS_END 0x00006FFF +#define BGE_JUMBO_RX_RINGS 0x00007000 +#define BGE_JUMBO_RX_RINGS_END 0x00007FFF +#define BGE_BUFFPOOL_1 0x00008000 +#define BGE_BUFFPOOL_1_END 0x0000FFFF +#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ +#define BGE_BUFFPOOL_2_END 0x00017FFF +#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ +#define BGE_BUFFPOOL_3_END 0x0001FFFF + +/* Mappings for external SSRAM configurations */ +#define BGE_SEND_RING_5_TO_6 0x00006000 +#define BGE_SEND_RING_5_TO_6_END 0x00006FFF +#define BGE_SEND_RING_7_TO_8 0x00007000 +#define BGE_SEND_RING_7_TO_8_END 0x00007FFF +#define BGE_SEND_RING_9_TO_16 0x00008000 +#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF +#define BGE_EXT_STD_RX_RINGS 0x0000C000 +#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF +#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 +#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF +#define BGE_MINI_RX_RINGS 0x0000E000 +#define BGE_MINI_RX_RINGS_END 0x0000FFFF +#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ +#define BGE_AVAIL_REGION1_END 0x00017FFF +#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ +#define BGE_AVAIL_REGION2_END 0x0001FFFF +#define BGE_EXT_SSRAM 0x00020000 +#define BGE_EXT_SSRAM_END 0x000FFFFF + + +/* + * BCM570x register offsets. These are memory mapped registers + * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. + * Each register must be accessed using 32 bit operations. + * + * All registers are accessed through a 32K shared memory block. + * The first group of registers are actually copies of the PCI + * configuration space registers. + */ + +/* + * PCI registers defined in the PCI 2.2 spec. + */ +#define BGE_PCI_VID 0x00 +#define BGE_PCI_DID 0x02 +#define BGE_PCI_CMD 0x04 +#define BGE_PCI_STS 0x06 +#define BGE_PCI_REV 0x08 +#define BGE_PCI_CLASS 0x09 +#define BGE_PCI_CACHESZ 0x0C +#define BGE_PCI_LATTIMER 0x0D +#define BGE_PCI_HDRTYPE 0x0E +#define BGE_PCI_BIST 0x0F +#define BGE_PCI_BAR0 0x10 +#define BGE_PCI_BAR1 0x14 +#define BGE_PCI_SUBSYS 0x2C +#define BGE_PCI_SUBVID 0x2E +#define BGE_PCI_ROMBASE 0x30 +#define BGE_PCI_CAPPTR 0x34 +#define BGE_PCI_INTLINE 0x3C +#define BGE_PCI_INTPIN 0x3D +#define BGE_PCI_MINGNT 0x3E +#define BGE_PCI_MAXLAT 0x3F +#define BGE_PCI_PCIXCAP 0x40 +#define BGE_PCI_NEXTPTR_PM 0x41 +#define BGE_PCI_PCIX_CMD 0x42 +#define BGE_PCI_PCIX_STS 0x44 +#define BGE_PCI_PWRMGMT_CAPID 0x48 +#define BGE_PCI_NEXTPTR_VPD 0x49 +#define BGE_PCI_PWRMGMT_CAPS 0x4A +#define BGE_PCI_PWRMGMT_CMD 0x4C +#define BGE_PCI_PWRMGMT_STS 0x4D +#define BGE_PCI_PWRMGMT_DATA 0x4F +#define BGE_PCI_VPD_CAPID 0x50 +#define BGE_PCI_NEXTPTR_MSI 0x51 +#define BGE_PCI_VPD_ADDR 0x52 +#define BGE_PCI_VPD_DATA 0x54 +#define BGE_PCI_MSI_CAPID 0x58 +#define BGE_PCI_NEXTPTR_NONE 0x59 +#define BGE_PCI_MSI_CTL 0x5A +#define BGE_PCI_MSI_ADDR_HI 0x5C +#define BGE_PCI_MSI_ADDR_LO 0x60 +#define BGE_PCI_MSI_DATA 0x64 + +/* PCI MSI. ??? */ +#define BGE_PCIE_CAPID_REG 0xD0 +#define BGE_PCIE_CAPID 0x10 + +/* + * PCI registers specific to the BCM570x family. + */ +#define BGE_PCI_MISC_CTL 0x68 +#define BGE_PCI_DMA_RW_CTL 0x6C +#define BGE_PCI_PCISTATE 0x70 +#define BGE_PCI_CLKCTL 0x74 +#define BGE_PCI_REG_BASEADDR 0x78 +#define BGE_PCI_MEMWIN_BASEADDR 0x7C +#define BGE_PCI_REG_DATA 0x80 +#define BGE_PCI_MEMWIN_DATA 0x84 +#define BGE_PCI_MODECTL 0x88 +#define BGE_PCI_MISC_CFG 0x8C +#define BGE_PCI_MISC_LOCALCTL 0x90 +#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 +#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C +#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 +#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 +#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 +#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC +#define BGE_PCI_ISR_MBX_HI 0xB0 +#define BGE_PCI_ISR_MBX_LO 0xB4 + +/* PCI Misc. Host control register */ +#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 +#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 +#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 +#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 +#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 +#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 +#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 +#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 +#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 + +#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) +#if BYTE_ORDER == LITTLE_ENDIAN +#define BGE_DMA_SWAP_OPTIONS \ + BGE_MODECTL_WORDSWAP_NONFRAME| \ + BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA +#else +#define BGE_DMA_SWAP_OPTIONS \ + BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ + BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA +#endif + +#define BGE_INIT \ + (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ + BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) + +#define BGE_CHIPID_TIGON_I 0x40000000 +#define BGE_CHIPID_TIGON_II 0x60000000 +#define BGE_CHIPID_BCM5700_A0 0x70000000 +#define BGE_CHIPID_BCM5700_A1 0x70010000 +#define BGE_CHIPID_BCM5700_B0 0x71000000 +#define BGE_CHIPID_BCM5700_B1 0x71010000 +#define BGE_CHIPID_BCM5700_B2 0x71020000 +#define BGE_CHIPID_BCM5700_B3 0x71030000 +#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 +#define BGE_CHIPID_BCM5700_C0 0x72000000 +#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ +#define BGE_CHIPID_BCM5701_B0 0x01000000 +#define BGE_CHIPID_BCM5701_B2 0x01020000 +#define BGE_CHIPID_BCM5701_B5 0x01050000 +#define BGE_CHIPID_BCM5703_A0 0x10000000 +#define BGE_CHIPID_BCM5703_A1 0x10010000 +#define BGE_CHIPID_BCM5703_A2 0x10020000 +#define BGE_CHIPID_BCM5703_A3 0x10030000 +#define BGE_CHIPID_BCM5703_B0 0x11000000 +#define BGE_CHIPID_BCM5704_A0 0x20000000 +#define BGE_CHIPID_BCM5704_A1 0x20010000 +#define BGE_CHIPID_BCM5704_A2 0x20020000 +#define BGE_CHIPID_BCM5704_A3 0x20030000 +#define BGE_CHIPID_BCM5704_B0 0x21000000 +#define BGE_CHIPID_BCM5705_A0 0x30000000 +#define BGE_CHIPID_BCM5705_A1 0x30010000 +#define BGE_CHIPID_BCM5705_A2 0x30020000 +#define BGE_CHIPID_BCM5705_A3 0x30030000 +#define BGE_CHIPID_BCM5750_A0 0x40000000 +#define BGE_CHIPID_BCM5750_A1 0x40010000 +#define BGE_CHIPID_BCM5750_A3 0x40030000 +#define BGE_CHIPID_BCM5750_B0 0x41000000 +#define BGE_CHIPID_BCM5750_B1 0x41010000 +#define BGE_CHIPID_BCM5750_C0 0x42000000 +#define BGE_CHIPID_BCM5750_C1 0x42010000 +#define BGE_CHIPID_BCM5750_C2 0x42020000 +#define BGE_CHIPID_BCM5714_A0 0x50000000 +#define BGE_CHIPID_BCM5752_A0 0x60000000 +#define BGE_CHIPID_BCM5752_A1 0x60010000 +#define BGE_CHIPID_BCM5752_A2 0x60020000 +#define BGE_CHIPID_BCM5714_B0 0x80000000 +#define BGE_CHIPID_BCM5714_B3 0x80030000 +#define BGE_CHIPID_BCM5715_A0 0x90000000 +#define BGE_CHIPID_BCM5715_A1 0x90010000 +#define BGE_CHIPID_BCM5715_A3 0x90030000 +#define BGE_CHIPID_BCM5755_A0 0xa0000000 +#define BGE_CHIPID_BCM5755_A1 0xa0010000 +#define BGE_CHIPID_BCM5755_A2 0xa0020000 +#define BGE_CHIPID_BCM5754_A0 0xb0000000 +#define BGE_CHIPID_BCM5754_A1 0xb0010000 +#define BGE_CHIPID_BCM5754_A2 0xb0020000 +#define BGE_CHIPID_BCM5787_A0 0xb0000000 +#define BGE_CHIPID_BCM5787_A1 0xb0010000 +#define BGE_CHIPID_BCM5787_A2 0xb0020000 + +/* shorthand one */ +#define BGE_ASICREV(x) ((x) >> 28) +#define BGE_ASICREV_BCM5701 0x00 +#define BGE_ASICREV_BCM5703 0x01 +#define BGE_ASICREV_BCM5704 0x02 +#define BGE_ASICREV_BCM5705 0x03 +#define BGE_ASICREV_BCM5750 0x04 +#define BGE_ASICREV_BCM5714_A0 0x05 +#define BGE_ASICREV_BCM5752 0x06 +#define BGE_ASICREV_BCM5700 0x07 +#define BGE_ASICREV_BCM5780 0x08 +#define BGE_ASICREV_BCM5714 0x09 +#define BGE_ASICREV_BCM5755 0x0a +#define BGE_ASICREV_BCM5754 0x0b +#define BGE_ASICREV_BCM5787 0x0b + +/* chip revisions */ +#define BGE_CHIPREV(x) ((x) >> 24) +#define BGE_CHIPREV_5700_AX 0x70 +#define BGE_CHIPREV_5700_BX 0x71 +#define BGE_CHIPREV_5700_CX 0x72 +#define BGE_CHIPREV_5701_AX 0x00 +#define BGE_CHIPREV_5703_AX 0x10 +#define BGE_CHIPREV_5704_AX 0x20 +#define BGE_CHIPREV_5704_BX 0x21 +#define BGE_CHIPREV_5750_AX 0x40 +#define BGE_CHIPREV_5750_BX 0x41 + +/* PCI DMA Read/Write Control register */ +#define BGE_PCIDMARWCTL_MINDMA 0x000000FF +#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 +#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 +#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 +#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 +#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 +#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 +#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 +#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 + +#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) +#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) +#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) +#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) + +#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 +#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 +#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 +#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 +#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 +#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 +#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 +#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 + +#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 +#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 +#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 +#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 +#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 +#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 +#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 +#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 + +/* + * PCI state register -- note, this register is read only + * unless the PCISTATE_WR bit of the PCI Misc. Host Control + * register is set. + */ +#define BGE_PCISTATE_FORCE_RESET 0x00000001 +#define BGE_PCISTATE_INTR_STATE 0x00000002 +#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ +#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ +#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ +#define BGE_PCISTATE_WANT_EXPROM 0x00000020 +#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 +#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 +#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 + +/* + * PCI Clock Control register -- note, this register is read only + * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control + * register is set. + */ +#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F +#define BGE_PCICLOCKCTL_M66EN 0x00000080 +#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 +#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 +#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 +#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 +#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 +#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 +#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 +#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 + + +#ifndef PCIM_CMD_MWIEN +#define PCIM_CMD_MWIEN 0x0010 +#endif + +/* + * High priority mailbox registers + * Each mailbox is 64-bits wide, though we only use the + * lower 32 bits. To write a 64-bit value, write the upper 32 bits + * first. The NIC will load the mailbox after the lower 32 bit word + * has been updated. + */ +#define BGE_MBX_IRQ0_HI 0x0200 +#define BGE_MBX_IRQ0_LO 0x0204 +#define BGE_MBX_IRQ1_HI 0x0208 +#define BGE_MBX_IRQ1_LO 0x020C +#define BGE_MBX_IRQ2_HI 0x0210 +#define BGE_MBX_IRQ2_LO 0x0214 +#define BGE_MBX_IRQ3_HI 0x0218 +#define BGE_MBX_IRQ3_LO 0x021C +#define BGE_MBX_GEN0_HI 0x0220 +#define BGE_MBX_GEN0_LO 0x0224 +#define BGE_MBX_GEN1_HI 0x0228 +#define BGE_MBX_GEN1_LO 0x022C +#define BGE_MBX_GEN2_HI 0x0230 +#define BGE_MBX_GEN2_LO 0x0234 +#define BGE_MBX_GEN3_HI 0x0228 +#define BGE_MBX_GEN3_LO 0x022C +#define BGE_MBX_GEN4_HI 0x0240 +#define BGE_MBX_GEN4_LO 0x0244 +#define BGE_MBX_GEN5_HI 0x0248 +#define BGE_MBX_GEN5_LO 0x024C +#define BGE_MBX_GEN6_HI 0x0250 +#define BGE_MBX_GEN6_LO 0x0254 +#define BGE_MBX_GEN7_HI 0x0258 +#define BGE_MBX_GEN7_LO 0x025C +#define BGE_MBX_RELOAD_STATS_HI 0x0260 +#define BGE_MBX_RELOAD_STATS_LO 0x0264 +#define BGE_MBX_RX_STD_PROD_HI 0x0268 +#define BGE_MBX_RX_STD_PROD_LO 0x026C +#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 +#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 +#define BGE_MBX_RX_MINI_PROD_HI 0x0278 +#define BGE_MBX_RX_MINI_PROD_LO 0x027C +#define BGE_MBX_RX_CONS0_HI 0x0280 +#define BGE_MBX_RX_CONS0_LO 0x0284 +#define BGE_MBX_RX_CONS1_HI 0x0288 +#define BGE_MBX_RX_CONS1_LO 0x028C +#define BGE_MBX_RX_CONS2_HI 0x0290 +#define BGE_MBX_RX_CONS2_LO 0x0294 +#define BGE_MBX_RX_CONS3_HI 0x0298 +#define BGE_MBX_RX_CONS3_LO 0x029C +#define BGE_MBX_RX_CONS4_HI 0x02A0 +#define BGE_MBX_RX_CONS4_LO 0x02A4 +#define BGE_MBX_RX_CONS5_HI 0x02A8 +#define BGE_MBX_RX_CONS5_LO 0x02AC +#define BGE_MBX_RX_CONS6_HI 0x02B0 +#define BGE_MBX_RX_CONS6_LO 0x02B4 +#define BGE_MBX_RX_CONS7_HI 0x02B8 +#define BGE_MBX_RX_CONS7_LO 0x02BC +#define BGE_MBX_RX_CONS8_HI 0x02C0 +#define BGE_MBX_RX_CONS8_LO 0x02C4 +#define BGE_MBX_RX_CONS9_HI 0x02C8 +#define BGE_MBX_RX_CONS9_LO 0x02CC +#define BGE_MBX_RX_CONS10_HI 0x02D0 +#define BGE_MBX_RX_CONS10_LO 0x02D4 +#define BGE_MBX_RX_CONS11_HI 0x02D8 +#define BGE_MBX_RX_CONS11_LO 0x02DC +#define BGE_MBX_RX_CONS12_HI 0x02E0 +#define BGE_MBX_RX_CONS12_LO 0x02E4 +#define BGE_MBX_RX_CONS13_HI 0x02E8 +#define BGE_MBX_RX_CONS13_LO 0x02EC +#define BGE_MBX_RX_CONS14_HI 0x02F0 +#define BGE_MBX_RX_CONS14_LO 0x02F4 +#define BGE_MBX_RX_CONS15_HI 0x02F8 +#define BGE_MBX_RX_CONS15_LO 0x02FC +#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 +#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 +#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 +#define BGE_MBX_TX_HOST_PROD1_LO 0x030C +#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 +#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 +#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 +#define BGE_MBX_TX_HOST_PROD3_LO 0x031C +#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 +#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 +#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 +#define BGE_MBX_TX_HOST_PROD5_LO 0x032C +#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 +#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 +#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 +#define BGE_MBX_TX_HOST_PROD7_LO 0x033C +#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 +#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 +#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 +#define BGE_MBX_TX_HOST_PROD9_LO 0x034C +#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 +#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 +#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 +#define BGE_MBX_TX_HOST_PROD11_LO 0x035C +#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 +#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 +#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 +#define BGE_MBX_TX_HOST_PROD13_LO 0x036C +#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 +#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 +#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 +#define BGE_MBX_TX_HOST_PROD15_LO 0x037C +#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 +#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 +#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 +#define BGE_MBX_TX_NIC_PROD1_LO 0x038C +#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 +#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 +#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 +#define BGE_MBX_TX_NIC_PROD3_LO 0x039C +#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 +#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 +#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 +#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC +#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 +#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 +#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 +#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC +#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 +#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 +#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 +#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC +#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 +#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 +#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 +#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC +#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 +#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 +#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 +#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC +#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 +#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 +#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 +#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC + +#define BGE_TX_RINGS_MAX 4 +#define BGE_TX_RINGS_EXTSSRAM_MAX 16 +#define BGE_RX_RINGS_MAX 16 + +/* Ethernet MAC control registers */ +#define BGE_MAC_MODE 0x0400 +#define BGE_MAC_STS 0x0404 +#define BGE_MAC_EVT_ENB 0x0408 +#define BGE_MAC_LED_CTL 0x040C +#define BGE_MAC_ADDR1_LO 0x0410 +#define BGE_MAC_ADDR1_HI 0x0414 +#define BGE_MAC_ADDR2_LO 0x0418 +#define BGE_MAC_ADDR2_HI 0x041C +#define BGE_MAC_ADDR3_LO 0x0420 +#define BGE_MAC_ADDR3_HI 0x0424 +#define BGE_MAC_ADDR4_LO 0x0428 +#define BGE_MAC_ADDR4_HI 0x042C +#define BGE_WOL_PATPTR 0x0430 +#define BGE_WOL_PATCFG 0x0434 +#define BGE_TX_RANDOM_BACKOFF 0x0438 +#define BGE_RX_MTU 0x043C +#define BGE_GBIT_PCS_TEST 0x0440 +#define BGE_TX_TBI_AUTONEG 0x0444 +#define BGE_RX_TBI_AUTONEG 0x0448 +#define BGE_MI_COMM 0x044C +#define BGE_MI_STS 0x0450 +#define BGE_MI_MODE 0x0454 +#define BGE_AUTOPOLL_STS 0x0458 +#define BGE_TX_MODE 0x045C +#define BGE_TX_STS 0x0460 +#define BGE_TX_LENGTHS 0x0464 +#define BGE_RX_MODE 0x0468 +#define BGE_RX_STS 0x046C +#define BGE_MAR0 0x0470 +#define BGE_MAR1 0x0474 +#define BGE_MAR2 0x0478 +#define BGE_MAR3 0x047C +#define BGE_RX_BD_RULES_CTL0 0x0480 +#define BGE_RX_BD_RULES_MASKVAL0 0x0484 +#define BGE_RX_BD_RULES_CTL1 0x0488 +#define BGE_RX_BD_RULES_MASKVAL1 0x048C +#define BGE_RX_BD_RULES_CTL2 0x0490 +#define BGE_RX_BD_RULES_MASKVAL2 0x0494 +#define BGE_RX_BD_RULES_CTL3 0x0498 +#define BGE_RX_BD_RULES_MASKVAL3 0x049C +#define BGE_RX_BD_RULES_CTL4 0x04A0 +#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 +#define BGE_RX_BD_RULES_CTL5 0x04A8 +#define BGE_RX_BD_RULES_MASKVAL5 0x04AC +#define BGE_RX_BD_RULES_CTL6 0x04B0 +#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 +#define BGE_RX_BD_RULES_CTL7 0x04B8 +#define BGE_RX_BD_RULES_MASKVAL7 0x04BC +#define BGE_RX_BD_RULES_CTL8 0x04C0 +#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 +#define BGE_RX_BD_RULES_CTL9 0x04C8 +#define BGE_RX_BD_RULES_MASKVAL9 0x04CC +#define BGE_RX_BD_RULES_CTL10 0x04D0 +#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 +#define BGE_RX_BD_RULES_CTL11 0x04D8 +#define BGE_RX_BD_RULES_MASKVAL11 0x04DC +#define BGE_RX_BD_RULES_CTL12 0x04E0 +#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 +#define BGE_RX_BD_RULES_CTL13 0x04E8 +#define BGE_RX_BD_RULES_MASKVAL13 0x04EC +#define BGE_RX_BD_RULES_CTL14 0x04F0 +#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 +#define BGE_RX_BD_RULES_CTL15 0x04F8 +#define BGE_RX_BD_RULES_MASKVAL15 0x04FC +#define BGE_RX_RULES_CFG 0x0500 +#define BGE_SERDES_CFG 0x0590 +#define BGE_SERDES_STS 0x0594 +#define BGE_SGDIG_CFG 0x05B0 +#define BGE_SGDIG_STS 0x05B4 +#define BGE_MAC_STATS 0x0800 + +/* Ethernet MAC Mode register */ +#define BGE_MACMODE_RESET 0x00000001 +#define BGE_MACMODE_HALF_DUPLEX 0x00000002 +#define BGE_MACMODE_PORTMODE 0x0000000C +#define BGE_MACMODE_LOOPBACK 0x00000010 +#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 +#define BGE_MACMODE_TX_BURST_ENB 0x00000100 +#define BGE_MACMODE_MAX_DEFER 0x00000200 +#define BGE_MACMODE_LINK_POLARITY 0x00000400 +#define BGE_MACMODE_RX_STATS_ENB 0x00000800 +#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 +#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 +#define BGE_MACMODE_TX_STATS_ENB 0x00004000 +#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 +#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 +#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 +#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 +#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 +#define BGE_MACMODE_MIP_ENB 0x00100000 +#define BGE_MACMODE_TXDMA_ENB 0x00200000 +#define BGE_MACMODE_RXDMA_ENB 0x00400000 +#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 + +#define BGE_PORTMODE_NONE 0x00000000 +#define BGE_PORTMODE_MII 0x00000004 +#define BGE_PORTMODE_GMII 0x00000008 +#define BGE_PORTMODE_TBI 0x0000000C + +/* MAC Status register */ +#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 +#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 +#define BGE_MACSTAT_RX_CFG 0x00000004 +#define BGE_MACSTAT_CFG_CHANGED 0x00000008 +#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 +#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 +#define BGE_MACSTAT_LINK_CHANGED 0x00001000 +#define BGE_MACSTAT_MI_COMPLETE 0x00400000 +#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 +#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 +#define BGE_MACSTAT_ODI_ERROR 0x02000000 +#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 +#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 + +/* MAC Event Enable Register */ +#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 +#define BGE_EVTENB_LINK_CHANGED 0x00001000 +#define BGE_EVTENB_MI_COMPLETE 0x00400000 +#define BGE_EVTENB_MI_INTERRUPT 0x00800000 +#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 +#define BGE_EVTENB_ODI_ERROR 0x02000000 +#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 +#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 + +/* LED Control Register */ +#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 +#define BGE_LEDCTL_1000MBPS_LED 0x00000002 +#define BGE_LEDCTL_100MBPS_LED 0x00000004 +#define BGE_LEDCTL_10MBPS_LED 0x00000008 +#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 +#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 +#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 +#define BGE_LEDCTL_1000MBPS_STS 0x00000080 +#define BGE_LEDCTL_100MBPS_STS 0x00000100 +#define BGE_LEDCTL_10MBPS_STS 0x00000200 +#define BGE_LEDCTL_TRADLED_STS 0x00000400 +#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 +#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 + +/* TX backoff seed register */ +#define BGE_TX_BACKOFF_SEED_MASK 0x3F + +/* Autopoll status register */ +#define BGE_AUTOPOLLSTS_ERROR 0x00000001 + +/* Transmit MAC mode register */ +#define BGE_TXMODE_RESET 0x00000001 +#define BGE_TXMODE_ENABLE 0x00000002 +#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 +#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 +#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 + +/* Transmit MAC status register */ +#define BGE_TXSTAT_RX_XOFFED 0x00000001 +#define BGE_TXSTAT_SENT_XOFF 0x00000002 +#define BGE_TXSTAT_SENT_XON 0x00000004 +#define BGE_TXSTAT_LINK_UP 0x00000008 +#define BGE_TXSTAT_ODI_UFLOW 0x00000010 +#define BGE_TXSTAT_ODI_OFLOW 0x00000020 + +/* Transmit MAC lengths register */ +#define BGE_TXLEN_SLOTTIME 0x000000FF +#define BGE_TXLEN_IPG 0x00000F00 +#define BGE_TXLEN_CRS 0x00003000 + +/* Receive MAC mode register */ +#define BGE_RXMODE_RESET 0x00000001 +#define BGE_RXMODE_ENABLE 0x00000002 +#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 +#define BGE_RXMODE_RX_GIANTS 0x00000020 +#define BGE_RXMODE_RX_RUNTS 0x00000040 +#define BGE_RXMODE_8022_LENCHECK 0x00000080 +#define BGE_RXMODE_RX_PROMISC 0x00000100 +#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 +#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 + +/* Receive MAC status register */ +#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 +#define BGE_RXSTAT_RCVD_XOFF 0x00000002 +#define BGE_RXSTAT_RCVD_XON 0x00000004 + +/* Receive Rules Control register */ +#define BGE_RXRULECTL_OFFSET 0x000000FF +#define BGE_RXRULECTL_CLASS 0x00001F00 +#define BGE_RXRULECTL_HDRTYPE 0x0000E000 +#define BGE_RXRULECTL_COMPARE_OP 0x00030000 +#define BGE_RXRULECTL_MAP 0x01000000 +#define BGE_RXRULECTL_DISCARD 0x02000000 +#define BGE_RXRULECTL_MASK 0x04000000 +#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 +#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 +#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 +#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 + +/* Receive Rules Mask register */ +#define BGE_RXRULEMASK_VALUE 0x0000FFFF +#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 + +/* SERDES configuration register */ +#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ +#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ +#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ +#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ +#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ +#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ +#define BGE_SERDESCFG_TXMODE 0x00001000 +#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ +#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ +#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ +#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ +#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ +#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ +#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ +#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ +#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ + +/* SERDES status register */ +#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ +#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ + +/* SGDIG config (not documented) */ +#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 +#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 +#define BGE_SGDIGCFG_SEND 0x40000000 +#define BGE_SGDIGCFG_AUTO 0x80000000 + +/* SGDIG status (not documented) */ +#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 +#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 +#define BGE_SGDIGSTS_DONE 0x00000002 + + +/* MI communication register */ +#define BGE_MICOMM_DATA 0x0000FFFF +#define BGE_MICOMM_REG 0x001F0000 +#define BGE_MICOMM_PHY 0x03E00000 +#define BGE_MICOMM_CMD 0x0C000000 +#define BGE_MICOMM_READFAIL 0x10000000 +#define BGE_MICOMM_BUSY 0x20000000 + +#define BGE_MIREG(x) ((x & 0x1F) << 16) +#define BGE_MIPHY(x) ((x & 0x1F) << 21) +#define BGE_MICMD_WRITE 0x04000000 +#define BGE_MICMD_READ 0x08000000 + +/* MI status register */ +#define BGE_MISTS_LINK 0x00000001 +#define BGE_MISTS_10MBPS 0x00000002 + +#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 +#define BGE_MIMODE_AUTOPOLL 0x00000010 +#define BGE_MIMODE_CLKCNT 0x001F0000 + + +/* + * Send data initiator control registers. + */ +#define BGE_SDI_MODE 0x0C00 +#define BGE_SDI_STATUS 0x0C04 +#define BGE_SDI_STATS_CTL 0x0C08 +#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C +#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 +#define BGE_LOCSTATS_COS0 0x0C80 +#define BGE_LOCSTATS_COS1 0x0C84 +#define BGE_LOCSTATS_COS2 0x0C88 +#define BGE_LOCSTATS_COS3 0x0C8C +#define BGE_LOCSTATS_COS4 0x0C90 +#define BGE_LOCSTATS_COS5 0x0C84 +#define BGE_LOCSTATS_COS6 0x0C98 +#define BGE_LOCSTATS_COS7 0x0C9C +#define BGE_LOCSTATS_COS8 0x0CA0 +#define BGE_LOCSTATS_COS9 0x0CA4 +#define BGE_LOCSTATS_COS10 0x0CA8 +#define BGE_LOCSTATS_COS11 0x0CAC +#define BGE_LOCSTATS_COS12 0x0CB0 +#define BGE_LOCSTATS_COS13 0x0CB4 +#define BGE_LOCSTATS_COS14 0x0CB8 +#define BGE_LOCSTATS_COS15 0x0CBC +#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 +#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 +#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 +#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC +#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 +#define BGE_LOCSTATS_IRQS 0x0CD4 +#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 +#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC + +/* Send Data Initiator mode register */ +#define BGE_SDIMODE_RESET 0x00000001 +#define BGE_SDIMODE_ENABLE 0x00000002 +#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 + +/* Send Data Initiator stats register */ +#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 + +/* Send Data Initiator stats control register */ +#define BGE_SDISTATSCTL_ENABLE 0x00000001 +#define BGE_SDISTATSCTL_FASTER 0x00000002 +#define BGE_SDISTATSCTL_CLEAR 0x00000004 +#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 +#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 + +/* + * Send Data Completion Control registers + */ +#define BGE_SDC_MODE 0x1000 +#define BGE_SDC_STATUS 0x1004 + +/* Send Data completion mode register */ +#define BGE_SDCMODE_RESET 0x00000001 +#define BGE_SDCMODE_ENABLE 0x00000002 +#define BGE_SDCMODE_ATTN 0x00000004 + +/* Send Data completion status register */ +#define BGE_SDCSTAT_ATTN 0x00000004 + +/* + * Send BD Ring Selector Control registers + */ +#define BGE_SRS_MODE 0x1400 +#define BGE_SRS_STATUS 0x1404 +#define BGE_SRS_HWDIAG 0x1408 +#define BGE_SRS_LOC_NIC_CONS0 0x1440 +#define BGE_SRS_LOC_NIC_CONS1 0x1444 +#define BGE_SRS_LOC_NIC_CONS2 0x1448 +#define BGE_SRS_LOC_NIC_CONS3 0x144C +#define BGE_SRS_LOC_NIC_CONS4 0x1450 +#define BGE_SRS_LOC_NIC_CONS5 0x1454 +#define BGE_SRS_LOC_NIC_CONS6 0x1458 +#define BGE_SRS_LOC_NIC_CONS7 0x145C +#define BGE_SRS_LOC_NIC_CONS8 0x1460 +#define BGE_SRS_LOC_NIC_CONS9 0x1464 +#define BGE_SRS_LOC_NIC_CONS10 0x1468 +#define BGE_SRS_LOC_NIC_CONS11 0x146C +#define BGE_SRS_LOC_NIC_CONS12 0x1470 +#define BGE_SRS_LOC_NIC_CONS13 0x1474 +#define BGE_SRS_LOC_NIC_CONS14 0x1478 +#define BGE_SRS_LOC_NIC_CONS15 0x147C + +/* Send BD Ring Selector Mode register */ +#define BGE_SRSMODE_RESET 0x00000001 +#define BGE_SRSMODE_ENABLE 0x00000002 +#define BGE_SRSMODE_ATTN 0x00000004 + +/* Send BD Ring Selector Status register */ +#define BGE_SRSSTAT_ERROR 0x00000004 + +/* Send BD Ring Selector HW Diagnostics register */ +#define BGE_SRSHWDIAG_STATE 0x0000000F +#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 +#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 +#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 + +/* + * Send BD Initiator Selector Control registers + */ +#define BGE_SBDI_MODE 0x1800 +#define BGE_SBDI_STATUS 0x1804 +#define BGE_SBDI_LOC_NIC_PROD0 0x1808 +#define BGE_SBDI_LOC_NIC_PROD1 0x180C +#define BGE_SBDI_LOC_NIC_PROD2 0x1810 +#define BGE_SBDI_LOC_NIC_PROD3 0x1814 +#define BGE_SBDI_LOC_NIC_PROD4 0x1818 +#define BGE_SBDI_LOC_NIC_PROD5 0x181C +#define BGE_SBDI_LOC_NIC_PROD6 0x1820 +#define BGE_SBDI_LOC_NIC_PROD7 0x1824 +#define BGE_SBDI_LOC_NIC_PROD8 0x1828 +#define BGE_SBDI_LOC_NIC_PROD9 0x182C +#define BGE_SBDI_LOC_NIC_PROD10 0x1830 +#define BGE_SBDI_LOC_NIC_PROD11 0x1834 +#define BGE_SBDI_LOC_NIC_PROD12 0x1838 +#define BGE_SBDI_LOC_NIC_PROD13 0x183C +#define BGE_SBDI_LOC_NIC_PROD14 0x1840 +#define BGE_SBDI_LOC_NIC_PROD15 0x1844 + +/* Send BD Initiator Mode register */ +#define BGE_SBDIMODE_RESET 0x00000001 +#define BGE_SBDIMODE_ENABLE 0x00000002 +#define BGE_SBDIMODE_ATTN 0x00000004 + +/* Send BD Initiator Status register */ +#define BGE_SBDISTAT_ERROR 0x00000004 + +/* + * Send BD Completion Control registers + */ +#define BGE_SBDC_MODE 0x1C00 +#define BGE_SBDC_STATUS 0x1C04 + +/* Send BD Completion Control Mode register */ +#define BGE_SBDCMODE_RESET 0x00000001 +#define BGE_SBDCMODE_ENABLE 0x00000002 +#define BGE_SBDCMODE_ATTN 0x00000004 + +/* Send BD Completion Control Status register */ +#define BGE_SBDCSTAT_ATTN 0x00000004 + +/* + * Receive List Placement Control registers + */ +#define BGE_RXLP_MODE 0x2000 +#define BGE_RXLP_STATUS 0x2004 +#define BGE_RXLP_SEL_LIST_LOCK 0x2008 +#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C +#define BGE_RXLP_CFG 0x2010 +#define BGE_RXLP_STATS_CTL 0x2014 +#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 +#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C +#define BGE_RXLP_HEAD0 0x2100 +#define BGE_RXLP_TAIL0 0x2104 +#define BGE_RXLP_COUNT0 0x2108 +#define BGE_RXLP_HEAD1 0x2110 +#define BGE_RXLP_TAIL1 0x2114 +#define BGE_RXLP_COUNT1 0x2118 +#define BGE_RXLP_HEAD2 0x2120 +#define BGE_RXLP_TAIL2 0x2124 +#define BGE_RXLP_COUNT2 0x2128 +#define BGE_RXLP_HEAD3 0x2130 +#define BGE_RXLP_TAIL3 0x2134 +#define BGE_RXLP_COUNT3 0x2138 +#define BGE_RXLP_HEAD4 0x2140 +#define BGE_RXLP_TAIL4 0x2144 +#define BGE_RXLP_COUNT4 0x2148 +#define BGE_RXLP_HEAD5 0x2150 +#define BGE_RXLP_TAIL5 0x2154 +#define BGE_RXLP_COUNT5 0x2158 +#define BGE_RXLP_HEAD6 0x2160 +#define BGE_RXLP_TAIL6 0x2164 +#define BGE_RXLP_COUNT6 0x2168 +#define BGE_RXLP_HEAD7 0x2170 +#define BGE_RXLP_TAIL7 0x2174 +#define BGE_RXLP_COUNT7 0x2178 +#define BGE_RXLP_HEAD8 0x2180 +#define BGE_RXLP_TAIL8 0x2184 +#define BGE_RXLP_COUNT8 0x2188 +#define BGE_RXLP_HEAD9 0x2190 +#define BGE_RXLP_TAIL9 0x2194 +#define BGE_RXLP_COUNT9 0x2198 +#define BGE_RXLP_HEAD10 0x21A0 +#define BGE_RXLP_TAIL10 0x21A4 +#define BGE_RXLP_COUNT10 0x21A8 +#define BGE_RXLP_HEAD11 0x21B0 +#define BGE_RXLP_TAIL11 0x21B4 +#define BGE_RXLP_COUNT11 0x21B8 +#define BGE_RXLP_HEAD12 0x21C0 +#define BGE_RXLP_TAIL12 0x21C4 +#define BGE_RXLP_COUNT12 0x21C8 +#define BGE_RXLP_HEAD13 0x21D0 +#define BGE_RXLP_TAIL13 0x21D4 +#define BGE_RXLP_COUNT13 0x21D8 +#define BGE_RXLP_HEAD14 0x21E0 +#define BGE_RXLP_TAIL14 0x21E4 +#define BGE_RXLP_COUNT14 0x21E8 +#define BGE_RXLP_HEAD15 0x21F0 +#define BGE_RXLP_TAIL15 0x21F4 +#define BGE_RXLP_COUNT15 0x21F8 +#define BGE_RXLP_LOCSTAT_COS0 0x2200 +#define BGE_RXLP_LOCSTAT_COS1 0x2204 +#define BGE_RXLP_LOCSTAT_COS2 0x2208 +#define BGE_RXLP_LOCSTAT_COS3 0x220C +#define BGE_RXLP_LOCSTAT_COS4 0x2210 +#define BGE_RXLP_LOCSTAT_COS5 0x2214 +#define BGE_RXLP_LOCSTAT_COS6 0x2218 +#define BGE_RXLP_LOCSTAT_COS7 0x221C +#define BGE_RXLP_LOCSTAT_COS8 0x2220 +#define BGE_RXLP_LOCSTAT_COS9 0x2224 +#define BGE_RXLP_LOCSTAT_COS10 0x2228 +#define BGE_RXLP_LOCSTAT_COS11 0x222C +#define BGE_RXLP_LOCSTAT_COS12 0x2230 +#define BGE_RXLP_LOCSTAT_COS13 0x2234 +#define BGE_RXLP_LOCSTAT_COS14 0x2238 +#define BGE_RXLP_LOCSTAT_COS15 0x223C +#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 +#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 +#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 +#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C +#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 +#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 +#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 + + +/* Receive List Placement mode register */ +#define BGE_RXLPMODE_RESET 0x00000001 +#define BGE_RXLPMODE_ENABLE 0x00000002 +#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 +#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 +#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 + +/* Receive List Placement Status register */ +#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 +#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 +#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 + +/* + * Receive Data and Receive BD Initiator Control Registers + */ +#define BGE_RDBDI_MODE 0x2400 +#define BGE_RDBDI_STATUS 0x2404 +#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 +#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 +#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 +#define BGE_RX_JUMBO_RCB_NICADDR 0x244C +#define BGE_RX_STD_RCB_HADDR_HI 0x2450 +#define BGE_RX_STD_RCB_HADDR_LO 0x2454 +#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 +#define BGE_RX_STD_RCB_NICADDR 0x245C +#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 +#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 +#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 +#define BGE_RX_MINI_RCB_NICADDR 0x246C +#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 +#define BGE_RDBDI_STD_RX_CONS 0x2474 +#define BGE_RDBDI_MINI_RX_CONS 0x2478 +#define BGE_RDBDI_RETURN_PROD0 0x2480 +#define BGE_RDBDI_RETURN_PROD1 0x2484 +#define BGE_RDBDI_RETURN_PROD2 0x2488 +#define BGE_RDBDI_RETURN_PROD3 0x248C +#define BGE_RDBDI_RETURN_PROD4 0x2490 +#define BGE_RDBDI_RETURN_PROD5 0x2494 +#define BGE_RDBDI_RETURN_PROD6 0x2498 +#define BGE_RDBDI_RETURN_PROD7 0x249C +#define BGE_RDBDI_RETURN_PROD8 0x24A0 +#define BGE_RDBDI_RETURN_PROD9 0x24A4 +#define BGE_RDBDI_RETURN_PROD10 0x24A8 +#define BGE_RDBDI_RETURN_PROD11 0x24AC +#define BGE_RDBDI_RETURN_PROD12 0x24B0 +#define BGE_RDBDI_RETURN_PROD13 0x24B4 +#define BGE_RDBDI_RETURN_PROD14 0x24B8 +#define BGE_RDBDI_RETURN_PROD15 0x24BC +#define BGE_RDBDI_HWDIAG 0x24C0 + + +/* Receive Data and Receive BD Initiator Mode register */ +#define BGE_RDBDIMODE_RESET 0x00000001 +#define BGE_RDBDIMODE_ENABLE 0x00000002 +#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 +#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 +#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 + +/* Receive Data and Receive BD Initiator Status register */ +#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 +#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 +#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 + + +/* + * Receive Data Completion Control registers + */ +#define BGE_RDC_MODE 0x2800 + +/* Receive Data Completion Mode register */ +#define BGE_RDCMODE_RESET 0x00000001 +#define BGE_RDCMODE_ENABLE 0x00000002 +#define BGE_RDCMODE_ATTN 0x00000004 + +/* + * Receive BD Initiator Control registers + */ +#define BGE_RBDI_MODE 0x2C00 +#define BGE_RBDI_STATUS 0x2C04 +#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 +#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C +#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 +#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 +#define BGE_RBDI_STD_REPL_THRESH 0x2C18 +#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C + +/* Receive BD Initiator Mode register */ +#define BGE_RBDIMODE_RESET 0x00000001 +#define BGE_RBDIMODE_ENABLE 0x00000002 +#define BGE_RBDIMODE_ATTN 0x00000004 + +/* Receive BD Initiator Status register */ +#define BGE_RBDISTAT_ATTN 0x00000004 + +/* + * Receive BD Completion Control registers + */ +#define BGE_RBDC_MODE 0x3000 +#define BGE_RBDC_STATUS 0x3004 +#define BGE_RBDC_JUMBO_BD_PROD 0x3008 +#define BGE_RBDC_STD_BD_PROD 0x300C +#define BGE_RBDC_MINI_BD_PROD 0x3010 + +/* Receive BD completion mode register */ +#define BGE_RBDCMODE_RESET 0x00000001 +#define BGE_RBDCMODE_ENABLE 0x00000002 +#define BGE_RBDCMODE_ATTN 0x00000004 + +/* Receive BD completion status register */ +#define BGE_RBDCSTAT_ERROR 0x00000004 + +/* + * Receive List Selector Control registers + */ +#define BGE_RXLS_MODE 0x3400 +#define BGE_RXLS_STATUS 0x3404 + +/* Receive List Selector Mode register */ +#define BGE_RXLSMODE_RESET 0x00000001 +#define BGE_RXLSMODE_ENABLE 0x00000002 +#define BGE_RXLSMODE_ATTN 0x00000004 + +/* Receive List Selector Status register */ +#define BGE_RXLSSTAT_ERROR 0x00000004 + +/* + * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) + */ +#define BGE_MBCF_MODE 0x3800 +#define BGE_MBCF_STATUS 0x3804 + +/* Mbuf Cluster Free mode register */ +#define BGE_MBCFMODE_RESET 0x00000001 +#define BGE_MBCFMODE_ENABLE 0x00000002 +#define BGE_MBCFMODE_ATTN 0x00000004 + +/* Mbuf Cluster Free status register */ +#define BGE_MBCFSTAT_ERROR 0x00000004 + +/* + * Host Coalescing Control registers + */ +#define BGE_HCC_MODE 0x3C00 +#define BGE_HCC_STATUS 0x3C04 +#define BGE_HCC_RX_COAL_TICKS 0x3C08 +#define BGE_HCC_TX_COAL_TICKS 0x3C0C +#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 +#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 +#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ +#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ +#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ +#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ +#define BGE_HCC_STATS_TICKS 0x3C28 +#define BGE_HCC_STATS_ADDR_HI 0x3C30 +#define BGE_HCC_STATS_ADDR_LO 0x3C34 +#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 +#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C +#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ +#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ +#define BGE_FLOW_ATTN 0x3C48 +#define BGE_HCC_JUMBO_BD_CONS 0x3C50 +#define BGE_HCC_STD_BD_CONS 0x3C54 +#define BGE_HCC_MINI_BD_CONS 0x3C58 +#define BGE_HCC_RX_RETURN_PROD0 0x3C80 +#define BGE_HCC_RX_RETURN_PROD1 0x3C84 +#define BGE_HCC_RX_RETURN_PROD2 0x3C88 +#define BGE_HCC_RX_RETURN_PROD3 0x3C8C +#define BGE_HCC_RX_RETURN_PROD4 0x3C90 +#define BGE_HCC_RX_RETURN_PROD5 0x3C94 +#define BGE_HCC_RX_RETURN_PROD6 0x3C98 +#define BGE_HCC_RX_RETURN_PROD7 0x3C9C +#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 +#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 +#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 +#define BGE_HCC_RX_RETURN_PROD11 0x3CAC +#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 +#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 +#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 +#define BGE_HCC_RX_RETURN_PROD15 0x3CBC +#define BGE_HCC_TX_BD_CONS0 0x3CC0 +#define BGE_HCC_TX_BD_CONS1 0x3CC4 +#define BGE_HCC_TX_BD_CONS2 0x3CC8 +#define BGE_HCC_TX_BD_CONS3 0x3CCC +#define BGE_HCC_TX_BD_CONS4 0x3CD0 +#define BGE_HCC_TX_BD_CONS5 0x3CD4 +#define BGE_HCC_TX_BD_CONS6 0x3CD8 +#define BGE_HCC_TX_BD_CONS7 0x3CDC +#define BGE_HCC_TX_BD_CONS8 0x3CE0 +#define BGE_HCC_TX_BD_CONS9 0x3CE4 +#define BGE_HCC_TX_BD_CONS10 0x3CE8 +#define BGE_HCC_TX_BD_CONS11 0x3CEC +#define BGE_HCC_TX_BD_CONS12 0x3CF0 +#define BGE_HCC_TX_BD_CONS13 0x3CF4 +#define BGE_HCC_TX_BD_CONS14 0x3CF8 +#define BGE_HCC_TX_BD_CONS15 0x3CFC + + +/* Host coalescing mode register */ +#define BGE_HCCMODE_RESET 0x00000001 +#define BGE_HCCMODE_ENABLE 0x00000002 +#define BGE_HCCMODE_ATTN 0x00000004 +#define BGE_HCCMODE_COAL_NOW 0x00000008 +#define BGE_HCCMODE_MSI_BITS 0x00000070 +#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 + +#define BGE_STATBLKSZ_FULL 0x00000000 +#define BGE_STATBLKSZ_64BYTE 0x00000080 +#define BGE_STATBLKSZ_32BYTE 0x00000100 + +/* Host coalescing status register */ +#define BGE_HCCSTAT_ERROR 0x00000004 + +/* Flow attention register */ +#define BGE_FLOWATTN_MB_LOWAT 0x00000040 +#define BGE_FLOWATTN_MEMARB 0x00000080 +#define BGE_FLOWATTN_HOSTCOAL 0x00008000 +#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 +#define BGE_FLOWATTN_RCB_INVAL 0x00020000 +#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 +#define BGE_FLOWATTN_RDBDI 0x00080000 +#define BGE_FLOWATTN_RXLS 0x00100000 +#define BGE_FLOWATTN_RXLP 0x00200000 +#define BGE_FLOWATTN_RBDC 0x00400000 +#define BGE_FLOWATTN_RBDI 0x00800000 +#define BGE_FLOWATTN_SDC 0x08000000 +#define BGE_FLOWATTN_SDI 0x10000000 +#define BGE_FLOWATTN_SRS 0x20000000 +#define BGE_FLOWATTN_SBDC 0x40000000 +#define BGE_FLOWATTN_SBDI 0x80000000 + +/* + * Memory arbiter registers + */ +#define BGE_MARB_MODE 0x4000 +#define BGE_MARB_STATUS 0x4004 +#define BGE_MARB_TRAPADDR_HI 0x4008 +#define BGE_MARB_TRAPADDR_LO 0x400C + +/* Memory arbiter mode register */ +#define BGE_MARBMODE_RESET 0x00000001 +#define BGE_MARBMODE_ENABLE 0x00000002 +#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 +#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 +#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 +#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 +#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 +#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 +#define BGE_MARBMODE_PCI_TRAP 0x00000100 +#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 +#define BGE_MARBMODE_RXQ_TRAP 0x00000400 +#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 +#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 +#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 +#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 +#define BGE_MARBMODE_MBUF_TRAP 0x00008000 +#define BGE_MARBMODE_TXDI_TRAP 0x00010000 +#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 +#define BGE_MARBMODE_TXBD_TRAP 0x00040000 +#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 +#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 +#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 +#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 +#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 +#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 +#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 + +/* Memory arbiter status register */ +#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 +#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 +#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 +#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 +#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 +#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 +#define BGE_MARBSTAT_PCI_TRAP 0x00000100 +#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 +#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 +#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 +#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 +#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 +#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 +#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 +#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 +#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 +#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 +#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 +#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 +#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 +#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 +#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 +#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 +#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 + +/* + * Buffer manager control registers + */ +#define BGE_BMAN_MODE 0x4400 +#define BGE_BMAN_STATUS 0x4404 +#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 +#define BGE_BMAN_MBUFPOOL_LEN 0x440C +#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 +#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 +#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 +#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C +#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 +#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 +#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 +#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C +#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 +#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 +#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 +#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C +#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 +#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 +#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 +#define BGE_BMAN_HWDIAG_1 0x444C +#define BGE_BMAN_HWDIAG_2 0x4450 +#define BGE_BMAN_HWDIAG_3 0x4454 + +/* Buffer manager mode register */ +#define BGE_BMANMODE_RESET 0x00000001 +#define BGE_BMANMODE_ENABLE 0x00000002 +#define BGE_BMANMODE_ATTN 0x00000004 +#define BGE_BMANMODE_TESTMODE 0x00000008 +#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 + +/* Buffer manager status register */ +#define BGE_BMANSTAT_ERRO 0x00000004 +#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 + + +/* + * Read DMA Control registers + */ +#define BGE_RDMA_MODE 0x4800 +#define BGE_RDMA_STATUS 0x4804 + +/* Read DMA mode register */ +#define BGE_RDMAMODE_RESET 0x00000001 +#define BGE_RDMAMODE_ENABLE 0x00000002 +#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 +#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC + +/* Read DMA status register */ +#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 + +/* + * Write DMA control registers + */ +#define BGE_WDMA_MODE 0x4C00 +#define BGE_WDMA_STATUS 0x4C04 + +/* Write DMA mode register */ +#define BGE_WDMAMODE_RESET 0x00000001 +#define BGE_WDMAMODE_ENABLE 0x00000002 +#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 +#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC + +/* Write DMA status register */ +#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 +#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 +#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 +#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 +#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 + + +/* + * RX CPU registers + */ +#define BGE_RXCPU_MODE 0x5000 +#define BGE_RXCPU_STATUS 0x5004 +#define BGE_RXCPU_PC 0x501C + +/* RX CPU mode register */ +#define BGE_RXCPUMODE_RESET 0x00000001 +#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 +#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 +#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 +#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 +#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 +#define BGE_RXCPUMODE_ROMFAIL 0x00000040 +#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 +#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 +#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 +#define BGE_RXCPUMODE_HALTCPU 0x00000400 +#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 +#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 +#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 + +/* RX CPU status register */ +#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 +#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 +#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 +#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 +#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 +#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 +#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 +#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 +#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 +#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 +#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 +#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 +#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 +#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 +#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 +#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 +#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 + + +/* + * TX CPU registers + */ +#define BGE_TXCPU_MODE 0x5400 +#define BGE_TXCPU_STATUS 0x5404 +#define BGE_TXCPU_PC 0x541C + +/* TX CPU mode register */ +#define BGE_TXCPUMODE_RESET 0x00000001 +#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 +#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 +#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 +#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 +#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 +#define BGE_TXCPUMODE_ROMFAIL 0x00000040 +#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 +#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 +#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 +#define BGE_TXCPUMODE_HALTCPU 0x00000400 +#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 +#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 + +/* TX CPU status register */ +#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 +#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 +#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 +#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 +#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 +#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 +#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 +#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 +#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 +#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 +#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 +#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 +#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 +#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 +#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 +#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 +#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 + + +/* + * Low priority mailbox registers + */ +#define BGE_LPMBX_IRQ0_HI 0x5800 +#define BGE_LPMBX_IRQ0_LO 0x5804 +#define BGE_LPMBX_IRQ1_HI 0x5808 +#define BGE_LPMBX_IRQ1_LO 0x580C +#define BGE_LPMBX_IRQ2_HI 0x5810 +#define BGE_LPMBX_IRQ2_LO 0x5814 +#define BGE_LPMBX_IRQ3_HI 0x5818 +#define BGE_LPMBX_IRQ3_LO 0x581C +#define BGE_LPMBX_GEN0_HI 0x5820 +#define BGE_LPMBX_GEN0_LO 0x5824 +#define BGE_LPMBX_GEN1_HI 0x5828 +#define BGE_LPMBX_GEN1_LO 0x582C +#define BGE_LPMBX_GEN2_HI 0x5830 +#define BGE_LPMBX_GEN2_LO 0x5834 +#define BGE_LPMBX_GEN3_HI 0x5828 +#define BGE_LPMBX_GEN3_LO 0x582C +#define BGE_LPMBX_GEN4_HI 0x5840 +#define BGE_LPMBX_GEN4_LO 0x5844 +#define BGE_LPMBX_GEN5_HI 0x5848 +#define BGE_LPMBX_GEN5_LO 0x584C +#define BGE_LPMBX_GEN6_HI 0x5850 +#define BGE_LPMBX_GEN6_LO 0x5854 +#define BGE_LPMBX_GEN7_HI 0x5858 +#define BGE_LPMBX_GEN7_LO 0x585C +#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 +#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 +#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 +#define BGE_LPMBX_RX_STD_PROD_LO 0x586C +#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 +#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 +#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 +#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C +#define BGE_LPMBX_RX_CONS0_HI 0x5880 +#define BGE_LPMBX_RX_CONS0_LO 0x5884 +#define BGE_LPMBX_RX_CONS1_HI 0x5888 +#define BGE_LPMBX_RX_CONS1_LO 0x588C +#define BGE_LPMBX_RX_CONS2_HI 0x5890 +#define BGE_LPMBX_RX_CONS2_LO 0x5894 +#define BGE_LPMBX_RX_CONS3_HI 0x5898 +#define BGE_LPMBX_RX_CONS3_LO 0x589C +#define BGE_LPMBX_RX_CONS4_HI 0x58A0 +#define BGE_LPMBX_RX_CONS4_LO 0x58A4 +#define BGE_LPMBX_RX_CONS5_HI 0x58A8 +#define BGE_LPMBX_RX_CONS5_LO 0x58AC +#define BGE_LPMBX_RX_CONS6_HI 0x58B0 +#define BGE_LPMBX_RX_CONS6_LO 0x58B4 +#define BGE_LPMBX_RX_CONS7_HI 0x58B8 +#define BGE_LPMBX_RX_CONS7_LO 0x58BC +#define BGE_LPMBX_RX_CONS8_HI 0x58C0 +#define BGE_LPMBX_RX_CONS8_LO 0x58C4 +#define BGE_LPMBX_RX_CONS9_HI 0x58C8 +#define BGE_LPMBX_RX_CONS9_LO 0x58CC +#define BGE_LPMBX_RX_CONS10_HI 0x58D0 +#define BGE_LPMBX_RX_CONS10_LO 0x58D4 +#define BGE_LPMBX_RX_CONS11_HI 0x58D8 +#define BGE_LPMBX_RX_CONS11_LO 0x58DC +#define BGE_LPMBX_RX_CONS12_HI 0x58E0 +#define BGE_LPMBX_RX_CONS12_LO 0x58E4 +#define BGE_LPMBX_RX_CONS13_HI 0x58E8 +#define BGE_LPMBX_RX_CONS13_LO 0x58EC +#define BGE_LPMBX_RX_CONS14_HI 0x58F0 +#define BGE_LPMBX_RX_CONS14_LO 0x58F4 +#define BGE_LPMBX_RX_CONS15_HI 0x58F8 +#define BGE_LPMBX_RX_CONS15_LO 0x58FC +#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 +#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 +#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 +#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C +#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 +#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 +#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 +#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C +#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 +#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 +#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 +#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C +#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 +#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 +#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 +#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C +#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 +#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 +#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 +#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C +#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 +#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 +#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 +#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C +#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 +#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 +#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 +#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C +#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 +#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 +#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 +#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C +#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 +#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 +#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 +#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C +#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 +#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 +#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 +#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C +#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 +#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 +#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 +#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC +#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 +#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 +#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 +#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC +#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 +#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 +#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 +#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC +#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 +#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 +#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 +#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC +#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 +#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 +#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 +#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC +#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 +#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 +#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 +#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC + +/* + * Flow throw Queue reset register + */ +#define BGE_FTQ_RESET 0x5C00 + +#define BGE_FTQRESET_DMAREAD 0x00000002 +#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 +#define BGE_FTQRESET_DMADONE 0x00000010 +#define BGE_FTQRESET_SBDC 0x00000020 +#define BGE_FTQRESET_SDI 0x00000040 +#define BGE_FTQRESET_WDMA 0x00000080 +#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 +#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 +#define BGE_FTQRESET_SDC 0x00000400 +#define BGE_FTQRESET_HCC 0x00000800 +#define BGE_FTQRESET_TXFIFO 0x00001000 +#define BGE_FTQRESET_MBC 0x00002000 +#define BGE_FTQRESET_RBDC 0x00004000 +#define BGE_FTQRESET_RXLP 0x00008000 +#define BGE_FTQRESET_RDBDI 0x00010000 +#define BGE_FTQRESET_RDC 0x00020000 +#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 + +/* + * Message Signaled Interrupt registers + */ +#define BGE_MSI_MODE 0x6000 +#define BGE_MSI_STATUS 0x6004 +#define BGE_MSI_FIFOACCESS 0x6008 + +/* MSI mode register */ +#define BGE_MSIMODE_RESET 0x00000001 +#define BGE_MSIMODE_ENABLE 0x00000002 +#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 +#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 +#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 + +/* MSI status register */ +#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 +#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 +#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 +#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 +#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 + + +/* + * DMA Completion registers + */ +#define BGE_DMAC_MODE 0x6400 + +/* DMA Completion mode register */ +#define BGE_DMACMODE_RESET 0x00000001 +#define BGE_DMACMODE_ENABLE 0x00000002 + + +/* + * General control registers. + */ +#define BGE_MODE_CTL 0x6800 +#define BGE_MISC_CFG 0x6804 +#define BGE_MISC_LOCAL_CTL 0x6808 +#define BGE_CPU_EVENT 0x6810 +#define BGE_EE_ADDR 0x6838 +#define BGE_EE_DATA 0x683C +#define BGE_EE_CTL 0x6840 +#define BGE_MDI_CTL 0x6844 +#define BGE_EE_DELAY 0x6848 +#define BGE_FASTBOOT_PC 0x6894 + +/* Mode control register */ +#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 +#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 +#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 +#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 +#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 +#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 +#define BGE_MODECTL_NO_RX_CRC 0x00000400 +#define BGE_MODECTL_RX_BADFRAMES 0x00000800 +#define BGE_MODECTL_NO_TX_INTR 0x00002000 +#define BGE_MODECTL_NO_RX_INTR 0x00004000 +#define BGE_MODECTL_FORCE_PCI32 0x00008000 +#define BGE_MODECTL_STACKUP 0x00010000 +#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 +#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 +#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 +#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 +#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 +#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 +#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 +#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 +#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 +#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 + +/* Misc. config register */ +#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 +#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE + +#define BGE_32BITTIME_66MHZ (0x41 << 1) + +/* Misc. Local Control */ +#define BGE_MLC_INTR_STATE 0x00000001 +#define BGE_MLC_INTR_CLR 0x00000002 +#define BGE_MLC_INTR_SET 0x00000004 +#define BGE_MLC_INTR_ONATTN 0x00000008 +#define BGE_MLC_MISCIO_IN0 0x00000100 +#define BGE_MLC_MISCIO_IN1 0x00000200 +#define BGE_MLC_MISCIO_IN2 0x00000400 +#define BGE_MLC_MISCIO_OUTEN0 0x00000800 +#define BGE_MLC_MISCIO_OUTEN1 0x00001000 +#define BGE_MLC_MISCIO_OUTEN2 0x00002000 +#define BGE_MLC_MISCIO_OUT0 0x00004000 +#define BGE_MLC_MISCIO_OUT1 0x00008000 +#define BGE_MLC_MISCIO_OUT2 0x00010000 +#define BGE_MLC_EXTRAM_ENB 0x00020000 +#define BGE_MLC_SRAM_SIZE 0x001C0000 +#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ +#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ +#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 +#define BGE_MLC_AUTO_EEPROM 0x01000000 + +#define BGE_SSRAMSIZE_256KB 0x00000000 +#define BGE_SSRAMSIZE_512KB 0x00040000 +#define BGE_SSRAMSIZE_1MB 0x00080000 +#define BGE_SSRAMSIZE_2MB 0x000C0000 +#define BGE_SSRAMSIZE_4MB 0x00100000 +#define BGE_SSRAMSIZE_8MB 0x00140000 +#define BGE_SSRAMSIZE_16M 0x00180000 + +/* EEPROM address register */ +#define BGE_EEADDR_ADDRESS 0x0000FFFC +#define BGE_EEADDR_HALFCLK 0x01FF0000 +#define BGE_EEADDR_START 0x02000000 +#define BGE_EEADDR_DEVID 0x1C000000 +#define BGE_EEADDR_RESET 0x20000000 +#define BGE_EEADDR_DONE 0x40000000 +#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ + +#define BGE_EEDEVID(x) ((x & 7) << 26) +#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) +#define BGE_HALFCLK_384SCL 0x60 +#define BGE_EE_READCMD \ + (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ + BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) +#define BGE_EE_WRCMD \ + (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ + BGE_EEADDR_START|BGE_EEADDR_DONE) + +/* EEPROM Control register */ +#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 +#define BGE_EECTL_CLKOUT 0x00000002 +#define BGE_EECTL_CLKIN 0x00000004 +#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 +#define BGE_EECTL_DATAOUT 0x00000010 +#define BGE_EECTL_DATAIN 0x00000020 + +/* MDI (MII/GMII) access register */ +#define BGE_MDI_DATA 0x00000001 +#define BGE_MDI_DIR 0x00000002 +#define BGE_MDI_SEL 0x00000004 +#define BGE_MDI_CLK 0x00000008 + +#define BGE_MEMWIN_START 0x00008000 +#define BGE_MEMWIN_END 0x0000FFFF + + +#define BGE_MEMWIN_READ(sc, x, val) \ + do { \ + pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ + (0xFFFF0000 & x), 4); \ + val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ + } while(0) + +#define BGE_MEMWIN_WRITE(sc, x, val) \ + do { \ + pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ + (0xFFFF0000 & x), 4); \ + CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ + } while(0) + +/* + * This magic number is written to the firmware mailbox at 0xb50 + * before a software reset is issued. After the internal firmware + * has completed its initialization it will write the opposite of + * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the + * driver to synchronize with the firmware. + */ +#define BGE_MAGIC_NUMBER 0x4B657654 + +typedef struct { + uint32_t bge_addr_hi; + uint32_t bge_addr_lo; +} bge_hostaddr; + +#define BGE_HOSTADDR(x, y) \ + do { \ + (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ + (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ + } while(0) + +#define BGE_ADDR_LO(y) \ + ((uint64_t) (y) & 0xFFFFFFFF) +#define BGE_ADDR_HI(y) \ + ((uint64_t) (y) >> 32) + +/* Ring control block structure */ +struct bge_rcb { + bge_hostaddr bge_hostaddr; + uint32_t bge_maxlen_flags; + uint32_t bge_nicaddr; +}; + +#define RCB_WRITE_4(sc, rcb, offset, val) \ + bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ + rcb + offsetof(struct bge_rcb, offset), val) +#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) + +#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 +#define BGE_RCB_FLAG_RING_DISABLED 0x0002 + +struct bge_tx_bd { + bge_hostaddr bge_addr; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_flags; + uint16_t bge_len; + uint16_t bge_vlan_tag; + uint16_t bge_rsvd; +#else + uint16_t bge_len; + uint16_t bge_flags; + uint16_t bge_rsvd; + uint16_t bge_vlan_tag; +#endif +}; + +#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 +#define BGE_TXBDFLAG_IP_CSUM 0x0002 +#define BGE_TXBDFLAG_END 0x0004 +#define BGE_TXBDFLAG_IP_FRAG 0x0008 +#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 +#define BGE_TXBDFLAG_VLAN_TAG 0x0040 +#define BGE_TXBDFLAG_COAL_NOW 0x0080 +#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 +#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 +#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 +#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 +#define BGE_TXBDFLAG_NO_CRC 0x8000 + +#define BGE_NIC_TXRING_ADDR(ringno, size) \ + BGE_SEND_RING_1_TO_4 + \ + ((ringno * sizeof(struct bge_tx_bd) * size) / 4) + +struct bge_rx_bd { + bge_hostaddr bge_addr; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_len; + uint16_t bge_idx; + uint16_t bge_flags; + uint16_t bge_type; + uint16_t bge_tcp_udp_csum; + uint16_t bge_ip_csum; + uint16_t bge_vlan_tag; + uint16_t bge_error_flag; +#else + uint16_t bge_idx; + uint16_t bge_len; + uint16_t bge_type; + uint16_t bge_flags; + uint16_t bge_ip_csum; + uint16_t bge_tcp_udp_csum; + uint16_t bge_error_flag; + uint16_t bge_vlan_tag; +#endif + uint32_t bge_rsvd; + uint32_t bge_opaque; +}; + +struct bge_extrx_bd { + bge_hostaddr bge_addr1; + bge_hostaddr bge_addr2; + bge_hostaddr bge_addr3; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_len2; + uint16_t bge_len1; + uint16_t bge_rsvd1; + uint16_t bge_len3; +#else + uint16_t bge_len1; + uint16_t bge_len2; + uint16_t bge_len3; + uint16_t bge_rsvd1; +#endif + bge_hostaddr bge_addr0; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_len0; + uint16_t bge_idx; + uint16_t bge_flags; + uint16_t bge_type; + uint16_t bge_tcp_udp_csum; + uint16_t bge_ip_csum; + uint16_t bge_vlan_tag; + uint16_t bge_error_flag; +#else + uint16_t bge_idx; + uint16_t bge_len0; + uint16_t bge_type; + uint16_t bge_flags; + uint16_t bge_ip_csum; + uint16_t bge_tcp_udp_csum; + uint16_t bge_error_flag; + uint16_t bge_vlan_tag; +#endif + uint32_t bge_rsvd0; + uint32_t bge_opaque; +}; + +#define BGE_RXBDFLAG_END 0x0004 +#define BGE_RXBDFLAG_JUMBO_RING 0x0020 +#define BGE_RXBDFLAG_VLAN_TAG 0x0040 +#define BGE_RXBDFLAG_ERROR 0x0400 +#define BGE_RXBDFLAG_MINI_RING 0x0800 +#define BGE_RXBDFLAG_IP_CSUM 0x1000 +#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 +#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 + +#define BGE_RXERRFLAG_BAD_CRC 0x0001 +#define BGE_RXERRFLAG_COLL_DETECT 0x0002 +#define BGE_RXERRFLAG_LINK_LOST 0x0004 +#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 +#define BGE_RXERRFLAG_MAC_ABORT 0x0010 +#define BGE_RXERRFLAG_RUNT 0x0020 +#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 +#define BGE_RXERRFLAG_GIANT 0x0080 + +struct bge_sts_idx { +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_rx_prod_idx; + uint16_t bge_tx_cons_idx; +#else + uint16_t bge_tx_cons_idx; + uint16_t bge_rx_prod_idx; +#endif +}; + +struct bge_status_block { + uint32_t bge_status; + uint32_t bge_rsvd0; +#if BYTE_ORDER == LITTLE_ENDIAN + uint16_t bge_rx_jumbo_cons_idx; + uint16_t bge_rx_std_cons_idx; + uint16_t bge_rx_mini_cons_idx; + uint16_t bge_rsvd1; +#else + uint16_t bge_rx_std_cons_idx; + uint16_t bge_rx_jumbo_cons_idx; + uint16_t bge_rsvd1; + uint16_t bge_rx_mini_cons_idx; +#endif + struct bge_sts_idx bge_idx[16]; +}; + +#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx +#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx + +#define BGE_STATFLAG_UPDATED 0x00000001 +#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 +#define BGE_STATFLAG_ERROR 0x00000004 + + +/* + * Broadcom Vendor ID + * (Note: the BCM570x still defaults to the Alteon PCI vendor ID + * even though they're now manufactured by Broadcom) + */ +#define BCOM_VENDORID 0x14E4 +#define BCOM_DEVICEID_BCM5700 0x1644 +#define BCOM_DEVICEID_BCM5701 0x1645 +#define BCOM_DEVICEID_BCM5702 0x1646 +#define BCOM_DEVICEID_BCM5702X 0x16A6 +#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 +#define BCOM_DEVICEID_BCM5703 0x1647 +#define BCOM_DEVICEID_BCM5703X 0x16A7 +#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 +#define BCOM_DEVICEID_BCM5704C 0x1648 +#define BCOM_DEVICEID_BCM5704S 0x16A8 +#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 +#define BCOM_DEVICEID_BCM5705 0x1653 +#define BCOM_DEVICEID_BCM5705K 0x1654 +#define BCOM_DEVICEID_BCM5705F 0x166E +#define BCOM_DEVICEID_BCM5705M 0x165D +#define BCOM_DEVICEID_BCM5705M_ALT 0x165E +#define BCOM_DEVICEID_BCM5714C 0x1668 +#define BCOM_DEVICEID_BCM5714S 0x1669 +#define BCOM_DEVICEID_BCM5715 0x1678 +#define BCOM_DEVICEID_BCM5715S 0x1679 +#define BCOM_DEVICEID_BCM5720 0x1658 +#define BCOM_DEVICEID_BCM5721 0x1659 +#define BCOM_DEVICEID_BCM5750 0x1676 +#define BCOM_DEVICEID_BCM5750M 0x167C +#define BCOM_DEVICEID_BCM5751 0x1677 +#define BCOM_DEVICEID_BCM5751F 0x167E +#define BCOM_DEVICEID_BCM5751M 0x167D +#define BCOM_DEVICEID_BCM5752 0x1600 +#define BCOM_DEVICEID_BCM5752M 0x1601 +#define BCOM_DEVICEID_BCM5753 0x16F7 +#define BCOM_DEVICEID_BCM5753F 0x16FE +#define BCOM_DEVICEID_BCM5753M 0x16FD +#define BCOM_DEVICEID_BCM5754 0x167A +#define BCOM_DEVICEID_BCM5754M 0x1672 +#define BCOM_DEVICEID_BCM5755 0x167B +#define BCOM_DEVICEID_BCM5755M 0x1673 +#define BCOM_DEVICEID_BCM5780 0x166A +#define BCOM_DEVICEID_BCM5780S 0x166B +#define BCOM_DEVICEID_BCM5781 0x16DD +#define BCOM_DEVICEID_BCM5782 0x1696 +#define BCOM_DEVICEID_BCM5786 0x169A +#define BCOM_DEVICEID_BCM5787 0x169B +#define BCOM_DEVICEID_BCM5787M 0x1693 +#define BCOM_DEVICEID_BCM5788 0x169C +#define BCOM_DEVICEID_BCM5789 0x169D +#define BCOM_DEVICEID_BCM5901 0x170D +#define BCOM_DEVICEID_BCM5901A2 0x170E +#define BCOM_DEVICEID_BCM5903M 0x16FF + +/* + * Alteon AceNIC PCI vendor/device ID. + */ +#define ALTEON_VENDORID 0x12AE +#define ALTEON_DEVICEID_ACENIC 0x0001 +#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 +#define ALTEON_DEVICEID_BCM5700 0x0003 +#define ALTEON_DEVICEID_BCM5701 0x0004 + +/* + * 3Com 3c996 PCI vendor/device ID. + */ +#define TC_VENDORID 0x10B7 +#define TC_DEVICEID_3C996 0x0003 + +/* + * SysKonnect PCI vendor ID + */ +#define SK_VENDORID 0x1148 +#define SK_DEVICEID_ALTIMA 0x4400 +#define SK_SUBSYSID_9D21 0x4421 +#define SK_SUBSYSID_9D41 0x4441 + +/* + * Altima PCI vendor/device ID. + */ +#define ALTIMA_VENDORID 0x173b +#define ALTIMA_DEVICE_AC1000 0x03e8 +#define ALTIMA_DEVICE_AC1002 0x03e9 +#define ALTIMA_DEVICE_AC9100 0x03ea + +/* + * Dell PCI vendor ID + */ + +#define DELL_VENDORID 0x1028 + +/* + * Apple PCI vendor ID. + */ +#define APPLE_VENDORID 0x106b +#define APPLE_DEVICE_BCM5701 0x1645 + +/* + * Sun PCI vendor ID + */ +#define SUN_VENDORID 0x108e + +/* + * Offset of MAC address inside EEPROM. + */ +#define BGE_EE_MAC_OFFSET 0x7C +#define BGE_EE_HWCFG_OFFSET 0xC8 + +#define BGE_HWCFG_VOLTAGE 0x00000003 +#define BGE_HWCFG_PHYLED_MODE 0x0000000C +#define BGE_HWCFG_MEDIA 0x00000030 +#define BGE_HWCFG_ASF 0x00000080 + +#define BGE_VOLTAGE_1POINT3 0x00000000 +#define BGE_VOLTAGE_1POINT8 0x00000001 + +#define BGE_PHYLEDMODE_UNSPEC 0x00000000 +#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 +#define BGE_PHYLEDMODE_SINGLELED 0x00000008 + +#define BGE_MEDIA_UNSPEC 0x00000000 +#define BGE_MEDIA_COPPER 0x00000010 +#define BGE_MEDIA_FIBER 0x00000020 + +#define BGE_TICKS_PER_SEC 1000000 + +/* + * Ring size constants. + */ +#define BGE_EVENT_RING_CNT 256 +#define BGE_CMD_RING_CNT 64 +#define BGE_STD_RX_RING_CNT 512 +#define BGE_JUMBO_RX_RING_CNT 256 +#define BGE_MINI_RX_RING_CNT 1024 +#define BGE_RETURN_RING_CNT 1024 + +/* 5705 has smaller return ring size */ + +#define BGE_RETURN_RING_CNT_5705 512 + +/* + * Possible TX ring sizes. + */ +#define BGE_TX_RING_CNT_128 128 +#define BGE_TX_RING_BASE_128 0x3800 + +#define BGE_TX_RING_CNT_256 256 +#define BGE_TX_RING_BASE_256 0x3000 + +#define BGE_TX_RING_CNT_512 512 +#define BGE_TX_RING_BASE_512 0x2000 + +#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 +#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 + +/* + * Tigon III statistics counters. + */ +/* Statistics maintained MAC Receive block. */ +struct bge_rx_mac_stats { + bge_hostaddr ifHCInOctets; + bge_hostaddr Reserved1; + bge_hostaddr etherStatsFragments; + bge_hostaddr ifHCInUcastPkts; + bge_hostaddr ifHCInMulticastPkts; + bge_hostaddr ifHCInBroadcastPkts; + bge_hostaddr dot3StatsFCSErrors; + bge_hostaddr dot3StatsAlignmentErrors; + bge_hostaddr xonPauseFramesReceived; + bge_hostaddr xoffPauseFramesReceived; + bge_hostaddr macControlFramesReceived; + bge_hostaddr xoffStateEntered; + bge_hostaddr dot3StatsFramesTooLong; + bge_hostaddr etherStatsJabbers; + bge_hostaddr etherStatsUndersizePkts; + bge_hostaddr inRangeLengthError; + bge_hostaddr outRangeLengthError; + bge_hostaddr etherStatsPkts64Octets; + bge_hostaddr etherStatsPkts65Octetsto127Octets; + bge_hostaddr etherStatsPkts128Octetsto255Octets; + bge_hostaddr etherStatsPkts256Octetsto511Octets; + bge_hostaddr etherStatsPkts512Octetsto1023Octets; + bge_hostaddr etherStatsPkts1024Octetsto1522Octets; + bge_hostaddr etherStatsPkts1523Octetsto2047Octets; + bge_hostaddr etherStatsPkts2048Octetsto4095Octets; + bge_hostaddr etherStatsPkts4096Octetsto8191Octets; + bge_hostaddr etherStatsPkts8192Octetsto9022Octets; +}; + + +/* Statistics maintained MAC Transmit block. */ +struct bge_tx_mac_stats { + bge_hostaddr ifHCOutOctets; + bge_hostaddr Reserved2; + bge_hostaddr etherStatsCollisions; + bge_hostaddr outXonSent; + bge_hostaddr outXoffSent; + bge_hostaddr flowControlDone; + bge_hostaddr dot3StatsInternalMacTransmitErrors; + bge_hostaddr dot3StatsSingleCollisionFrames; + bge_hostaddr dot3StatsMultipleCollisionFrames; + bge_hostaddr dot3StatsDeferredTransmissions; + bge_hostaddr Reserved3; + bge_hostaddr dot3StatsExcessiveCollisions; + bge_hostaddr dot3StatsLateCollisions; + bge_hostaddr dot3Collided2Times; + bge_hostaddr dot3Collided3Times; + bge_hostaddr dot3Collided4Times; + bge_hostaddr dot3Collided5Times; + bge_hostaddr dot3Collided6Times; + bge_hostaddr dot3Collided7Times; + bge_hostaddr dot3Collided8Times; + bge_hostaddr dot3Collided9Times; + bge_hostaddr dot3Collided10Times; + bge_hostaddr dot3Collided11Times; + bge_hostaddr dot3Collided12Times; + bge_hostaddr dot3Collided13Times; + bge_hostaddr dot3Collided14Times; + bge_hostaddr dot3Collided15Times; + bge_hostaddr ifHCOutUcastPkts; + bge_hostaddr ifHCOutMulticastPkts; + bge_hostaddr ifHCOutBroadcastPkts; + bge_hostaddr dot3StatsCarrierSenseErrors; + bge_hostaddr ifOutDiscards; + bge_hostaddr ifOutErrors; +}; + +/* Stats counters access through registers */ +struct bge_mac_stats_regs { + uint32_t ifHCOutOctets; + uint32_t Reserved0; + uint32_t etherStatsCollisions; + uint32_t outXonSent; + uint32_t outXoffSent; + uint32_t Reserved1; + uint32_t dot3StatsInternalMacTransmitErrors; + uint32_t dot3StatsSingleCollisionFrames; + uint32_t dot3StatsMultipleCollisionFrames; + uint32_t dot3StatsDeferredTransmissions; + uint32_t Reserved2; + uint32_t dot3StatsExcessiveCollisions; + uint32_t dot3StatsLateCollisions; + uint32_t Reserved3[14]; + uint32_t ifHCOutUcastPkts; + uint32_t ifHCOutMulticastPkts; + uint32_t ifHCOutBroadcastPkts; + uint32_t Reserved4[2]; + uint32_t ifHCInOctets; + uint32_t Reserved5; + uint32_t etherStatsFragments; + uint32_t ifHCInUcastPkts; + uint32_t ifHCInMulticastPkts; + uint32_t ifHCInBroadcastPkts; + uint32_t dot3StatsFCSErrors; + uint32_t dot3StatsAlignmentErrors; + uint32_t xonPauseFramesReceived; + uint32_t xoffPauseFramesReceived; + uint32_t macControlFramesReceived; + uint32_t xoffStateEntered; + uint32_t dot3StatsFramesTooLong; + uint32_t etherStatsJabbers; + uint32_t etherStatsUndersizePkts; +}; + +struct bge_stats { + uint8_t Reserved0[256]; + + /* Statistics maintained by Receive MAC. */ + struct bge_rx_mac_stats rxstats; + + bge_hostaddr Unused1[37]; + + /* Statistics maintained by Transmit MAC. */ + struct bge_tx_mac_stats txstats; + + bge_hostaddr Unused2[31]; + + /* Statistics maintained by Receive List Placement. */ + bge_hostaddr COSIfHCInPkts[16]; + bge_hostaddr COSFramesDroppedDueToFilters; + bge_hostaddr nicDmaWriteQueueFull; + bge_hostaddr nicDmaWriteHighPriQueueFull; + bge_hostaddr nicNoMoreRxBDs; + bge_hostaddr ifInDiscards; + bge_hostaddr ifInErrors; + bge_hostaddr nicRecvThresholdHit; + + bge_hostaddr Unused3[9]; + + /* Statistics maintained by Send Data Initiator. */ + bge_hostaddr COSIfHCOutPkts[16]; + bge_hostaddr nicDmaReadQueueFull; + bge_hostaddr nicDmaReadHighPriQueueFull; + bge_hostaddr nicSendDataCompQueueFull; + + /* Statistics maintained by Host Coalescing. */ + bge_hostaddr nicRingSetSendProdIndex; + bge_hostaddr nicRingStatusUpdate; + bge_hostaddr nicInterrupts; + bge_hostaddr nicAvoidedInterrupts; + bge_hostaddr nicSendThresholdHit; + + uint8_t Reserved4[320]; +}; + +/* + * Tigon general information block. This resides in host memory + * and contains the status counters, ring control blocks and + * producer pointers. + */ + +struct bge_gib { + struct bge_stats bge_stats; + struct bge_rcb bge_tx_rcb[16]; + struct bge_rcb bge_std_rx_rcb; + struct bge_rcb bge_jumbo_rx_rcb; + struct bge_rcb bge_mini_rx_rcb; + struct bge_rcb bge_return_rcb; +}; + +#define BGE_FRAMELEN 1518 +#define BGE_MAX_FRAMELEN 1536 +#define BGE_JUMBO_FRAMELEN 9018 +#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) +#define BGE_MIN_FRAMELEN 60 + +/* + * Other utility macros. + */ +#define BGE_INC(x, y) (x) = (x + 1) % y + +/* + * Register access macros. The Tigon always uses memory mapped register + * accesses and all registers must be accessed with 32 bit operations. + */ + +#define CSR_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) + +#define CSR_READ_4(sc, reg) \ + bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) + +#define BGE_SETBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) +#define BGE_CLRBIT(sc, reg, x) \ + CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) + +#define PCI_SETBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) +#define PCI_CLRBIT(dev, reg, x, s) \ + pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) + +/* + * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS + * values are tuneable. They control the actual amount of buffers + * allocated for the standard, mini and jumbo receive rings. + */ + +#define BGE_SSLOTS 256 +#define BGE_MSLOTS 256 +#define BGE_JSLOTS 384 + +#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) +#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ + (BGE_JRAWLEN % sizeof(uint64_t)))) +#define BGE_JPAGESZ PAGE_SIZE +#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) +#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) + +#define BGE_NSEG_JUMBO 4 +#define BGE_NSEG_NEW 32 + +/* + * Ring structures. Most of these reside in host memory and we tell + * the NIC where they are via the ring control blocks. The exceptions + * are the tx and command rings, which live in NIC memory and which + * we access via the shared memory window. + */ + +struct bge_ring_data { + struct bge_rx_bd *bge_rx_std_ring; + bus_addr_t bge_rx_std_ring_paddr; + struct bge_extrx_bd *bge_rx_jumbo_ring; + bus_addr_t bge_rx_jumbo_ring_paddr; + struct bge_rx_bd *bge_rx_return_ring; + bus_addr_t bge_rx_return_ring_paddr; + struct bge_tx_bd *bge_tx_ring; + bus_addr_t bge_tx_ring_paddr; + struct bge_status_block *bge_status_block; + bus_addr_t bge_status_block_paddr; + struct bge_stats *bge_stats; + bus_addr_t bge_stats_paddr; + struct bge_gib bge_info; +}; + +#define BGE_STD_RX_RING_SZ \ + (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) +#define BGE_JUMBO_RX_RING_SZ \ + (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) +#define BGE_TX_RING_SZ \ + (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) +#define BGE_RX_RTN_RING_SZ(x) \ + (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) + +#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) + +#define BGE_STATS_SZ sizeof (struct bge_stats) + +/* + * Mbuf pointers. We need these to keep track of the virtual addresses + * of our mbuf chains since we can only convert from physical to virtual, + * not the other way around. + */ +struct bge_chain_data { + bus_dma_tag_t bge_parent_tag; + bus_dma_tag_t bge_rx_std_ring_tag; + bus_dma_tag_t bge_rx_jumbo_ring_tag; + bus_dma_tag_t bge_rx_return_ring_tag; + bus_dma_tag_t bge_tx_ring_tag; + bus_dma_tag_t bge_status_tag; + bus_dma_tag_t bge_stats_tag; + bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ + bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ + bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; + bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; + bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; + bus_dmamap_t bge_rx_std_ring_map; + bus_dmamap_t bge_rx_jumbo_ring_map; + bus_dmamap_t bge_tx_ring_map; + bus_dmamap_t bge_rx_return_ring_map; + bus_dmamap_t bge_status_map; + bus_dmamap_t bge_stats_map; + struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; + struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; + struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; +}; + +struct bge_dmamap_arg { + struct bge_softc *sc; + bus_addr_t bge_busaddr; + uint16_t bge_flags; + int bge_idx; + int bge_maxsegs; + struct bge_tx_bd *bge_ring; +}; + +#define BGE_HWREV_TIGON 0x01 +#define BGE_HWREV_TIGON_II 0x02 +#define BGE_TIMEOUT 100000 +#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ + +struct bge_bcom_hack { + int reg; + int val; +}; + +#define ASF_ENABLE 1 +#define ASF_NEW_HANDSHAKE 2 +#define ASF_STACKUP 4 + +struct bge_softc { + struct ifnet *bge_ifp; /* interface info */ + device_t bge_dev; + struct mtx bge_mtx; + device_t bge_miibus; + bus_space_handle_t bge_bhandle; + bus_space_tag_t bge_btag; + void *bge_intrhand; + struct resource *bge_irq; + struct resource *bge_res; + struct ifmedia bge_ifmedia; /* TBI media info */ + uint32_t bge_flags; +#define BGE_FLAG_TBI 0x00000001 +#define BGE_FLAG_JUMBO 0x00000002 +#define BGE_FLAG_EEPROM 0x00000004 +#define BGE_FLAG_MSI 0x00000100 +#define BGE_FLAG_PCIX 0x00000200 +#define BGE_FLAG_PCIE 0x00000400 +#define BGE_FLAG_5700_FAMILY 0x00001000 +#define BGE_FLAG_5705_PLUS 0x00002000 +#define BGE_FLAG_5714_FAMILY 0x00004000 +#define BGE_FLAG_575X_PLUS 0x00008000 +#define BGE_FLAG_RX_ALIGNBUG 0x00100000 +#define BGE_FLAG_NO_3LED 0x00200000 +#define BGE_FLAG_ADC_BUG 0x00400000 +#define BGE_FLAG_5704_A0_BUG 0x00800000 +#define BGE_FLAG_JITTER_BUG 0x01000000 +#define BGE_FLAG_BER_BUG 0x02000000 +#define BGE_FLAG_ADJUST_TRIM 0x04000000 +#define BGE_FLAG_CRC_BUG 0x08000000 + uint32_t bge_chipid; + uint8_t bge_asicrev; + uint8_t bge_chiprev; + uint8_t bge_asf_mode; + uint8_t bge_asf_count; + struct bge_ring_data bge_ldata; /* rings */ + struct bge_chain_data bge_cdata; /* mbufs */ + uint16_t bge_tx_saved_considx; + uint16_t bge_rx_saved_considx; + uint16_t bge_ev_saved_considx; + uint16_t bge_return_ring_cnt; + uint16_t bge_std; /* current std ring head */ + uint16_t bge_jumbo; /* current jumo ring head */ + uint32_t bge_stat_ticks; + uint32_t bge_rx_coal_ticks; + uint32_t bge_tx_coal_ticks; + uint32_t bge_tx_prodidx; + uint32_t bge_rx_max_coal_bds; + uint32_t bge_tx_max_coal_bds; + uint32_t bge_tx_buf_ratio; + int bge_if_flags; + int bge_txcnt; + int bge_link; /* link state */ + int bge_link_evt; /* pending link event */ + int bge_timer; + struct callout bge_stat_ch; + uint32_t bge_rx_discards; + uint32_t bge_tx_discards; + uint32_t bge_tx_collisions; +#ifdef DEVICE_POLLING + int rxcycles; +#endif /* DEVICE_POLLING */ +}; + +#define BGE_LOCK_INIT(_sc, _name) \ + mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) +#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) +#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) +#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) +#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/Jamfile b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/Jamfile new file mode 100644 index 0000000000..3b641b9328 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/Jamfile @@ -0,0 +1,15 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network broadcom_bcm570x dev mii ; + +UsePrivateHeaders kernel net ; + +UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ; +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ; + +KernelStaticLibrary broadcom_bcm570x_mii.a + : + ukphy.c + ukphy_subr.c + ; + diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/brgphyreg.h b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/brgphyreg.h new file mode 100644 index 0000000000..87d0a456a9 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/brgphyreg.h @@ -0,0 +1,364 @@ +/*- + * Copyright (c) 2000 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/mii/brgphyreg.h,v 1.10 2007/06/07 02:21:38 davidch Exp $ + */ + +#ifndef _DEV_MII_BRGPHYREG_H_ +#define _DEV_MII_BRGPHYREG_H_ + +/* + * Broadcom BCM5400 registers + */ + +#define BRGPHY_MII_BMCR 0x00 +#define BRGPHY_BMCR_RESET 0x8000 +#define BRGPHY_BMCR_LOOP 0x4000 +#define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */ +#define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ +#define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */ +#define BRGPHY_BMCR_ISO 0x0400 /* Isolate */ +#define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ +#define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */ +#define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */ +#define BRGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ + +#define BRGPHY_S1000 BRGPHY_BMCR_SPD1 /* 1000mbps */ +#define BRGPHY_S100 BRGPHY_BMCR_SPD0 /* 100mpbs */ +#define BRGPHY_S10 0 /* 10mbps */ + +#define BRGPHY_MII_BMSR 0x01 +#define BRGPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ +#define BRGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ +#define BRGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ +#define BRGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ +#define BRGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ +#define BRGPHY_BMSR_LINK 0x0004 /* Link status */ +#define BRGPHY_BMSR_JABBER 0x0002 /* Jabber detected */ +#define BRGPHY_BMSR_EXT 0x0001 /* Extended capability */ + +#define BRGPHY_MII_ANAR 0x04 +#define BRGPHY_ANAR_NP 0x8000 /* Next page */ +#define BRGPHY_ANAR_RF 0x2000 /* Remote fault */ +#define BRGPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ +#define BRGPHY_ANAR_PC 0x0400 /* Pause capable */ +#define BRGPHY_ANAR_SEL 0x001F /* Selector field, 00001=Ethernet */ + +#define BRGPHY_MII_ANLPAR 0x05 +#define BRGPHY_ANLPAR_NP 0x8000 /* Next page */ +#define BRGPHY_ANLPAR_RF 0x2000 /* Remote fault */ +#define BRGPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ +#define BRGPHY_ANLPAR_PC 0x0400 /* Pause capable */ +#define BRGPHY_ANLPAR_SEL 0x001F /* Selector field, 00001=Ethernet */ + +#define BRGPHY_SEL_TYPE 0x0001 /* Ethernet */ + +#define BRGPHY_MII_ANER 0x06 +#define BRGPHY_ANER_PDF 0x0010 /* Parallel detection fault */ +#define BRGPHY_ANER_LPNP 0x0008 /* Link partner can next page */ +#define BRGPHY_ANER_NP 0x0004 /* Local PHY can next page */ +#define BRGPHY_ANER_RX 0x0002 /* Next page received */ +#define BRGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ + +#define BRGPHY_MII_NEXTP 0x07 /* Next page */ + +#define BRGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */ + +#define BRGPHY_MII_1000CTL 0x09 /* 1000baseT control */ +#define BRGPHY_1000CTL_TST 0xE000 /* Test modes */ +#define BRGPHY_1000CTL_MSE 0x1000 /* Master/Slave enable */ +#define BRGPHY_1000CTL_MSC 0x0800 /* Master/Slave configuration */ +#define BRGPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ +#define BRGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ +#define BRGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ + +#define BRGPHY_MII_1000STS 0x0A /* 1000baseT status */ +#define BRGPHY_1000STS_MSF 0x8000 /* Master/slave fault */ +#define BRGPHY_1000STS_MSR 0x4000 /* Master/slave result */ +#define BRGPHY_1000STS_LRS 0x2000 /* Local receiver status */ +#define BRGPHY_1000STS_RRS 0x1000 /* Remote receiver status */ +#define BRGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ +#define BRGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ +#define BRGPHY_1000STS_IEC 0x00FF /* Idle error count */ + +#define BRGPHY_MII_EXTSTS 0x0F /* Extended status */ +#define BRGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ +#define BRGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ +#define BRGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ +#define BRGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ + +#define BRGPHY_MII_PHY_EXTCTL 0x10 /* PHY extended control */ +#define BRGPHY_PHY_EXTCTL_MAC_PHY 0x8000 /* 10BIT/GMI-interface */ +#define BRGPHY_PHY_EXTCTL_DIS_CROSS 0x4000 /* Disable MDI crossover */ +#define BRGPHY_PHY_EXTCTL_TX_DIS 0x2000 /* TX output disabled */ +#define BRGPHY_PHY_EXTCTL_INT_DIS 0x1000 /* Interrupts disabled */ +#define BRGPHY_PHY_EXTCTL_F_INT 0x0800 /* Force interrupt */ +#define BRGPHY_PHY_EXTCTL_BY_45 0x0400 /* Bypass 4B5B-Decoder */ +#define BRGPHY_PHY_EXTCTL_BY_SCR 0x0200 /* Bypass scrambler */ +#define BRGPHY_PHY_EXTCTL_BY_MLT3 0x0100 /* Bypass MLT3 encoder */ +#define BRGPHY_PHY_EXTCTL_BY_RXA 0x0080 /* Bypass RX alignment */ +#define BRGPHY_PHY_EXTCTL_RES_SCR 0x0040 /* Reset scrambler */ +#define BRGPHY_PHY_EXTCTL_EN_LTR 0x0020 /* Enable LED traffic mode */ +#define BRGPHY_PHY_EXTCTL_LED_ON 0x0010 /* Force LEDs on */ +#define BRGPHY_PHY_EXTCTL_LED_OFF 0x0008 /* Force LEDs off */ +#define BRGPHY_PHY_EXTCTL_EX_IPG 0x0004 /* Extended TX IPG mode */ +#define BRGPHY_PHY_EXTCTL_3_LED 0x0002 /* Three link LED mode */ +#define BRGPHY_PHY_EXTCTL_HIGH_LA 0x0001 /* GMII Fifo Elasticy (?) */ + +#define BRGPHY_MII_PHY_EXTSTS 0x11 /* PHY extended status */ +#define BRGPHY_PHY_EXTSTS_CROSS_STAT 0x2000 /* MDI crossover status */ +#define BRGPHY_PHY_EXTSTS_INT_STAT 0x1000 /* Interrupt status */ +#define BRGPHY_PHY_EXTSTS_RRS 0x0800 /* Remote receiver status */ +#define BRGPHY_PHY_EXTSTS_LRS 0x0400 /* Local receiver status */ +#define BRGPHY_PHY_EXTSTS_LOCKED 0x0200 /* Locked */ +#define BRGPHY_PHY_EXTSTS_LS 0x0100 /* Link status */ +#define BRGPHY_PHY_EXTSTS_RF 0x0080 /* Remove fault */ +#define BRGPHY_PHY_EXTSTS_CE_ER 0x0040 /* Carrier ext error */ +#define BRGPHY_PHY_EXTSTS_BAD_SSD 0x0020 /* Bad SSD */ +#define BRGPHY_PHY_EXTSTS_BAD_ESD 0x0010 /* Bad ESS */ +#define BRGPHY_PHY_EXTSTS_RX_ER 0x0008 /* RX error */ +#define BRGPHY_PHY_EXTSTS_TX_ER 0x0004 /* TX error */ +#define BRGPHY_PHY_EXTSTS_LOCK_ER 0x0002 /* Lock error */ +#define BRGPHY_PHY_EXTSTS_MLT3_ER 0x0001 /* MLT3 code error */ + +#define BRGPHY_MII_RXERRCNT 0x12 /* RX error counter */ + +#define BRGPHY_MII_FCERRCNT 0x13 /* False carrier sense counter */ +#define BGRPHY_FCERRCNT 0x00FF /* False carrier counter */ + +#define BRGPHY_MII_RXNOCNT 0x14 /* RX not OK counter */ +#define BRGPHY_RXNOCNT_LOCAL 0xFF00 /* Local RX not OK counter */ +#define BRGPHY_RXNOCNT_REMOTE 0x00FF /* Local RX not OK counter */ + +#define BRGPHY_MII_DSP_RW_PORT 0x15 /* DSP coefficient r/w port */ + +#define BRGPHY_MII_DSP_ADDR_REG 0x17 /* DSP coefficient addr register */ + +#define BRGPHY_DSP_TAP_NUMBER_MASK 0x00 +#define BRGPHY_DSP_AGC_A 0x00 +#define BRGPHY_DSP_AGC_B 0x01 +#define BRGPHY_DSP_MSE_PAIR_STATUS 0x02 +#define BRGPHY_DSP_SOFT_DECISION 0x03 +#define BRGPHY_DSP_PHASE_REG 0x04 +#define BRGPHY_DSP_SKEW 0x05 +#define BRGPHY_DSP_POWER_SAVER_UPPER_BOUND 0x06 +#define BRGPHY_DSP_POWER_SAVER_LOWER_BOUND 0x07 +#define BRGPHY_DSP_LAST_ECHO 0x08 +#define BRGPHY_DSP_FREQUENCY 0x09 +#define BRGPHY_DSP_PLL_BANDWIDTH 0x0A +#define BRGPHY_DSP_PLL_PHASE_OFFSET 0x0B + +#define BRGPHYDSP_FILTER_DCOFFSET 0x0C00 +#define BRGPHY_DSP_FILTER_FEXT3 0x0B00 +#define BRGPHY_DSP_FILTER_FEXT2 0x0A00 +#define BRGPHY_DSP_FILTER_FEXT1 0x0900 +#define BRGPHY_DSP_FILTER_FEXT0 0x0800 +#define BRGPHY_DSP_FILTER_NEXT3 0x0700 +#define BRGPHY_DSP_FILTER_NEXT2 0x0600 +#define BRGPHY_DSP_FILTER_NEXT1 0x0500 +#define BRGPHY_DSP_FILTER_NEXT0 0x0400 +#define BRGPHY_DSP_FILTER_ECHO 0x0300 +#define BRGPHY_DSP_FILTER_DFE 0x0200 +#define BRGPHY_DSP_FILTER_FFE 0x0100 + +#define BRGPHY_DSP_CONTROL_ALL_FILTERS 0x1000 + +#define BRGPHY_DSP_SEL_CH_0 0x0000 +#define BRGPHY_DSP_SEL_CH_1 0x2000 +#define BRGPHY_DSP_SEL_CH_2 0x4000 +#define BRGPHY_DSP_SEL_CH_3 0x6000 + +#define BRGPHY_MII_AUXCTL 0x18 /* AUX control */ +#define BRGPHY_AUXCTL_LOW_SQ 0x8000 /* Low squelch */ +#define BRGPHY_AUXCTL_LONG_PKT 0x4000 /* RX long packets */ +#define BRGPHY_AUXCTL_ER_CTL 0x3000 /* Edgerate control */ +#define BRGPHY_AUXCTL_TX_TST 0x0400 /* TX test, always 1 */ +#define BRGPHY_AUXCTL_DIS_PRF 0x0080 /* dis part resp filter */ +#define BRGPHY_AUXCTL_DIAG_MODE 0x0004 /* Diagnostic mode */ + +#define BRGPHY_MII_AUXSTS 0x19 /* AUX status */ +#define BRGPHY_AUXSTS_ACOMP 0x8000 /* Autoneg complete */ +#define BRGPHY_AUXSTS_AN_ACK 0x4000 /* Autoneg complete ack */ +#define BRGPHY_AUXSTS_AN_ACK_D 0x2000 /* Autoneg complete ack detect */ +#define BRGPHY_AUXSTS_AN_NPW 0x1000 /* Autoneg next page wait */ +#define BRGPHY_AUXSTS_AN_RES 0x0700 /* Autoneg HCD */ +#define BRGPHY_AUXSTS_PDF 0x0080 /* Parallel detect. fault */ +#define BRGPHY_AUXSTS_RF 0x0040 /* Remote fault */ +#define BRGPHY_AUXSTS_ANP_R 0x0020 /* Autoneg page received */ +#define BRGPHY_AUXSTS_LP_ANAB 0x0010 /* Link partner autoneg ability */ +#define BRGPHY_AUXSTS_LP_NPAB 0x0008 /* Link partner next page ability */ +#define BRGPHY_AUXSTS_LINK 0x0004 /* Link status */ +#define BRGPHY_AUXSTS_PRR 0x0002 /* Pause resolution-RX */ +#define BRGPHY_AUXSTS_PRT 0x0001 /* Pause resolution-TX */ + +#define BRGPHY_RES_1000FD 0x0700 /* 1000baseT full duplex */ +#define BRGPHY_RES_1000HD 0x0600 /* 1000baseT half duplex */ +#define BRGPHY_RES_100FD 0x0500 /* 100baseT full duplex */ +#define BRGPHY_RES_100T4 0x0400 /* 100baseT4 */ +#define BRGPHY_RES_100HD 0x0300 /* 100baseT half duplex */ +#define BRGPHY_RES_10FD 0x0200 /* 10baseT full duplex */ +#define BRGPHY_RES_10HD 0x0100 /* 10baseT half duplex */ + +#define BRGPHY_MII_ISR 0x1A /* Interrupt status */ +#define BRGPHY_ISR_PSERR 0x4000 /* Pair swap error */ +#define BRGPHY_ISR_MDXI_SC 0x2000 /* MDIX Status Change */ +#define BRGPHY_ISR_HCT 0x1000 /* Counter above 32K */ +#define BRGPHY_ISR_LCT 0x0800 /* All counter below 128 */ +#define BRGPHY_ISR_AN_PR 0x0400 /* Autoneg page received */ +#define BRGPHY_ISR_NO_HDCL 0x0200 /* No HCD Link */ +#define BRGPHY_ISR_NO_HDC 0x0100 /* No HCD */ +#define BRGPHY_ISR_USHDC 0x0080 /* Negotiated Unsupported HCD */ +#define BRGPHY_ISR_SCR_S_ERR 0x0040 /* Scrambler sync error */ +#define BRGPHY_ISR_RRS_CHG 0x0020 /* Remote RX status change */ +#define BRGPHY_ISR_LRS_CHG 0x0010 /* Local RX status change */ +#define BRGPHY_ISR_DUP_CHG 0x0008 /* Duplex mode change */ +#define BRGPHY_ISR_LSP_CHG 0x0004 /* Link speed changed */ +#define BRGPHY_ISR_LNK_CHG 0x0002 /* Link status change */ +#define BRGPHY_ISR_CRCERR 0x0001 /* CRC error */ + +#define BRGPHY_MII_IMR 0x1B /* Interrupt mask */ +#define BRGPHY_IMR_PSERR 0x4000 /* Pair swap error */ +#define BRGPHY_IMR_MDXI_SC 0x2000 /* MDIX Status Change */ +#define BRGPHY_IMR_HCT 0x1000 /* Counter above 32K */ +#define BRGPHY_IMR_LCT 0x0800 /* All counter below 128 */ +#define BRGPHY_IMR_AN_PR 0x0400 /* Autoneg page received */ +#define BRGPHY_IMR_NO_HDCL 0x0200 /* No HCD Link */ +#define BRGPHY_IMR_NO_HDC 0x0100 /* No HCD */ +#define BRGPHY_IMR_USHDC 0x0080 /* Negotiated Unsupported HCD */ +#define BRGPHY_IMR_SCR_S_ERR 0x0040 /* Scrambler sync error */ +#define BRGPHY_IMR_RRS_CHG 0x0020 /* Remote RX status change */ +#define BRGPHY_IMR_LRS_CHG 0x0010 /* Local RX status change */ +#define BRGPHY_IMR_DUP_CHG 0x0008 /* Duplex mode change */ +#define BRGPHY_IMR_LSP_CHG 0x0004 /* Link speed changed */ +#define BRGPHY_IMR_LNK_CHG 0x0002 /* Link status change */ +#define BRGPHY_IMR_CRCERR 0x0001 /* CRC error */ + +/*******************************************************/ +/* Begin: Shared SerDes PHY register definitions */ +/*******************************************************/ + +/* SerDes autoneg is different from copper */ +#define BRGPHY_SERDES_ANAR 0x04 +#define BRGPHY_SERDES_ANAR_FDX 0x0020 +#define BRGPHY_SERDES_ANAR_HDX 0x0040 +#define BRGPHY_SERDES_ANAR_NO_PAUSE (0x0 << 7) +#define BRGPHY_SERDES_ANAR_SYM_PAUSE (0x1 << 7) +#define BRGPHY_SERDES_ANAR_ASYM_PAUSE (0x2 << 7) +#define BRGPHY_SERDES_ANAR_BOTH_PAUSE (0x3 << 7) + +#define BRGPHY_SERDES_ANLPAR 0x05 +#define BRGPHY_SERDES_ANLPAR_FDX 0x0020 +#define BRGPHY_SERDES_ANLPAR_HDX 0x0040 +#define BRGPHY_SERDES_ANLPAR_NO_PAUSE (0x0 << 7) +#define BRGPHY_SERDES_ANLPAR_SYM_PAUSE (0x1 << 7) +#define BRGPHY_SERDES_ANLPAR_ASYM_PAUSE (0x2 << 7) +#define BRGPHY_SERDES_ANLPAR_BOTH_PAUSE (0x3 << 7) + +/*******************************************************/ +/* End: Shared SerDes PHY register definitions */ +/*******************************************************/ + +/*******************************************************/ +/* Begin: PHY register values for the 5706 PHY */ +/*******************************************************/ + +/* + * Shadow register 0x1C, bit 15 is write enable, + * bits 14-10 select function (0x00 to 0x1F). + */ +#define BRGPHY_MII_SHADOW_1C 0x1C +#define BRGPHY_SHADOW_1C_WRITE_EN 0x8000 +#define BRGPHY_SHADOW_1C_SELECT_MASK 0x7C00 + +/* Shadow 0x1C Mode Control Register (select value 0x1F) */ +#define BRGPHY_SHADOW_1C_MODE_CTRL (0x1F << 10) +/* When set, Regs 0-0x0F are 1000X, else 1000T */ +#define BRGPHY_SHADOW_1C_ENA_1000X 0x0001 + +#define BRGPHY_MII_TEST1 0x1E +#define BRGPHY_TEST1_TRIM_EN 0x0010 +#define BRGPHY_TEST1_CRC_EN 0x8000 + +#define BRGPHY_MII_TEST2 0x1F + +/*******************************************************/ +/* End: PHY register values for the 5706 PHY */ +/*******************************************************/ + +/*******************************************************/ +/* Begin: PHY register values for the 5708S SerDes PHY */ +/*******************************************************/ + +/* Autoneg Next Page Transmit 1 Regiser */ +#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1 0x0B +#define BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G 0x0001 + +/* Use the BLOCK_ADDR register to select the page for registers 0x10 to 0x1E */ +#define BRGPHY_5708S_BLOCK_ADDR 0x1f +#define BRGPHY_5708S_DIG_PG0 0x0000 +#define BRGPHY_5708S_DIG3_PG2 0x0002 +#define BRGPHY_5708S_TX_MISC_PG5 0x0005 + +/* 5708S SerDes "Digital" Registers (page 0) */ +#define BRGPHY_5708S_PG0_1000X_CTL1 0x10 +#define BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN 0x0010 +#define BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE 0x0001 + +#define BRGPHY_5708S_PG0_1000X_STAT1 0x14 +#define BRGPHY_5708S_PG0_1000X_STAT1_LINK 0x0002 +#define BRGPHY_5708S_PG0_1000X_STAT1_FDX 0x0004 +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK 0x0018 +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10 (0x0 << 3) +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100 (0x1 << 3) +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G (0x2 << 3) +#define BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G (0x3 << 3) + + +#define BRGPHY_5708S_PG0_1000X_CTL2 0x11 +#define BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN 0x0001 + +/* 5708S SerDes "Digital 3" Registers (page 2) */ +#define BRGPHY_5708S_PG2_DIGCTL_3_0 0x10 +#define BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE 0x0001 + +/* 5708S SerDes "TX Misc" Registers (page 5) */ +#define BRGPHY_5708S_PG5_2500STATUS1 0x10 +#define BRGPHY_5708S_PG5_TXACTL1 0x15 +#define BRGPHY_5708S_PG5_TXACTL3 0x17 + +/*******************************************************/ +/* End: PHY register values for the 5708S SerDes PHY */ +/*******************************************************/ + +#define BRGPHY_INTRS \ + ~(BRGPHY_IMR_LNK_CHG|BRGPHY_IMR_LSP_CHG|BRGPHY_IMR_DUP_CHG) + +#endif /* _DEV_BRGPHY_MIIREG_H_ */ diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/miidevs.h b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/miidevs.h new file mode 100644 index 0000000000..9ee45234c2 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/miidevs.h @@ -0,0 +1,12 @@ +#define MII_OUI_BROADCOM 0x001018 +#define MII_MODEL_BROADCOM_3C905B 0x0012 +#define MII_MODEL_BROADCOM_3C905C 0x0017 +#define MII_MODEL_BROADCOM_BCM5201 0x0021 +#define MII_MODEL_BROADCOM_BCM5221 0x001e +#define MII_MODEL_BROADCOM_BCM4401 0x0036 + +#define MII_STR_BROADCOM_3C905B "3C905B" +#define MII_STR_BROADCOM_3C905C "3C905C" +#define MII_STR_BROADCOM_BCM5201 "BCM5201" +#define MII_STR_BROADCOM_BCM5221 "BCM5221" +#define MII_STR_BROADCOM_BCM4401 "BCM4401" diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy.c b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy.c new file mode 100644 index 0000000000..10347825bf --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy.c @@ -0,0 +1,220 @@ +/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */ + +/*- + * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center, and by Frank van der Linden. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1997 Manuel Bouyer. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Manuel Bouyer. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $"); + +/* + * driver for generic unknown PHYs + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "miibus_if.h" + +static int ukphy_probe(device_t); +static int ukphy_attach(device_t); + +static device_method_t ukphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, ukphy_probe), + DEVMETHOD(device_attach, ukphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t ukphy_devclass; + +static driver_t ukphy_driver = { + "ukphy", + ukphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0); + +static int ukphy_service(struct mii_softc *, struct mii_data *, int); + +static int +ukphy_probe(device_t dev) +{ + + /* + * We know something is here, so always match at a low priority. + */ + device_set_desc(dev, "Generic IEEE 802.3u media interface"); + return (BUS_PROBE_GENERIC); +} + +static int +ukphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = device_get_softc(sc->mii_dev); + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + if (bootverbose) + device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", + MII_OUI(ma->mii_id1, ma->mii_id2), + MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2)); + + sc->mii_inst = mii->mii_instance; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = ukphy_service; + sc->mii_pdata = mii; + + mii->mii_instance++; + + mii_phy_reset(sc); + + sc->mii_capabilities = + PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + mii_phy_setmedia(sc); + + return (0); +} + +static int +ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int reg; + + switch (cmd) { + case MII_POLLSTAT: + /* + * If we're not polling our PHY instance, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + break; + + case MII_MEDIACHG: + /* + * If the media indicates a different PHY instance, + * isolate ourselves. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) { + reg = PHY_READ(sc, MII_BMCR); + PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); + return (0); + } + + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + mii_phy_setmedia(sc); + break; + + case MII_TICK: + /* + * If we're not currently selected, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + if (mii_phy_tick(sc) == EJUSTRETURN) + return (0); + break; + } + + /* Update the media status. */ + ukphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} diff --git a/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy_subr.c b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy_subr.c new file mode 100644 index 0000000000..fb40b75c1d --- /dev/null +++ b/src/add-ons/kernel/drivers/network/broadcom_bcm570x/dev/mii/ukphy_subr.c @@ -0,0 +1,129 @@ +/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center, and by Frank van der Linden. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.8.8.1 2006/07/19 04:40:26 yongari Exp $"); + +/* + * Subroutines shared by the ukphy driver and other PHY drivers. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "miibus_if.h" + +/* + * Media status subroutine. If a PHY driver does media detection simply + * by decoding the NWay autonegotiation, use this routine. + */ +void +ukphy_status(struct mii_softc *phy) +{ + struct mii_data *mii = phy->mii_pdata; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int bmsr, bmcr, anlpar, gtcr, gtsr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR); + if (bmsr & BMSR_LINK) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(phy, MII_BMCR); + if (bmcr & BMCR_ISO) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if (bmcr & BMCR_LOOP) + mii->mii_media_active |= IFM_LOOP; + + if (bmcr & BMCR_AUTOEN) { + /* + * NWay autonegotiation takes the highest-order common + * bit of the ANAR and ANLPAR (i.e. best media advertised + * both by us and our link partner). + */ + if ((bmsr & BMSR_ACOMP) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR); + if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 && + (phy->mii_extcapabilities & + (EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) { + gtcr = PHY_READ(phy, MII_100T2CR); + gtsr = PHY_READ(phy, MII_100T2SR); + } else + gtcr = gtsr = 0; + + if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX)) + mii->mii_media_active |= IFM_1000_T|IFM_FDX; + else if ((gtcr & GTCR_ADV_1000THDX) && + (gtsr & GTSR_LP_1000THDX)) + mii->mii_media_active |= IFM_1000_T; + else if (anlpar & ANLPAR_T4) + mii->mii_media_active |= IFM_100_T4; + else if (anlpar & ANLPAR_TX_FD) + mii->mii_media_active |= IFM_100_TX|IFM_FDX; + else if (anlpar & ANLPAR_TX) + mii->mii_media_active |= IFM_100_TX; + else if (anlpar & ANLPAR_10_FD) + mii->mii_media_active |= IFM_10_T|IFM_FDX; + else if (anlpar & ANLPAR_10) + mii->mii_media_active |= IFM_10_T; + else + mii->mii_media_active |= IFM_NONE; + } else + mii->mii_media_active = ife->ifm_media; +} diff --git a/src/add-ons/kernel/drivers/network/nforce/Jamfile b/src/add-ons/kernel/drivers/network/nforce/Jamfile new file mode 100644 index 0000000000..4510eae910 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/Jamfile @@ -0,0 +1,3 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network nforce ; + +SubInclude HAIKU_TOP src add-ons kernel drivers network nforce dev ; diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/Jamfile b/src/add-ons/kernel/drivers/network/nforce/dev/Jamfile new file mode 100644 index 0000000000..2e896d5050 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/Jamfile @@ -0,0 +1,4 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network nforce dev ; + +SubInclude HAIKU_TOP src add-ons kernel drivers network nforce dev mii ; +SubInclude HAIKU_TOP src add-ons kernel drivers network nforce dev nfe ; diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/mii/Jamfile b/src/add-ons/kernel/drivers/network/nforce/dev/mii/Jamfile new file mode 100644 index 0000000000..990eddf9d8 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/mii/Jamfile @@ -0,0 +1,15 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network nforce dev mii ; + +UsePrivateHeaders kernel net ; + +UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ; +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ; + +KernelStaticLibrary nforce_mii.a + : + ciphy.c + ukphy.c + ukphy_subr.c + ; diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphy.c b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphy.c new file mode 100644 index 0000000000..1c97cacffb --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphy.c @@ -0,0 +1,424 @@ +/*- + * Copyright (c) 2004 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/ciphy.c,v 1.9 2007/06/06 06:55:49 yongari Exp $"); + +/* + * Driver for the Cicada CS8201 10/100/1000 copper PHY. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include "miidevs.h" + +#include + +#include "miibus_if.h" + +#include +/* +#include +*/ +static int ciphy_probe(device_t); +static int ciphy_attach(device_t); + +static device_method_t ciphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, ciphy_probe), + DEVMETHOD(device_attach, ciphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t ciphy_devclass; + +static driver_t ciphy_driver = { + "ciphy", + ciphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(ciphy, miibus, ciphy_driver, ciphy_devclass, 0, 0); + +static int ciphy_service(struct mii_softc *, struct mii_data *, int); +static void ciphy_status(struct mii_softc *); +static void ciphy_reset(struct mii_softc *); +static void ciphy_fixup(struct mii_softc *); + +static const struct mii_phydesc ciphys[] = { + MII_PHY_DESC(CICADA, CS8201), + MII_PHY_DESC(CICADA, CS8201A), + MII_PHY_DESC(CICADA, CS8201B), + MII_PHY_DESC(VITESSE, VSC8601), + MII_PHY_END +}; + +static int +ciphy_probe(device_t dev) +{ + + return (mii_phy_dev_probe(dev, ciphys, BUS_PROBE_DEFAULT)); +} + +static int +ciphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = device_get_softc(sc->mii_dev); + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + sc->mii_inst = mii->mii_instance; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = ciphy_service; + sc->mii_pdata = mii; + + sc->mii_flags |= MIIF_NOISOLATE; + mii->mii_instance++; + + ciphy_reset(sc); + + sc->mii_capabilities = + PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + return (0); +} + +static int +ciphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int reg, speed, gig; + + switch (cmd) { + case MII_POLLSTAT: + /* + * If we're not polling our PHY instance, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + break; + + case MII_MEDIACHG: + /* + * If the media indicates a different PHY instance, + * isolate ourselves. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) { + reg = PHY_READ(sc, MII_BMCR); + PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); + return (0); + } + + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + ciphy_fixup(sc); /* XXX hardware bug work-around */ + + switch (IFM_SUBTYPE(ife->ifm_media)) { + case IFM_AUTO: +#ifdef foo + /* + * If we're already in auto mode, just return. + */ + if (PHY_READ(sc, CIPHY_MII_BMCR) & CIPHY_BMCR_AUTOEN) + return (0); +#endif + (void) mii_phy_auto(sc); + break; + case IFM_1000_T: + speed = CIPHY_S1000; + goto setit; + case IFM_100_TX: + speed = CIPHY_S100; + goto setit; + case IFM_10_T: + speed = CIPHY_S10; +setit: + if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { + speed |= CIPHY_BMCR_FDX; + gig = CIPHY_1000CTL_AFD; + } else { + gig = CIPHY_1000CTL_AHD; + } + + PHY_WRITE(sc, CIPHY_MII_1000CTL, 0); + PHY_WRITE(sc, CIPHY_MII_BMCR, speed); + PHY_WRITE(sc, CIPHY_MII_ANAR, CIPHY_SEL_TYPE); + + if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) + break; + + PHY_WRITE(sc, CIPHY_MII_1000CTL, gig); + PHY_WRITE(sc, CIPHY_MII_BMCR, + speed|CIPHY_BMCR_AUTOEN|CIPHY_BMCR_STARTNEG); + + /* + * When setting the link manually, one side must + * be the master and the other the slave. However + * ifmedia doesn't give us a good way to specify + * this, so we fake it by using one of the LINK + * flags. If LINK0 is set, we program the PHY to + * be a master, otherwise it's a slave. + */ + if ((mii->mii_ifp->if_flags & IFF_LINK0)) { + PHY_WRITE(sc, CIPHY_MII_1000CTL, + gig|CIPHY_1000CTL_MSE|CIPHY_1000CTL_MSC); + } else { + PHY_WRITE(sc, CIPHY_MII_1000CTL, + gig|CIPHY_1000CTL_MSE); + } + break; + case IFM_NONE: + PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN); + break; + case IFM_100_T4: + default: + return (EINVAL); + } + break; + + case MII_TICK: + /* + * If we're not currently selected, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + + /* + * Is the interface even up? + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + return (0); + + /* + * Only used for autonegotiation. + */ + if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) + break; + + /* + * Check to see if we have link. If we do, we don't + * need to restart the autonegotiation process. Read + * the BMSR twice in case it's latched. + */ + reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); + if (reg & BMSR_LINK) + break; + + /* + * Only retry autonegotiation every 5 seconds. + */ + if (++sc->mii_ticks <= MII_ANEGTICKS) + break; + + sc->mii_ticks = 0; + mii_phy_auto(sc); + return (0); + } + + /* Update the media status. */ + ciphy_status(sc); + + /* + * Callback if something changed. Note that we need to poke + * apply fixups for certain PHY revs. + */ + if (sc->mii_media_active != mii->mii_media_active || + sc->mii_media_status != mii->mii_media_status || + cmd == MII_MEDIACHG) { + ciphy_fixup(sc); + } + mii_phy_update(sc, cmd); + return (0); +} + +static void +ciphy_status(struct mii_softc *sc) +{ + struct mii_data *mii = sc->mii_pdata; + int bmsr, bmcr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); + + if (bmsr & BMSR_LINK) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(sc, CIPHY_MII_BMCR); + + if (bmcr & CIPHY_BMCR_LOOP) + mii->mii_media_active |= IFM_LOOP; + + if (bmcr & CIPHY_BMCR_AUTOEN) { + if ((bmsr & CIPHY_BMSR_ACOMP) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + } + + bmsr = PHY_READ(sc, CIPHY_MII_AUXCSR); + switch (bmsr & CIPHY_AUXCSR_SPEED) { + case CIPHY_SPEED10: + mii->mii_media_active |= IFM_10_T; + break; + case CIPHY_SPEED100: + mii->mii_media_active |= IFM_100_TX; + break; + case CIPHY_SPEED1000: + mii->mii_media_active |= IFM_1000_T; + break; + default: + device_printf(sc->mii_dev, "unknown PHY speed %x\n", + bmsr & CIPHY_AUXCSR_SPEED); + break; + } + + if (bmsr & CIPHY_AUXCSR_FDX) + mii->mii_media_active |= IFM_FDX; +} + +static void +ciphy_reset(struct mii_softc *sc) +{ + + mii_phy_reset(sc); + DELAY(1000); +} + +#define PHY_SETBIT(x, y, z) \ + PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) +#define PHY_CLRBIT(x, y, z) \ + PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) + +static void +ciphy_fixup(struct mii_softc *sc) +{ + uint16_t model; + uint16_t status, speed; + uint16_t val; + + model = MII_MODEL(PHY_READ(sc, CIPHY_MII_PHYIDR2)); + status = PHY_READ(sc, CIPHY_MII_AUXCSR); + speed = status & CIPHY_AUXCSR_SPEED; + + if (strcmp(device_get_name(device_get_parent(sc->mii_dev)), + "nfe") == 0) { + /* need to set for 2.5V RGMII for NVIDIA adapters */ + val = PHY_READ(sc, CIPHY_MII_ECTL1); + val &= ~(CIPHY_ECTL1_IOVOL | CIPHY_ECTL1_INTSEL); + val |= (CIPHY_IOVOL_2500MV | CIPHY_INTSEL_RGMII); + PHY_WRITE(sc, CIPHY_MII_ECTL1, val); + /* From Linux. */ + val = PHY_READ(sc, CIPHY_MII_AUXCSR); + val |= CIPHY_AUXCSR_MDPPS; + PHY_WRITE(sc, CIPHY_MII_AUXCSR, val); + val = PHY_READ(sc, CIPHY_MII_10BTCSR); + val |= CIPHY_10BTCSR_ECHO; + PHY_WRITE(sc, CIPHY_MII_10BTCSR, val); + } + + switch (model) { + case MII_MODEL_CICADA_CS8201: + + /* Turn off "aux mode" (whatever that means) */ + PHY_SETBIT(sc, CIPHY_MII_AUXCSR, CIPHY_AUXCSR_MDPPS); + + /* + * Work around speed polling bug in VT3119/VT3216 + * when using MII in full duplex mode. + */ + if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && + (status & CIPHY_AUXCSR_FDX)) { + PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); + } else { + PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); + } + + /* Enable link/activity LED blink. */ + PHY_SETBIT(sc, CIPHY_MII_LED, CIPHY_LED_LINKACTBLINK); + + break; + + case MII_MODEL_CICADA_CS8201A: + case MII_MODEL_CICADA_CS8201B: + + /* + * Work around speed polling bug in VT3119/VT3216 + * when using MII in full duplex mode. + */ + if ((speed == CIPHY_SPEED10 || speed == CIPHY_SPEED100) && + (status & CIPHY_AUXCSR_FDX)) { + PHY_SETBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); + } else { + PHY_CLRBIT(sc, CIPHY_MII_10BTCSR, CIPHY_10BTCSR_ECHO); + } + + break; + case MII_MODEL_VITESSE_VSC8601: + break; + default: + device_printf(sc->mii_dev, "unknown CICADA PHY model %x\n", + model); + break; + } +} diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphyreg.h b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphyreg.h new file mode 100644 index 0000000000..485e0a4220 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ciphyreg.h @@ -0,0 +1,361 @@ +/*- + * Copyright (c) 2004 + * Bill Paul . All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Bill Paul. + * 4. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD: src/sys/dev/mii/ciphyreg.h,v 1.3 2007/06/06 06:55:49 yongari Exp $ + */ + +#ifndef _DEV_MII_CIPHYREG_H_ +#define _DEV_MII_CIPHYREG_H_ + +/* + * Register definitions for the Cicada CS8201 10/100/1000 gigE copper + * PHY, embedded within the VIA Networks VT6122 controller. + */ + +/* Command register */ +#define CIPHY_MII_BMCR 0x00 +#define CIPHY_BMCR_RESET 0x8000 +#define CIPHY_BMCR_LOOP 0x4000 +#define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */ +#define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */ +#define CIPHY_BMCR_PDOWN 0x0800 /* Power down */ +#define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */ +#define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */ +#define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */ +#define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */ + +#define CIPHY_S1000 CIPHY_BMCR_SPD1 /* 1000mbps */ +#define CIPHY_S100 CIPHY_BMCR_SPD0 /* 100mpbs */ +#define CIPHY_S10 0 /* 10mbps */ + +/* Status register */ +#define CIPHY_MII_BMSR 0x01 +#define CIPHY_BMSR_100T4 0x8000 /* 100 base T4 capable */ +#define CIPHY_BMSR_100TXFDX 0x4000 /* 100 base Tx full duplex capable */ +#define CIPHY_BMSR_100TXHDX 0x2000 /* 100 base Tx half duplex capable */ +#define CIPHY_BMSR_10TFDX 0x1000 /* 10 base T full duplex capable */ +#define CIPHY_BMSR_10THDX 0x0800 /* 10 base T half duplex capable */ +#define CIPHY_BMSR_100T2FDX 0x0400 /* 100 base T2 full duplex capable */ +#define CIPHY_BMSR_100T2HDX 0x0200 /* 100 base T2 half duplex capable */ +#define CIPHY_BMSR_EXTSTS 0x0100 /* Extended status present */ +#define CIPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */ +#define CIPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */ +#define CIPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */ +#define CIPHY_BMSR_ANEG 0x0008 /* Autoneg capable */ +#define CIPHY_BMSR_LINK 0x0004 /* Link status */ +#define CIPHY_BMSR_JABBER 0x0002 /* Jabber detected */ +#define CIPHY_BMSR_EXT 0x0001 /* Extended capability */ + +/* PHY ID registers */ +#define CIPHY_MII_PHYIDR1 0x02 +#define CIPHY_MII_PHYIDR2 0x03 + +/* Autoneg advertisement */ +#define CIPHY_MII_ANAR 0x04 +#define CIPHY_ANAR_NP 0x8000 /* Next page */ +#define CIPHY_ANAR_RF 0x2000 /* Remote fault */ +#define CIPHY_ANAR_ASP 0x0800 /* Asymmetric Pause */ +#define CIPHY_ANAR_PC 0x0400 /* Pause capable */ +#define CIPHY_ANAR_T4 0x0200 /* local device supports 100bT4 */ +#define CIPHY_ANAR_TX_FD 0x0100 /* local device supports 100bTx FD */ +#define CIPHY_ANAR_TX 0x0080 /* local device supports 100bTx */ +#define CIPHY_ANAR_10_FD 0x0040 /* local device supports 10bT FD */ +#define CIPHY_ANAR_10 0x0020 /* local device supports 10bT */ +#define CIPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */ + +/* Autoneg link partner ability */ +#define CIPHY_MII_ANLPAR 0x05 +#define CIPHY_ANLPAR_NP 0x8000 /* Next page */ +#define CIPHY_ANLPAR_ACK 0x4000 /* link partner acknowledge */ +#define CIPHY_ANLPAR_RF 0x2000 /* Remote fault */ +#define CIPHY_ANLPAR_ASP 0x0800 /* Asymmetric Pause */ +#define CIPHY_ANLPAR_PC 0x0400 /* Pause capable */ +#define CIPHY_ANLPAR_T4 0x0200 /* link partner supports 100bT4 */ +#define CIPHY_ANLPAR_TX_FD 0x0100 /* link partner supports 100bTx FD */ +#define CIPHY_ANLPAR_TX 0x0080 /* link partner supports 100bTx */ +#define CIPHY_ANLPAR_10_FD 0x0040 /* link partner supports 10bT FD */ +#define CIPHY_ANLPAR_10 0x0020 /* link partner supports 10bT */ +#define CIPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */ + +#define CIPHY_SEL_TYPE 0x0001 /* ethernet */ + +/* Antoneg expansion register */ +#define CIPHY_MII_ANER 0x06 +#define CIPHY_ANER_PDF 0x0010 /* Parallel detection fault */ +#define CIPHY_ANER_LPNP 0x0008 /* Link partner can next page */ +#define CIPHY_ANER_NP 0x0004 /* Local PHY can next page */ +#define CIPHY_ANER_RX 0x0002 /* Next page received */ +#define CIPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */ + +/* Autoneg next page transmit regisyer */ +#define CIPHY_MII_NEXTP 0x07 +#define CIPHY_NEXTP_MOREP 0x8000 /* More pages to follow */ +#define CIPHY_NEXTP_MESS 0x2000 /* 1 = message page, 0 = unformatted */ +#define CIPHY_NEXTP_ACK2 0x1000 /* MAC acknowledge */ +#define CIPHY_NEXTP_TOGGLE 0x0800 /* Toggle */ +#define CIPHY_NEXTP_CODE 0x07FF /* Code bits */ + +/* Autoneg link partner next page receive register */ +#define CIPHY_MII_NEXTP_LP 0x08 +#define CIPHY_NEXTPLP_MOREP 0x8000 /* More pages to follow */ +#define CIPHY_NEXTPLP_MESS 0x2000 /* 1 = message page, 0 = unformatted */ +#define CIPHY_NEXTPLP_ACK2 0x1000 /* MAC acknowledge */ +#define CIPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */ +#define CIPHY_NEXTPLP_CODE 0x07FF /* Code bits */ + +/* 1000BT control register */ +#define CIPHY_MII_1000CTL 0x09 +#define CIPHY_1000CTL_TST 0xE000 /* test modes */ +#define CIPHY_1000CTL_MSE 0x1000 /* Master/Slave manual enable */ +#define CIPHY_1000CTL_MSC 0x0800 /* Master/Slave select */ +#define CIPHY_1000CTL_RD 0x0400 /* Repeater/DTE */ +#define CIPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */ +#define CIPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */ + +#define CIPHY_TEST_TX_JITTER 0x2000 +#define CIPHY_TEST_TX_JITTER_MASTER_MODE 0x4000 +#define CIPHY_TEST_TX_JITTER_SLAVE_MODE 0x6000 +#define CIPHY_TEST_TX_DISTORTION 0x8000 + +/* 1000BT status register */ +#define CIPHY_MII_1000STS 0x0A +#define CIPHY_1000STS_MSF 0x8000 /* Master/slave fault */ +#define CIPHY_1000STS_MSR 0x4000 /* Master/slave result */ +#define CIPHY_1000STS_LRS 0x2000 /* Local receiver status */ +#define CIPHY_1000STS_RRS 0x1000 /* Remote receiver status */ +#define CIPHY_1000STS_LPFD 0x0800 /* Link partner can FD */ +#define CIPHY_1000STS_LPHD 0x0400 /* Link partner can HD */ +#define CIPHY_1000STS_IEC 0x00FF /* Idle error count */ + +#define CIPHY_MII_EXTSTS 0x0F /* Extended status */ +#define CIPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */ +#define CIPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */ +#define CIPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */ +#define CIPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */ + +/* 1000BT status extension register #1 */ +#define CIPHY_MII_1000STS1 0x0F +#define CIPHY_1000STS1_1000XFDX 0x8000 /* 1000baseX FDX capable */ +#define CIPHY_1000STS1_1000XHDX 0x4000 /* 1000baseX HDX capable */ +#define CIPHY_1000STS1_1000TFDX 0x2000 /* 1000baseT FDX capable */ +#define CIPHY_1000STS1_1000THDX 0x1000 /* 1000baseT HDX capable */ + +/* Vendor-specific PHY registers */ + +/* 100baseTX status extention register */ +#define CIPHY_MII_100STS 0x10 +#define CIPHY_100STS_DESLCK 0x8000 /* descrambler locked */ +#define CIPHY_100STS_LKCERR 0x4000 /* lock error detected/lock lost */ +#define CIPHY_100STS_DISC 0x2000 /* disconnect state */ +#define CIPHY_100STS_LINK 0x1000 /* current link state */ +#define CIPHY_100STS_RXERR 0x0800 /* receive error detected */ +#define CIPHY_100STS_TXERR 0x0400 /* transmit error detected */ +#define CIPHY_100STS_SSDERR 0x0200 /* false carrier error detected */ +#define CIPHY_100STS_ESDERR 0x0100 /* premature end of stream error */ + +/* 1000BT status extention register #2 */ +#define CIPHY_MII_1000STS2 0x11 +#define CIPHY_1000STS2_DESLCK 0x8000 /* descrambler locked */ +#define CIPHY_1000STS2_LKCERR 0x4000 /* lock error detected/lock lost */ +#define CIPHY_1000STS2_DISC 0x2000 /* disconnect state */ +#define CIPHY_1000STS2_LINK 0x1000 /* current link state */ +#define CIPHY_1000STS2_RXERR 0x0800 /* receive error detected */ +#define CIPHY_1000STS2_TXERR 0x0400 /* transmit error detected */ +#define CIPHY_1000STS2_SSDERR 0x0200 /* false carrier error detected */ +#define CIPHY_1000STS2_ESDERR 0x0100 /* premature end of stream error */ +#define CIPHY_1000STS2_CARREXT 0x0080 /* carrier extention err detected */ +#define CIPHY_1000STS2_BCM5400 0x0040 /* non-complient BCM5400 detected */ + +/* Bypass control register */ +#define CIPHY_MII_BYPASS 0x12 +#define CIPHY_BYPASS_TX 0x8000 /* transmit disable */ +#define CIPHY_BYPASS_4B5B 0x4000 /* bypass the 4B5B encoder */ +#define CIPHY_BYPASS_SCRAM 0x2000 /* bypass scrambler */ +#define CIPHY_BYPASS_DSCAM 0x1000 /* bypass descrambler */ +#define CIPHY_BYPASS_PCSRX 0x0800 /* bypass PCS receive */ +#define CIPHY_BYPASS_PCSTX 0x0400 /* bypass PCS transmit */ +#define CIPHY_BYPASS_LFI 0x0200 /* bypass LFI timer */ +#define CIPHY_BYPASS_TXCLK 0x0100 /* enable transmit clock on LED4 pin */ +#define CIPHY_BYPASS_BCM5400_F 0x0080 /* force BCM5400 detect */ +#define CIPHY_BYPASS_BCM5400 0x0040 /* bypass BCM5400 detect */ +#define CIPHY_BYPASS_PAIRSWAP 0x0020 /* disable automatic pair swap */ +#define CIPHY_BYPASS_POLARITY 0x0010 /* disable polarity correction */ +#define CIPHY_BYPASS_PARALLEL 0x0008 /* parallel detect enable */ +#define CIPHY_BYPASS_PULSE 0x0004 /* disable pulse shaping filter */ +#define CIPHY_BYPASS_1000BNP 0x0002 /* disable 1000BT next page exchange */ + +/* RX error count register */ +#define CIPHY_MII_RXERR 0x13 + +/* False carrier sense count register */ +#define CIPHY_MII_FCSERR 0x14 + +/* Ddisconnect error counter */ +#define CIPHY_MII_DISCERR 0x15 + +/* 10baseT control/status register */ +#define CIPHY_MII_10BTCSR 0x16 +#define CIPHY_10BTCSR_DLIT 0x8000 /* Disable data link integrity test */ +#define CIPHY_10BTCSR_JABBER 0x4000 /* Disable jabber detect */ +#define CIPHY_10BTCSR_ECHO 0x2000 /* Disable echo mode */ +#define CIPHY_10BTCSR_SQE 0x1000 /* Disable signal quality error */ +#define CIPHY_10BTCSR_SQUENCH 0x0C00 /* Squelch control */ +#define CIPHY_10BTCSR_EOFERR 0x0100 /* End of Frame error */ +#define CIPHY_10BTCSR_DISC 0x0080 /* Disconnect status */ +#define CIPHY_10BTCSR_LINK 0x0040 /* current link state */ +#define CIPHY_10BTCSR_ITRIM 0x0038 /* current reference trim */ +#define CIPHY_10BTCSR_CSR 0x0006 /* CSR behavior control */ + +#define CIPHY_SQUELCH_300MV 0x0000 +#define CIPHY_SQUELCH_197MV 0x0400 +#define CIPHY_SQUELCH_450MV 0x0800 +#define CIPHY_SQUELCH_RSVD 0x0C00 + +#define CIPHY_ITRIM_PLUS2 0x0000 +#define CIPHY_ITRIM_PLUS4 0x0008 +#define CIPHY_ITRIM_PLUS6 0x0010 +#define CIPHY_ITRIM_PLUS6_ 0x0018 +#define CIPHY_ITRIM_MINUS4 0x0020 +#define CIPHY_ITRIM_MINUS4_ 0x0028 +#define CIPHY_ITRIM_MINUS2 0x0030 +#define CIPHY_ITRIM_ZERO 0x0038 + +/* Extended PHY control register #1 */ +#define CIPHY_MII_ECTL1 0x17 +#define CIPHY_ECTL1_ACTIPHY 0x0020 /* Enable ActiPHY power saving */ +#define CIPHY_ECTL1_IOVOL 0x0e00 /* MAC interface and I/O voltage select */ +#define CIPHY_ECTL1_INTSEL 0xf000 /* select MAC interface */ + +#define CIPHY_IOVOL_3300MV 0x0000 /* 3.3V for I/O pins */ +#define CIPHY_IOVOL_2500MV 0x0200 /* 2.5V for I/O pins */ + +#define CIPHY_INTSEL_GMII 0x0000 /* GMII/MII */ +#define CIPHY_INTSEL_RGMII 0x1000 +#define CIPHY_INTSEL_TBI 0x2000 +#define CIPHY_INTSEL_RTBI 0x3000 + +/* Extended PHY control register #2 */ +#define CIPHY_MII_ECTL2 0x18 +#define CIPHY_ECTL2_ERATE 0xE000 /* 10/1000 edge rate control */ +#define CIPHY_ECTL2_VTRIM 0x1C00 /* voltage reference trim */ +#define CIPHY_ECTL2_CABLELEN 0x000E /* Cable quality/length */ +#define CIPHY_ECTL2_ANALOGLOOP 0x0001 /* 1000BT analog loopback */ + +#define CIPHY_CABLELEN_0TO10M 0x0000 +#define CIPHY_CABLELEN_10TO20M 0x0002 +#define CIPHY_CABLELEN_20TO40M 0x0004 +#define CIPHY_CABLELEN_40TO80M 0x0006 +#define CIPHY_CABLELEN_80TO100M 0x0008 +#define CIPHY_CABLELEN_100TO140M 0x000A +#define CIPHY_CABLELEN_140TO180M 0x000C +#define CIPHY_CABLELEN_OVER180M 0x000E + +/* Interrupt mask register */ +#define CIPHY_MII_IMR 0x19 +#define CIPHY_IMR_PINENABLE 0x8000 /* Interrupt pin enable */ +#define CIPHY_IMR_SPEED 0x4000 /* speed changed event */ +#define CIPHY_IMR_LINK 0x2000 /* link change/ActiPHY event */ +#define CIPHY_IMR_DPX 0x1000 /* duplex change event */ +#define CIPHY_IMR_ANEGERR 0x0800 /* autoneg error event */ +#define CIPHY_IMR_ANEGDONE 0x0400 /* autoneg done event */ +#define CIPHY_IMR_NPRX 0x0200 /* page received event */ +#define CIPHY_IMR_SYMERR 0x0100 /* symbol error event */ +#define CIPHY_IMR_LOCKERR 0x0080 /* descrambler lock lost event */ +#define CIPHY_IMR_XOVER 0x0040 /* MDI crossover change event */ +#define CIPHY_IMR_POLARITY 0x0020 /* polarity change event */ +#define CIPHY_IMR_JABBER 0x0010 /* jabber detect event */ +#define CIPHY_IMR_SSDERR 0x0008 /* false carrier detect event */ +#define CIPHY_IMR_ESDERR 0x0004 /* parallel detect error event */ +#define CIPHY_IMR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ +#define CIPHY_IMR_RXERR 0x0001 /* RX error event */ + +/* Interrupt status register */ +#define CIPHY_MII_ISR 0x1A +#define CIPHY_ISR_IPENDING 0x8000 /* Interrupt is pending */ +#define CIPHY_ISR_SPEED 0x4000 /* speed changed event */ +#define CIPHY_ISR_LINK 0x2000 /* link change/ActiPHY event */ +#define CIPHY_ISR_DPX 0x1000 /* duplex change event */ +#define CIPHY_ISR_ANEGERR 0x0800 /* autoneg error event */ +#define CIPHY_ISR_ANEGDONE 0x0400 /* autoneg done event */ +#define CIPHY_ISR_NPRX 0x0200 /* page received event */ +#define CIPHY_ISR_SYMERR 0x0100 /* symbol error event */ +#define CIPHY_ISR_LOCKERR 0x0080 /* descrambler lock lost event */ +#define CIPHY_ISR_XOVER 0x0040 /* MDI crossover change event */ +#define CIPHY_ISR_POLARITY 0x0020 /* polarity change event */ +#define CIPHY_ISR_JABBER 0x0010 /* jabber detect event */ +#define CIPHY_ISR_SSDERR 0x0008 /* false carrier detect event */ +#define CIPHY_ISR_ESDERR 0x0004 /* parallel detect error event */ +#define CIPHY_ISR_MASTERSLAVE 0x0002 /* master/slave resolve done event */ +#define CIPHY_ISR_RXERR 0x0001 /* RX error event */ + +/* LED control register */ +#define CIPHY_MII_LED 0x1B +#define CIPHY_LED_LINK10FORCE 0x8000 /* Force on link10 LED */ +#define CIPHY_LED_LINK10DIS 0x4000 /* Disable link10 LED */ +#define CIPHY_LED_LINK100FORCE 0x2000 /* Force on link10 LED */ +#define CIPHY_LED_LINK100DIS 0x1000 /* Disable link100 LED */ +#define CIPHY_LED_LINK1000FORCE 0x0800 /* Force on link1000 LED */ +#define CIPHY_LED_LINK1000DIS 0x0400 /* Disable link1000 LED */ +#define CIPHY_LED_FDXFORCE 0x0200 /* Force on duplex LED */ +#define CIPHY_LED_FDXDIS 0x0100 /* Disable duplex LED */ +#define CIPHY_LED_ACTFORCE 0x0080 /* Force on activity LED */ +#define CIPHY_LED_ACTDIS 0x0040 /* Disable activity LED */ +#define CIPHY_LED_PULSE 0x0008 /* LED pulse enable */ +#define CIPHY_LED_LINKACTBLINK 0x0004 /* enable link/activity LED blink */ +#define CIPHY_LED_BLINKRATE 0x0002 /* blink rate 0=10hz, 1=5hz */ + +/* Auxilliary control and status register */ +#define CIPHY_MII_AUXCSR 0x1C +#define CIPHY_AUXCSR_ANEGDONE 0x8000 /* Autoneg complete */ +#define CIPHY_AUXCSR_ANEGOFF 0x4000 /* Autoneg disabled */ +#define CIPHY_AUXCSR_XOVER 0x2000 /* MDI/MDI-X crossover indication */ +#define CIPHY_AUXCSR_PAIRSWAP 0x1000 /* pair swap indication */ +#define CIPHY_AUXCSR_APOLARITY 0x0800 /* polarity inversion pair A */ +#define CIPHY_AUXCSR_BPOLARITY 0x0400 /* polarity inversion pair B */ +#define CIPHY_AUXCSR_CPOLARITY 0x0200 /* polarity inversion pair C */ +#define CIPHY_AUXCSR_DPOLARITY 0x0100 /* polarity inversion pair D */ +#define CIPHY_AUXCSR_FDX 0x0020 /* duplex 1=full, 0=half */ +#define CIPHY_AUXCSR_SPEED 0x0018 /* speed */ +#define CIPHY_AUXCSR_MDPPS 0x0004 /* No idea, not documented */ +#define CIPHY_AUXCSR_STICKYREST 0x0002 /* reset clears sticky bits */ + +#define CIPHY_SPEED10 0x0000 +#define CIPHY_SPEED100 0x0008 +#define CIPHY_SPEED1000 0x0010 + +/* Delay skew status register */ +#define CIPHY_MII_DSKEW 0x1D +#define CIPHY_DSKEW_PAIRA 0x7000 /* Pair A skew in symbol times */ +#define CIPHY_DSKEW_PAIRB 0x0700 /* Pair B skew in symbol times */ +#define CIPHY_DSKEW_PAIRC 0x0070 /* Pair C skew in symbol times */ +#define CIPHY_DSKEW_PAIRD 0x0007 /* Pair D skew in symbol times */ + +#endif /* _DEV_CIPHY_MIIREG_H_ */ diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/mii/miidevs.h b/src/add-ons/kernel/drivers/network/nforce/dev/mii/miidevs.h new file mode 100644 index 0000000000..e9838bf297 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/mii/miidevs.h @@ -0,0 +1,21 @@ +/* + * Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved. + * Distributed under the terms of the MIT License. + */ +#ifndef _FBSD_MII_DEVS_H +#define _FBSD_MII_DEVS_H + +#define MII_OUI_CICADA 0x0003f1 +#define MII_OUI_VITESSE 0x0001c1 + +#define MII_MODEL_CICADA_CS8201 0x0001 +#define MII_MODEL_CICADA_CS8201A 0x0020 +#define MII_MODEL_CICADA_CS8201B 0x0021 +#define MII_MODEL_VITESSE_VSC8601 0x0002 + +#define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000TX PHY" +#define MII_STR_CICADA_CS8201A MII_STR_CICADA_CS8201 +#define MII_STR_CICADA_CS8201B MII_STR_CICADA_CS8201 +#define MII_STR_VITESSE_VSC8601 "Vitesse VSC8601 10/100/1000TX PHY" + +#endif /* _FBSD_MII_DEVS_H */ diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy.c b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy.c new file mode 100644 index 0000000000..10347825bf --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy.c @@ -0,0 +1,220 @@ +/* $NetBSD: ukphy.c,v 1.2 1999/04/23 04:24:32 thorpej Exp $ */ + +/*- + * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center, and by Frank van der Linden. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1997 Manuel Bouyer. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Manuel Bouyer. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy.c,v 1.20 2007/01/20 00:52:29 marius Exp $"); + +/* + * driver for generic unknown PHYs + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "miibus_if.h" + +static int ukphy_probe(device_t); +static int ukphy_attach(device_t); + +static device_method_t ukphy_methods[] = { + /* device interface */ + DEVMETHOD(device_probe, ukphy_probe), + DEVMETHOD(device_attach, ukphy_attach), + DEVMETHOD(device_detach, mii_phy_detach), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + { 0, 0 } +}; + +static devclass_t ukphy_devclass; + +static driver_t ukphy_driver = { + "ukphy", + ukphy_methods, + sizeof(struct mii_softc) +}; + +DRIVER_MODULE(ukphy, miibus, ukphy_driver, ukphy_devclass, 0, 0); + +static int ukphy_service(struct mii_softc *, struct mii_data *, int); + +static int +ukphy_probe(device_t dev) +{ + + /* + * We know something is here, so always match at a low priority. + */ + device_set_desc(dev, "Generic IEEE 802.3u media interface"); + return (BUS_PROBE_GENERIC); +} + +static int +ukphy_attach(device_t dev) +{ + struct mii_softc *sc; + struct mii_attach_args *ma; + struct mii_data *mii; + + sc = device_get_softc(dev); + ma = device_get_ivars(dev); + sc->mii_dev = device_get_parent(dev); + mii = device_get_softc(sc->mii_dev); + LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); + + if (bootverbose) + device_printf(dev, "OUI 0x%06x, model 0x%04x, rev. %d\n", + MII_OUI(ma->mii_id1, ma->mii_id2), + MII_MODEL(ma->mii_id2), MII_REV(ma->mii_id2)); + + sc->mii_inst = mii->mii_instance; + sc->mii_phy = ma->mii_phyno; + sc->mii_service = ukphy_service; + sc->mii_pdata = mii; + + mii->mii_instance++; + + mii_phy_reset(sc); + + sc->mii_capabilities = + PHY_READ(sc, MII_BMSR) & ma->mii_capmask; + if (sc->mii_capabilities & BMSR_EXTSTAT) + sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); + device_printf(dev, " "); + mii_phy_add_media(sc); + printf("\n"); + + MIIBUS_MEDIAINIT(sc->mii_dev); + mii_phy_setmedia(sc); + + return (0); +} + +static int +ukphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) +{ + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int reg; + + switch (cmd) { + case MII_POLLSTAT: + /* + * If we're not polling our PHY instance, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + break; + + case MII_MEDIACHG: + /* + * If the media indicates a different PHY instance, + * isolate ourselves. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) { + reg = PHY_READ(sc, MII_BMCR); + PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO); + return (0); + } + + /* + * If the interface is not up, don't do anything. + */ + if ((mii->mii_ifp->if_flags & IFF_UP) == 0) + break; + + mii_phy_setmedia(sc); + break; + + case MII_TICK: + /* + * If we're not currently selected, just return. + */ + if (IFM_INST(ife->ifm_media) != sc->mii_inst) + return (0); + if (mii_phy_tick(sc) == EJUSTRETURN) + return (0); + break; + } + + /* Update the media status. */ + ukphy_status(sc); + + /* Callback if something changed. */ + mii_phy_update(sc, cmd); + return (0); +} diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy_subr.c b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy_subr.c new file mode 100644 index 0000000000..884a3a2674 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/mii/ukphy_subr.c @@ -0,0 +1,129 @@ +/* $NetBSD: ukphy_subr.c,v 1.2 1998/11/05 04:08:02 thorpej Exp $ */ + +/*- + * Copyright (c) 1998 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center, and by Frank van der Linden. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/mii/ukphy_subr.c,v 1.9 2006/05/19 03:51:42 yongari Exp $"); + +/* + * Subroutines shared by the ukphy driver and other PHY drivers. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "miibus_if.h" + +/* + * Media status subroutine. If a PHY driver does media detection simply + * by decoding the NWay autonegotiation, use this routine. + */ +void +ukphy_status(struct mii_softc *phy) +{ + struct mii_data *mii = phy->mii_pdata; + struct ifmedia_entry *ife = mii->mii_media.ifm_cur; + int bmsr, bmcr, anlpar, gtcr, gtsr; + + mii->mii_media_status = IFM_AVALID; + mii->mii_media_active = IFM_ETHER; + + bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR); + if (bmsr & BMSR_LINK) + mii->mii_media_status |= IFM_ACTIVE; + + bmcr = PHY_READ(phy, MII_BMCR); + if (bmcr & BMCR_ISO) { + mii->mii_media_active |= IFM_NONE; + mii->mii_media_status = 0; + return; + } + + if (bmcr & BMCR_LOOP) + mii->mii_media_active |= IFM_LOOP; + + if (bmcr & BMCR_AUTOEN) { + /* + * NWay autonegotiation takes the highest-order common + * bit of the ANAR and ANLPAR (i.e. best media advertised + * both by us and our link partner). + */ + if ((bmsr & BMSR_ACOMP) == 0) { + /* Erg, still trying, I guess... */ + mii->mii_media_active |= IFM_NONE; + return; + } + + anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR); + if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 && + (phy->mii_extcapabilities & + (EXTSR_1000THDX | EXTSR_1000TFDX)) != 0) { + gtcr = PHY_READ(phy, MII_100T2CR); + gtsr = PHY_READ(phy, MII_100T2SR); + } else + gtcr = gtsr = 0; + + if ((gtcr & GTCR_ADV_1000TFDX) && (gtsr & GTSR_LP_1000TFDX)) + mii->mii_media_active |= IFM_1000_T|IFM_FDX; + else if ((gtcr & GTCR_ADV_1000THDX) && + (gtsr & GTSR_LP_1000THDX)) + mii->mii_media_active |= IFM_1000_T; + else if (anlpar & ANLPAR_T4) + mii->mii_media_active |= IFM_100_T4; + else if (anlpar & ANLPAR_TX_FD) + mii->mii_media_active |= IFM_100_TX|IFM_FDX; + else if (anlpar & ANLPAR_TX) + mii->mii_media_active |= IFM_100_TX; + else if (anlpar & ANLPAR_10_FD) + mii->mii_media_active |= IFM_10_T|IFM_FDX; + else if (anlpar & ANLPAR_10) + mii->mii_media_active |= IFM_10_T; + else + mii->mii_media_active |= IFM_NONE; + } else + mii->mii_media_active = ife->ifm_media; +} diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/Jamfile b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/Jamfile new file mode 100644 index 0000000000..3cdf9d36ab --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/Jamfile @@ -0,0 +1,15 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network nforce dev nfe ; + +UsePrivateHeaders kernel net ; + +UseHeaders [ FDirName $(SUBDIR) .. .. ] : true ; +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] ; + +KernelAddon nforce : + if_nfe.c + + glue.c + : libfreebsd_network.a nforce_mii.a + ; diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/glue.c b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/glue.c new file mode 100644 index 0000000000..68c4d453c9 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/glue.c @@ -0,0 +1,31 @@ +/* + * Copyright 2007, Axel Dörfler, axeld@pinc-software.de. All Rights Reserved. + * Distributed under the terms of the MIT License. + */ + + +#include + + +HAIKU_FBSD_DRIVER_GLUE(nforce, nfe, pci) + +HAIKU_DRIVER_REQUIREMENTS(FBSD_TASKQUEUES | FBSD_FAST_TASKQUEUE); +NO_HAIKU_CHECK_DISABLE_INTERRUPTS(); +NO_HAIKU_REENABLE_INTERRUPTS(); + +extern driver_t *DRIVER_MODULE_NAME(ciphy, miibus); +extern driver_t *DRIVER_MODULE_NAME(ukphy, miibus); + + +driver_t * +__haiku_select_miibus_driver(device_t dev) +{ + driver_t *drivers[] = { + DRIVER_MODULE_NAME(ciphy, miibus), + DRIVER_MODULE_NAME(ukphy, miibus), + NULL + }; + + return __haiku_probe_miibus(dev, drivers); +} + diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c new file mode 100644 index 0000000000..1412e6f07d --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfe.c @@ -0,0 +1,3218 @@ +/* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */ + +/*- + * Copyright (c) 2006 Shigeaki Tagashira + * Copyright (c) 2006 Damien Bergamini + * Copyright (c) 2005, 2006 Jonathan Gray + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ + +#include +__FBSDID("$FreeBSD: src/sys/dev/nfe/if_nfe.c,v 1.21 2007/09/14 05:12:25 yongari Exp $"); + +#ifdef HAVE_KERNEL_OPTION_HEADERS +#include "opt_device_polling.h" +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +MODULE_DEPEND(nfe, pci, 1, 1, 1); +MODULE_DEPEND(nfe, ether, 1, 1, 1); +MODULE_DEPEND(nfe, miibus, 1, 1, 1); + +/* "device miibus" required. See GENERIC if you get errors here. */ +#include "miibus_if.h" + +static int nfe_probe(device_t); +static int nfe_attach(device_t); +static int nfe_detach(device_t); +static int nfe_suspend(device_t); +static int nfe_resume(device_t); +static void nfe_shutdown(device_t); +static void nfe_power(struct nfe_softc *); +static int nfe_miibus_readreg(device_t, int, int); +static int nfe_miibus_writereg(device_t, int, int, int); +static void nfe_miibus_statchg(device_t); +static void nfe_link_task(void *, int); +static void nfe_set_intr(struct nfe_softc *); +static __inline void nfe_enable_intr(struct nfe_softc *); +static __inline void nfe_disable_intr(struct nfe_softc *); +static int nfe_ioctl(struct ifnet *, u_long, caddr_t); +static void nfe_alloc_msix(struct nfe_softc *, int); +static int nfe_intr(void *); +static void nfe_int_task(void *, int); +static void *nfe_jalloc(struct nfe_softc *); +static void nfe_jfree(void *, void *); +static __inline void nfe_discard_rxbuf(struct nfe_softc *, int); +static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int); +static int nfe_newbuf(struct nfe_softc *, int); +static int nfe_jnewbuf(struct nfe_softc *, int); +static int nfe_rxeof(struct nfe_softc *, int); +static int nfe_jrxeof(struct nfe_softc *, int); +static void nfe_txeof(struct nfe_softc *); +static struct mbuf *nfe_defrag(struct mbuf *, int, int); +static int nfe_encap(struct nfe_softc *, struct mbuf **); +static void nfe_setmulti(struct nfe_softc *); +static void nfe_tx_task(void *, int); +static void nfe_start(struct ifnet *); +static void nfe_watchdog(struct ifnet *); +static void nfe_init(void *); +static void nfe_init_locked(void *); +static void nfe_stop(struct ifnet *); +static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); +static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); +static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); +static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); +static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); +static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); +static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); +static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); +static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); +static int nfe_ifmedia_upd(struct ifnet *); +static void nfe_ifmedia_sts(struct ifnet *, struct ifmediareq *); +static void nfe_tick(void *); +static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); +static void nfe_set_macaddr(struct nfe_softc *, uint8_t *); +static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int); + +static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); +static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS); + +#ifdef NFE_DEBUG +static int nfedebug = 0; +#define DPRINTF(sc, ...) do { \ + if (nfedebug) \ + device_printf((sc)->nfe_dev, __VA_ARGS__); \ +} while (0) +#define DPRINTFN(sc, n, ...) do { \ + if (nfedebug >= (n)) \ + device_printf((sc)->nfe_dev, __VA_ARGS__); \ +} while (0) +#else +#define DPRINTF(sc, ...) +#define DPRINTFN(sc, n, ...) +#endif + +#define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx) +#define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx) +#define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED) + +#define NFE_JLIST_LOCK(_sc) mtx_lock(&(_sc)->nfe_jlist_mtx) +#define NFE_JLIST_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_jlist_mtx) + +/* Tunables. */ +static int msi_disable = 0; +static int msix_disable = 0; +static int jumbo_disable = 0; +TUNABLE_INT("hw.nfe.msi_disable", &msi_disable); +TUNABLE_INT("hw.nfe.msix_disable", &msix_disable); +TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable); + +static device_method_t nfe_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, nfe_probe), + DEVMETHOD(device_attach, nfe_attach), + DEVMETHOD(device_detach, nfe_detach), + DEVMETHOD(device_suspend, nfe_suspend), + DEVMETHOD(device_resume, nfe_resume), + DEVMETHOD(device_shutdown, nfe_shutdown), + + /* bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + DEVMETHOD(bus_driver_added, bus_generic_driver_added), + + /* MII interface */ + DEVMETHOD(miibus_readreg, nfe_miibus_readreg), + DEVMETHOD(miibus_writereg, nfe_miibus_writereg), + DEVMETHOD(miibus_statchg, nfe_miibus_statchg), + + { NULL, NULL } +}; + +static driver_t nfe_driver = { + "nfe", + nfe_methods, + sizeof(struct nfe_softc) +}; + +static devclass_t nfe_devclass; + +DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0); +DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); + +static struct nfe_type nfe_devs[] = { + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, + "NVIDIA nForce MCP Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, + "NVIDIA nForce2 MCP2 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1, + "NVIDIA nForce2 400 MCP4 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2, + "NVIDIA nForce2 400 MCP5 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, + "NVIDIA nForce3 MCP3 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN, + "NVIDIA nForce3 250 MCP6 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, + "NVIDIA nForce3 MCP7 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1, + "NVIDIA nForce4 CK804 MCP8 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2, + "NVIDIA nForce4 CK804 MCP9 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, + "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */ + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, + "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */ + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1, + "NVIDIA nForce 430 MCP12 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2, + "NVIDIA nForce 430 MCP13 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, + "NVIDIA nForce MCP55 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, + "NVIDIA nForce MCP55 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, + "NVIDIA nForce MCP61 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, + "NVIDIA nForce MCP61 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, + "NVIDIA nForce MCP61 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, + "NVIDIA nForce MCP61 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, + "NVIDIA nForce MCP65 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, + "NVIDIA nForce MCP65 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, + "NVIDIA nForce MCP65 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, + "NVIDIA nForce MCP65 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, + "NVIDIA nForce MCP67 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, + "NVIDIA nForce MCP67 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, + "NVIDIA nForce MCP67 Networking Adapter"}, + {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, + "NVIDIA nForce MCP67 Networking Adapter"}, + {0, 0, NULL} +}; + + +/* Probe for supported hardware ID's */ +static int +nfe_probe(device_t dev) +{ + struct nfe_type *t; + + t = nfe_devs; + /* Check for matching PCI DEVICE ID's */ + while (t->name != NULL) { + if ((pci_get_vendor(dev) == t->vid_id) && + (pci_get_device(dev) == t->dev_id)) { + device_set_desc(dev, t->name); + return (BUS_PROBE_DEFAULT); + } + t++; + } + + return (ENXIO); +} + +static void +nfe_alloc_msix(struct nfe_softc *sc, int count) +{ + int rid; + + rid = PCIR_BAR(2); + sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY, + &rid, RF_ACTIVE); + if (sc->nfe_msix_res == NULL) { + device_printf(sc->nfe_dev, + "couldn't allocate MSIX table resource\n"); + return; + } + rid = PCIR_BAR(3); + sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev, + SYS_RES_MEMORY, &rid, RF_ACTIVE); + if (sc->nfe_msix_pba_res == NULL) { + device_printf(sc->nfe_dev, + "couldn't allocate MSIX PBA resource\n"); + bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2), + sc->nfe_msix_res); + sc->nfe_msix_res = NULL; + return; + } + + if (pci_alloc_msix(sc->nfe_dev, &count) == 0) { + if (count == NFE_MSI_MESSAGES) { + if (bootverbose) + device_printf(sc->nfe_dev, + "Using %d MSIX messages\n", count); + sc->nfe_msix = 1; + } else { + if (bootverbose) + device_printf(sc->nfe_dev, + "couldn't allocate MSIX\n"); + pci_release_msi(sc->nfe_dev); + bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, + PCIR_BAR(3), sc->nfe_msix_pba_res); + bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, + PCIR_BAR(2), sc->nfe_msix_res); + sc->nfe_msix_pba_res = NULL; + sc->nfe_msix_res = NULL; + } + } +} + +static int +nfe_attach(device_t dev) +{ + struct nfe_softc *sc; + struct ifnet *ifp; + bus_addr_t dma_addr_max; + int error = 0, i, msic, reg, rid; + + sc = device_get_softc(dev); + sc->nfe_dev = dev; + + mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF); + mtx_init(&sc->nfe_jlist_mtx, "nfe_jlist_mtx", NULL, MTX_DEF); + callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0); + TASK_INIT(&sc->nfe_link_task, 0, nfe_link_task, sc); + SLIST_INIT(&sc->nfe_jfree_listhead); + SLIST_INIT(&sc->nfe_jinuse_listhead); + + pci_enable_busmaster(dev); + + rid = PCIR_BAR(0); + sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->nfe_res[0] == NULL) { + device_printf(dev, "couldn't map memory resources\n"); + mtx_destroy(&sc->nfe_mtx); + return (ENXIO); + } + + if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { + uint16_t v, width; + + v = pci_read_config(dev, reg + 0x08, 2); + /* Change max. read request size to 4096. */ + v &= ~(7 << 12); + v |= (5 << 12); + pci_write_config(dev, reg + 0x08, v, 2); + + v = pci_read_config(dev, reg + 0x0c, 2); + /* link capability */ + v = (v >> 4) & 0x0f; + width = pci_read_config(dev, reg + 0x12, 2); + /* negotiated link width */ + width = (width >> 4) & 0x3f; + if (v != width) + device_printf(sc->nfe_dev, + "warning, negotiated width of link(x%d) != " + "max. width of link(x%d)\n", width, v); + } + + /* Allocate interrupt */ + if (msix_disable == 0 || msi_disable == 0) { + if (msix_disable == 0 && + (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES) + nfe_alloc_msix(sc, msic); + if (msi_disable == 0 && sc->nfe_msix == 0 && + (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES && + pci_alloc_msi(dev, &msic) == 0) { + if (msic == NFE_MSI_MESSAGES) { + if (bootverbose) + device_printf(dev, + "Using %d MSI messages\n", msic); + sc->nfe_msi = 1; + } else + pci_release_msi(dev); + } + } + + if (sc->nfe_msix == 0 && sc->nfe_msi == 0) { + rid = 0; + sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->nfe_irq[0] == NULL) { + device_printf(dev, "couldn't allocate IRQ resources\n"); + error = ENXIO; + goto fail; + } + } else { + for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { + sc->nfe_irq[i] = bus_alloc_resource_any(dev, + SYS_RES_IRQ, &rid, RF_ACTIVE); + if (sc->nfe_irq[i] == NULL) { + device_printf(dev, + "couldn't allocate IRQ resources for " + "message %d\n", rid); + error = ENXIO; + goto fail; + } + } + /* Map interrupts to vector 0. */ + if (sc->nfe_msix != 0) { + NFE_WRITE(sc, NFE_MSIX_MAP0, 0); + NFE_WRITE(sc, NFE_MSIX_MAP1, 0); + } else if (sc->nfe_msi != 0) { + NFE_WRITE(sc, NFE_MSI_MAP0, 0); + NFE_WRITE(sc, NFE_MSI_MAP1, 0); + } + } + + /* Set IRQ status/mask register. */ + sc->nfe_irq_status = NFE_IRQ_STATUS; + sc->nfe_irq_mask = NFE_IRQ_MASK; + sc->nfe_intrs = NFE_IRQ_WANTED; + sc->nfe_nointrs = 0; + if (sc->nfe_msix != 0) { + sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS; + sc->nfe_nointrs = NFE_IRQ_WANTED; + } else if (sc->nfe_msi != 0) { + sc->nfe_irq_mask = NFE_MSI_IRQ_MASK; + sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED; + } + + sc->nfe_devid = pci_get_device(dev); + sc->nfe_revid = pci_get_revid(dev); + sc->nfe_flags = 0; + + switch (sc->nfe_devid) { + case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: + case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: + case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: + case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: + sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; + break; + case PCI_PRODUCT_NVIDIA_MCP51_LAN1: + case PCI_PRODUCT_NVIDIA_MCP51_LAN2: + sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT; + break; + case PCI_PRODUCT_NVIDIA_CK804_LAN1: + case PCI_PRODUCT_NVIDIA_CK804_LAN2: + case PCI_PRODUCT_NVIDIA_MCP04_LAN1: + case PCI_PRODUCT_NVIDIA_MCP04_LAN2: + sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM; + break; + case PCI_PRODUCT_NVIDIA_MCP55_LAN1: + case PCI_PRODUCT_NVIDIA_MCP55_LAN2: + sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | + NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL; + break; + + case PCI_PRODUCT_NVIDIA_MCP61_LAN1: + case PCI_PRODUCT_NVIDIA_MCP61_LAN2: + case PCI_PRODUCT_NVIDIA_MCP61_LAN3: + case PCI_PRODUCT_NVIDIA_MCP61_LAN4: + case PCI_PRODUCT_NVIDIA_MCP67_LAN1: + case PCI_PRODUCT_NVIDIA_MCP67_LAN2: + case PCI_PRODUCT_NVIDIA_MCP67_LAN3: + case PCI_PRODUCT_NVIDIA_MCP67_LAN4: + sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | + NFE_TX_FLOW_CTRL; + break; + case PCI_PRODUCT_NVIDIA_MCP65_LAN1: + case PCI_PRODUCT_NVIDIA_MCP65_LAN2: + case PCI_PRODUCT_NVIDIA_MCP65_LAN3: + case PCI_PRODUCT_NVIDIA_MCP65_LAN4: + sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | + NFE_PWR_MGMT | NFE_TX_FLOW_CTRL; + break; + } + + nfe_power(sc); + /* Check for reversed ethernet address */ + if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) + sc->nfe_flags |= NFE_CORRECT_MACADDR; + nfe_get_macaddr(sc, sc->eaddr); + /* + * Allocate the parent bus DMA tag appropriate for PCI. + */ + dma_addr_max = BUS_SPACE_MAXADDR_32BIT; + if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0) + dma_addr_max = NFE_DMA_MAXADDR; + error = bus_dma_tag_create( + bus_get_dma_tag(sc->nfe_dev), /* parent */ + 1, 0, /* alignment, boundary */ + dma_addr_max, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->nfe_parent_tag); + if (error) + goto fail; + + ifp = sc->nfe_ifp = if_alloc(IFT_ETHER); + if (ifp == NULL) { + device_printf(dev, "can not if_alloc()\n"); + error = ENOSPC; + goto fail; + } + TASK_INIT(&sc->nfe_tx_task, 1, nfe_tx_task, ifp); + + /* + * Allocate Tx and Rx rings. + */ + if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0) + goto fail; + + if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0) + goto fail; + + nfe_alloc_jrx_ring(sc, &sc->jrxq); + + SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), + OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, + &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I", + "max number of Rx events to process"); + + sc->nfe_process_limit = NFE_PROC_DEFAULT; + error = resource_int_value(device_get_name(dev), device_get_unit(dev), + "process_limit", &sc->nfe_process_limit); + if (error == 0) { + if (sc->nfe_process_limit < NFE_PROC_MIN || + sc->nfe_process_limit > NFE_PROC_MAX) { + device_printf(dev, "process_limit value out of range; " + "using default: %d\n", NFE_PROC_DEFAULT); + sc->nfe_process_limit = NFE_PROC_DEFAULT; + } + } + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_mtu = ETHERMTU; + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_ioctl = nfe_ioctl; + ifp->if_start = nfe_start; + ifp->if_hwassist = 0; + ifp->if_capabilities = 0; + ifp->if_watchdog = NULL; + ifp->if_init = nfe_init; + IFQ_SET_MAXLEN(&ifp->if_snd, NFE_TX_RING_COUNT - 1); + ifp->if_snd.ifq_drv_maxlen = NFE_TX_RING_COUNT - 1; + IFQ_SET_READY(&ifp->if_snd); + + if (sc->nfe_flags & NFE_HW_CSUM) { + ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4; + ifp->if_hwassist |= NFE_CSUM_FEATURES | CSUM_TSO; + } + ifp->if_capenable = ifp->if_capabilities; + + sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; + /* VLAN capability setup. */ + ifp->if_capabilities |= IFCAP_VLAN_MTU; + if ((sc->nfe_flags & NFE_HW_VLAN) != 0) { + ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; + if ((ifp->if_capabilities & IFCAP_HWCSUM) != 0) + ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; + } + ifp->if_capenable = ifp->if_capabilities; + + /* + * Tell the upper layer(s) we support long frames. + * Must appear after the call to ether_ifattach() because + * ether_ifattach() sets ifi_hdrlen to the default value. + */ + ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); + +#ifdef DEVICE_POLLING + ifp->if_capabilities |= IFCAP_POLLING; +#endif + + /* Do MII setup */ + if (mii_phy_probe(dev, &sc->nfe_miibus, nfe_ifmedia_upd, + nfe_ifmedia_sts)) { + device_printf(dev, "MII without any phy!\n"); + error = ENXIO; + goto fail; + } + ether_ifattach(ifp, sc->eaddr); + + TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc); + sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK, + taskqueue_thread_enqueue, &sc->nfe_tq); + taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq", + device_get_nameunit(sc->nfe_dev)); + error = 0; + if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { + error = bus_setup_intr(dev, sc->nfe_irq[0], + INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, + &sc->nfe_intrhand[0]); + } else { + for (i = 0; i < NFE_MSI_MESSAGES; i++) { + error = bus_setup_intr(dev, sc->nfe_irq[i], + INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, + &sc->nfe_intrhand[i]); + if (error != 0) + break; + } + } + if (error) { + device_printf(dev, "couldn't set up irq\n"); + taskqueue_free(sc->nfe_tq); + sc->nfe_tq = NULL; + ether_ifdetach(ifp); + goto fail; + } + +fail: + if (error) + nfe_detach(dev); + + return (error); +} + + +static int +nfe_detach(device_t dev) +{ + struct nfe_softc *sc; + struct ifnet *ifp; + uint8_t eaddr[ETHER_ADDR_LEN]; + int i, rid; + + sc = device_get_softc(dev); + KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized")); + ifp = sc->nfe_ifp; + +#ifdef DEVICE_POLLING + if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) + ether_poll_deregister(ifp); +#endif + if (device_is_attached(dev)) { + NFE_LOCK(sc); + nfe_stop(ifp); + ifp->if_flags &= ~IFF_UP; + NFE_UNLOCK(sc); + callout_drain(&sc->nfe_stat_ch); + taskqueue_drain(taskqueue_fast, &sc->nfe_tx_task); + taskqueue_drain(taskqueue_swi, &sc->nfe_link_task); + ether_ifdetach(ifp); + } + + if (ifp) { + /* restore ethernet address */ + if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { + for (i = 0; i < ETHER_ADDR_LEN; i++) { + eaddr[i] = sc->eaddr[5 - i]; + } + } else + bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN); + nfe_set_macaddr(sc, eaddr); + if_free(ifp); + } + if (sc->nfe_miibus) + device_delete_child(dev, sc->nfe_miibus); + bus_generic_detach(dev); + if (sc->nfe_tq != NULL) { + taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task); + taskqueue_free(sc->nfe_tq); + sc->nfe_tq = NULL; + } + + for (i = 0; i < NFE_MSI_MESSAGES; i++) { + if (sc->nfe_intrhand[i] != NULL) { + bus_teardown_intr(dev, sc->nfe_irq[i], + sc->nfe_intrhand[i]); + sc->nfe_intrhand[i] = NULL; + } + } + + if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { + if (sc->nfe_irq[0] != NULL) + bus_release_resource(dev, SYS_RES_IRQ, 0, + sc->nfe_irq[0]); + } else { + for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { + if (sc->nfe_irq[i] != NULL) { + bus_release_resource(dev, SYS_RES_IRQ, rid, + sc->nfe_irq[i]); + sc->nfe_irq[i] = NULL; + } + } + pci_release_msi(dev); + } + if (sc->nfe_msix_pba_res != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3), + sc->nfe_msix_pba_res); + sc->nfe_msix_pba_res = NULL; + } + if (sc->nfe_msix_res != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2), + sc->nfe_msix_res); + sc->nfe_msix_res = NULL; + } + if (sc->nfe_res[0] != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), + sc->nfe_res[0]); + sc->nfe_res[0] = NULL; + } + + nfe_free_tx_ring(sc, &sc->txq); + nfe_free_rx_ring(sc, &sc->rxq); + nfe_free_jrx_ring(sc, &sc->jrxq); + + if (sc->nfe_parent_tag) { + bus_dma_tag_destroy(sc->nfe_parent_tag); + sc->nfe_parent_tag = NULL; + } + + mtx_destroy(&sc->nfe_jlist_mtx); + mtx_destroy(&sc->nfe_mtx); + + return (0); +} + + +static int +nfe_suspend(device_t dev) +{ + struct nfe_softc *sc; + + sc = device_get_softc(dev); + + NFE_LOCK(sc); + nfe_stop(sc->nfe_ifp); + sc->nfe_suspended = 1; + NFE_UNLOCK(sc); + + return (0); +} + + +static int +nfe_resume(device_t dev) +{ + struct nfe_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + + NFE_LOCK(sc); + ifp = sc->nfe_ifp; + if (ifp->if_flags & IFF_UP) + nfe_init_locked(sc); + sc->nfe_suspended = 0; + NFE_UNLOCK(sc); + + return (0); +} + + +/* Take PHY/NIC out of powerdown, from Linux */ +static void +nfe_power(struct nfe_softc *sc) +{ + uint32_t pwr; + + if ((sc->nfe_flags & NFE_PWR_MGMT) == 0) + return; + NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); + NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); + DELAY(100); + NFE_WRITE(sc, NFE_MAC_RESET, 0); + DELAY(100); + NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); + pwr = NFE_READ(sc, NFE_PWR2_CTL); + pwr &= ~NFE_PWR2_WAKEUP_MASK; + if (sc->nfe_revid >= 0xa3 && + (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 || + sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2)) + pwr |= NFE_PWR2_REVA3; + NFE_WRITE(sc, NFE_PWR2_CTL, pwr); +} + + +static void +nfe_miibus_statchg(device_t dev) +{ + struct nfe_softc *sc; + + sc = device_get_softc(dev); + taskqueue_enqueue(taskqueue_swi, &sc->nfe_link_task); +} + + +static void +nfe_link_task(void *arg, int pending) +{ + struct nfe_softc *sc; + struct mii_data *mii; + struct ifnet *ifp; + uint32_t phy, seed, misc = NFE_MISC1_MAGIC, link = NFE_MEDIA_SET; + uint32_t gmask, rxctl, txctl, val; + + sc = (struct nfe_softc *)arg; + + NFE_LOCK(sc); + + mii = device_get_softc(sc->nfe_miibus); + ifp = sc->nfe_ifp; + if (mii == NULL || ifp == NULL) { + NFE_UNLOCK(sc); + return; + } + + if (mii->mii_media_status & IFM_ACTIVE) { + if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) + sc->nfe_link = 1; + } else + sc->nfe_link = 0; + + phy = NFE_READ(sc, NFE_PHY_IFACE); + phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); + + seed = NFE_READ(sc, NFE_RNDSEED); + seed &= ~NFE_SEED_MASK; + + if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) { + phy |= NFE_PHY_HDX; /* half-duplex */ + misc |= NFE_MISC1_HDX; + } + + switch (IFM_SUBTYPE(mii->mii_media_active)) { + case IFM_1000_T: /* full-duplex only */ + link |= NFE_MEDIA_1000T; + seed |= NFE_SEED_1000T; + phy |= NFE_PHY_1000T; + break; + case IFM_100_TX: + link |= NFE_MEDIA_100TX; + seed |= NFE_SEED_100TX; + phy |= NFE_PHY_100TX; + break; + case IFM_10_T: + link |= NFE_MEDIA_10T; + seed |= NFE_SEED_10T; + break; + } + + if ((phy & 0x10000000) != 0) { + if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) + val = NFE_R1_MAGIC_1000; + else + val = NFE_R1_MAGIC_10_100; + } else + val = NFE_R1_MAGIC_DEFAULT; + NFE_WRITE(sc, NFE_SETUP_R1, val); + + NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ + + NFE_WRITE(sc, NFE_PHY_IFACE, phy); + NFE_WRITE(sc, NFE_MISC1, misc); + NFE_WRITE(sc, NFE_LINKSPEED, link); + + gmask = mii->mii_media_active & IFM_GMASK; + if ((gmask & IFM_FDX) != 0) { + /* It seems all hardwares supports Rx pause frames. */ + val = NFE_READ(sc, NFE_RXFILTER); + if ((gmask & IFM_FLAG0) != 0) + val |= NFE_PFF_RX_PAUSE; + else + val &= ~NFE_PFF_RX_PAUSE; + NFE_WRITE(sc, NFE_RXFILTER, val); + if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { + val = NFE_READ(sc, NFE_MISC1); + if ((gmask & IFM_FLAG1) != 0) { + NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, + NFE_TX_PAUSE_FRAME_ENABLE); + val |= NFE_MISC1_TX_PAUSE; + } else { + val &= ~NFE_MISC1_TX_PAUSE; + NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, + NFE_TX_PAUSE_FRAME_DISABLE); + } + NFE_WRITE(sc, NFE_MISC1, val); + } + } else { + /* disable rx/tx pause frames */ + val = NFE_READ(sc, NFE_RXFILTER); + val &= ~NFE_PFF_RX_PAUSE; + NFE_WRITE(sc, NFE_RXFILTER, val); + if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { + NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, + NFE_TX_PAUSE_FRAME_DISABLE); + val = NFE_READ(sc, NFE_MISC1); + val &= ~NFE_MISC1_TX_PAUSE; + NFE_WRITE(sc, NFE_MISC1, val); + } + } + + txctl = NFE_READ(sc, NFE_TX_CTL); + rxctl = NFE_READ(sc, NFE_RX_CTL); + if (sc->nfe_link != 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + txctl |= NFE_TX_START; + rxctl |= NFE_RX_START; + } else { + txctl &= ~NFE_TX_START; + rxctl &= ~NFE_RX_START; + } + NFE_WRITE(sc, NFE_TX_CTL, txctl); + NFE_WRITE(sc, NFE_RX_CTL, rxctl); + + NFE_UNLOCK(sc); +} + + +static int +nfe_miibus_readreg(device_t dev, int phy, int reg) +{ + struct nfe_softc *sc = device_get_softc(dev); + uint32_t val; + int ntries; + + NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); + + if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { + NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); + DELAY(100); + } + + NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); + + for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { + DELAY(100); + if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) + break; + } + if (ntries == NFE_TIMEOUT) { + DPRINTFN(sc, 2, "timeout waiting for PHY\n"); + return 0; + } + + if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { + DPRINTFN(sc, 2, "could not read PHY\n"); + return 0; + } + + val = NFE_READ(sc, NFE_PHY_DATA); + if (val != 0xffffffff && val != 0) + sc->mii_phyaddr = phy; + + DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); + + return (val); +} + + +static int +nfe_miibus_writereg(device_t dev, int phy, int reg, int val) +{ + struct nfe_softc *sc = device_get_softc(dev); + uint32_t ctl; + int ntries; + + NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); + + if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { + NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); + DELAY(100); + } + + NFE_WRITE(sc, NFE_PHY_DATA, val); + ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; + NFE_WRITE(sc, NFE_PHY_CTL, ctl); + + for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { + DELAY(100); + if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) + break; + } +#ifdef NFE_DEBUG + if (nfedebug >= 2 && ntries == NFE_TIMEOUT) + device_printf(sc->nfe_dev, "could not write to PHY\n"); +#endif + return (0); +} + +/* + * Allocate a jumbo buffer. + */ +static void * +nfe_jalloc(struct nfe_softc *sc) +{ + struct nfe_jpool_entry *entry; + + NFE_JLIST_LOCK(sc); + + entry = SLIST_FIRST(&sc->nfe_jfree_listhead); + + if (entry == NULL) { + NFE_JLIST_UNLOCK(sc); + return (NULL); + } + + SLIST_REMOVE_HEAD(&sc->nfe_jfree_listhead, jpool_entries); + SLIST_INSERT_HEAD(&sc->nfe_jinuse_listhead, entry, jpool_entries); + + NFE_JLIST_UNLOCK(sc); + + return (sc->jrxq.jslots[entry->slot]); +} + +/* + * Release a jumbo buffer. + */ +static void +nfe_jfree(void *buf, void *args) +{ + struct nfe_softc *sc; + struct nfe_jpool_entry *entry; + int i; + + /* Extract the softc struct pointer. */ + sc = (struct nfe_softc *)args; + KASSERT(sc != NULL, ("%s: can't find softc pointer!", __func__)); + + NFE_JLIST_LOCK(sc); + /* Calculate the slot this buffer belongs to. */ + i = ((vm_offset_t)buf + - (vm_offset_t)sc->jrxq.jpool) / NFE_JLEN; + KASSERT(i >= 0 && i < NFE_JSLOTS, + ("%s: asked to free buffer that we don't manage!", __func__)); + + entry = SLIST_FIRST(&sc->nfe_jinuse_listhead); + KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); + entry->slot = i; + SLIST_REMOVE_HEAD(&sc->nfe_jinuse_listhead, jpool_entries); + SLIST_INSERT_HEAD(&sc->nfe_jfree_listhead, entry, jpool_entries); + if (SLIST_EMPTY(&sc->nfe_jinuse_listhead)) + wakeup(sc); + + NFE_JLIST_UNLOCK(sc); +} + +struct nfe_dmamap_arg { + bus_addr_t nfe_busaddr; +}; + +static int +nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) +{ + struct nfe_dmamap_arg ctx; + struct nfe_rx_data *data; + void *desc; + int i, error, descsize; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->desc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->desc32; + descsize = sizeof (struct nfe_desc32); + } + + ring->cur = ring->next = 0; + + error = bus_dma_tag_create(sc->nfe_parent_tag, + NFE_RING_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ + NFE_RX_RING_COUNT * descsize, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &ring->rx_desc_tag); + if (error != 0) { + device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); + goto fail; + } + + /* allocate memory to desc */ + error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK | + BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map); + if (error != 0) { + device_printf(sc->nfe_dev, "could not create desc DMA map\n"); + goto fail; + } + if (sc->nfe_flags & NFE_40BIT_ADDR) + ring->desc64 = desc; + else + ring->desc32 = desc; + + /* map desc to device visible address space */ + ctx.nfe_busaddr = 0; + error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc, + NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); + if (error != 0) { + device_printf(sc->nfe_dev, "could not load desc DMA map\n"); + goto fail; + } + ring->physaddr = ctx.nfe_busaddr; + + error = bus_dma_tag_create(sc->nfe_parent_tag, + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + MCLBYTES, 1, /* maxsize, nsegments */ + MCLBYTES, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &ring->rx_data_tag); + if (error != 0) { + device_printf(sc->nfe_dev, "could not create Rx DMA tag\n"); + goto fail; + } + + error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create Rx DMA spare map\n"); + goto fail; + } + + /* + * Pre-allocate Rx buffers and populate Rx ring. + */ + for (i = 0; i < NFE_RX_RING_COUNT; i++) { + data = &sc->rxq.data[i]; + data->rx_data_map = NULL; + data->m = NULL; + error = bus_dmamap_create(ring->rx_data_tag, 0, + &data->rx_data_map); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create Rx DMA map\n"); + goto fail; + } + } + +fail: + return (error); +} + + +static void +nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) +{ + struct nfe_dmamap_arg ctx; + struct nfe_rx_data *data; + void *desc; + struct nfe_jpool_entry *entry; + uint8_t *ptr; + int i, error, descsize; + + if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) + return; + if (jumbo_disable != 0) { + device_printf(sc->nfe_dev, "disabling jumbo frame support\n"); + sc->nfe_jumbo_disable = 1; + return; + } + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->jdesc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->jdesc32; + descsize = sizeof (struct nfe_desc32); + } + + ring->jcur = ring->jnext = 0; + + /* Create DMA tag for jumbo Rx ring. */ + error = bus_dma_tag_create(sc->nfe_parent_tag, + NFE_RING_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */ + 1, /* nsegments */ + NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &ring->jrx_desc_tag); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create jumbo ring DMA tag\n"); + goto fail; + } + + /* Create DMA tag for jumbo buffer blocks. */ + error = bus_dma_tag_create(sc->nfe_parent_tag, + PAGE_SIZE, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + NFE_JMEM, /* maxsize */ + 1, /* nsegments */ + NFE_JMEM, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &ring->jrx_jumbo_tag); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create jumbo Rx buffer block DMA tag\n"); + goto fail; + } + + /* Create DMA tag for jumbo Rx buffers. */ + error = bus_dma_tag_create(sc->nfe_parent_tag, + PAGE_SIZE, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + NFE_JLEN, /* maxsize */ + 1, /* nsegments */ + NFE_JLEN, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &ring->jrx_data_tag); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create jumbo Rx buffer DMA tag\n"); + goto fail; + } + + /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ + error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK | + BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not allocate DMA'able memory for jumbo Rx ring\n"); + goto fail; + } + if (sc->nfe_flags & NFE_40BIT_ADDR) + ring->jdesc64 = desc; + else + ring->jdesc32 = desc; + + ctx.nfe_busaddr = 0; + error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc, + NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not load DMA'able memory for jumbo Rx ring\n"); + goto fail; + } + ring->jphysaddr = ctx.nfe_busaddr; + + /* Create DMA maps for jumbo Rx buffers. */ + error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create jumbo Rx DMA spare map\n"); + goto fail; + } + + for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { + data = &sc->jrxq.jdata[i]; + data->rx_data_map = NULL; + data->m = NULL; + error = bus_dmamap_create(ring->jrx_data_tag, 0, + &data->rx_data_map); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create jumbo Rx DMA map\n"); + goto fail; + } + } + + /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ + error = bus_dmamem_alloc(ring->jrx_jumbo_tag, (void **)&ring->jpool, + BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, + &ring->jrx_jumbo_map); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not allocate DMA'able memory for jumbo pool\n"); + goto fail; + } + + ctx.nfe_busaddr = 0; + error = bus_dmamap_load(ring->jrx_jumbo_tag, ring->jrx_jumbo_map, + ring->jpool, NFE_JMEM, nfe_dma_map_segs, &ctx, 0); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not load DMA'able memory for jumbo pool\n"); + goto fail; + } + + /* + * Now divide it up into 9K pieces and save the addresses + * in an array. + */ + ptr = ring->jpool; + for (i = 0; i < NFE_JSLOTS; i++) { + ring->jslots[i] = ptr; + ptr += NFE_JLEN; + entry = malloc(sizeof(struct nfe_jpool_entry), M_DEVBUF, + M_WAITOK); + if (entry == NULL) { + device_printf(sc->nfe_dev, + "no memory for jumbo buffers!\n"); + error = ENOMEM; + goto fail; + } + entry->slot = i; + SLIST_INSERT_HEAD(&sc->nfe_jfree_listhead, entry, + jpool_entries); + } + + return; + +fail: + /* + * Running without jumbo frame support is ok for most cases + * so don't fail on creating dma tag/map for jumbo frame. + */ + nfe_free_jrx_ring(sc, ring); + device_printf(sc->nfe_dev, "disabling jumbo frame support due to " + "resource shortage\n"); + sc->nfe_jumbo_disable = 1; +} + + +static int +nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) +{ + void *desc; + size_t descsize; + int i; + + ring->cur = ring->next = 0; + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->desc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->desc32; + descsize = sizeof (struct nfe_desc32); + } + bzero(desc, descsize * NFE_RX_RING_COUNT); + for (i = 0; i < NFE_RX_RING_COUNT; i++) { + if (nfe_newbuf(sc, i) != 0) + return (ENOBUFS); + } + + bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (0); +} + + +static int +nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) +{ + void *desc; + size_t descsize; + int i; + + ring->jcur = ring->jnext = 0; + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->jdesc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->jdesc32; + descsize = sizeof (struct nfe_desc32); + } + bzero(desc, descsize * NFE_RX_RING_COUNT); + for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { + if (nfe_jnewbuf(sc, i) != 0) + return (ENOBUFS); + } + + bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (0); +} + + +static void +nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) +{ + struct nfe_rx_data *data; + void *desc; + int i, descsize; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->desc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->desc32; + descsize = sizeof (struct nfe_desc32); + } + + for (i = 0; i < NFE_RX_RING_COUNT; i++) { + data = &ring->data[i]; + if (data->rx_data_map != NULL) { + bus_dmamap_destroy(ring->rx_data_tag, + data->rx_data_map); + data->rx_data_map = NULL; + } + if (data->m != NULL) { + m_freem(data->m); + data->m = NULL; + } + } + if (ring->rx_data_tag != NULL) { + if (ring->rx_spare_map != NULL) { + bus_dmamap_destroy(ring->rx_data_tag, + ring->rx_spare_map); + ring->rx_spare_map = NULL; + } + bus_dma_tag_destroy(ring->rx_data_tag); + ring->rx_data_tag = NULL; + } + + if (desc != NULL) { + bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map); + bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map); + ring->desc64 = NULL; + ring->desc32 = NULL; + ring->rx_desc_map = NULL; + } + if (ring->rx_desc_tag != NULL) { + bus_dma_tag_destroy(ring->rx_desc_tag); + ring->rx_desc_tag = NULL; + } +} + + +static void +nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) +{ + struct nfe_jpool_entry *entry; + struct nfe_rx_data *data; + void *desc; + int i, descsize; + + if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) + return; + + NFE_JLIST_LOCK(sc); + while ((entry = SLIST_FIRST(&sc->nfe_jinuse_listhead))) { + device_printf(sc->nfe_dev, + "asked to free buffer that is in use!\n"); + SLIST_REMOVE_HEAD(&sc->nfe_jinuse_listhead, jpool_entries); + SLIST_INSERT_HEAD(&sc->nfe_jfree_listhead, entry, + jpool_entries); + } + + while (!SLIST_EMPTY(&sc->nfe_jfree_listhead)) { + entry = SLIST_FIRST(&sc->nfe_jfree_listhead); + SLIST_REMOVE_HEAD(&sc->nfe_jfree_listhead, jpool_entries); + free(entry, M_DEVBUF); + } + NFE_JLIST_UNLOCK(sc); + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->jdesc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->jdesc32; + descsize = sizeof (struct nfe_desc32); + } + + for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { + data = &ring->jdata[i]; + if (data->rx_data_map != NULL) { + bus_dmamap_destroy(ring->jrx_data_tag, + data->rx_data_map); + data->rx_data_map = NULL; + } + if (data->m != NULL) { + m_freem(data->m); + data->m = NULL; + } + } + if (ring->jrx_data_tag != NULL) { + if (ring->jrx_spare_map != NULL) { + bus_dmamap_destroy(ring->jrx_data_tag, + ring->jrx_spare_map); + ring->jrx_spare_map = NULL; + } + bus_dma_tag_destroy(ring->jrx_data_tag); + ring->jrx_data_tag = NULL; + } + + if (desc != NULL) { + bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map); + bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map); + ring->jdesc64 = NULL; + ring->jdesc32 = NULL; + ring->jrx_desc_map = NULL; + } + /* Destroy jumbo buffer block. */ + if (ring->jrx_jumbo_map != NULL) + bus_dmamap_unload(ring->jrx_jumbo_tag, ring->jrx_jumbo_map); + if (ring->jrx_jumbo_map != NULL) { + bus_dmamem_free(ring->jrx_jumbo_tag, ring->jpool, + ring->jrx_jumbo_map); + ring->jpool = NULL; + ring->jrx_jumbo_map = NULL; + } + if (ring->jrx_desc_tag != NULL) { + bus_dma_tag_destroy(ring->jrx_desc_tag); + ring->jrx_desc_tag = NULL; + } +} + + +static int +nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) +{ + struct nfe_dmamap_arg ctx; + int i, error; + void *desc; + int descsize; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->desc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->desc32; + descsize = sizeof (struct nfe_desc32); + } + + ring->queued = 0; + ring->cur = ring->next = 0; + + error = bus_dma_tag_create(sc->nfe_parent_tag, + NFE_RING_ALIGN, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ + NFE_TX_RING_COUNT * descsize, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &ring->tx_desc_tag); + if (error != 0) { + device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK | + BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map); + if (error != 0) { + device_printf(sc->nfe_dev, "could not create desc DMA map\n"); + goto fail; + } + if (sc->nfe_flags & NFE_40BIT_ADDR) + ring->desc64 = desc; + else + ring->desc32 = desc; + + ctx.nfe_busaddr = 0; + error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc, + NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); + if (error != 0) { + device_printf(sc->nfe_dev, "could not load desc DMA map\n"); + goto fail; + } + ring->physaddr = ctx.nfe_busaddr; + + error = bus_dma_tag_create(sc->nfe_parent_tag, + 1, 0, + BUS_SPACE_MAXADDR, + BUS_SPACE_MAXADDR, + NULL, NULL, + NFE_TSO_MAXSIZE, + NFE_MAX_SCATTER, + NFE_TSO_MAXSGSIZE, + 0, + NULL, NULL, + &ring->tx_data_tag); + if (error != 0) { + device_printf(sc->nfe_dev, "could not create Tx DMA tag\n"); + goto fail; + } + + for (i = 0; i < NFE_TX_RING_COUNT; i++) { + error = bus_dmamap_create(ring->tx_data_tag, 0, + &ring->data[i].tx_data_map); + if (error != 0) { + device_printf(sc->nfe_dev, + "could not create Tx DMA map\n"); + goto fail; + } + } + +fail: + return (error); +} + + +static void +nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) +{ + void *desc; + size_t descsize; + + sc->nfe_force_tx = 0; + ring->queued = 0; + ring->cur = ring->next = 0; + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->desc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->desc32; + descsize = sizeof (struct nfe_desc32); + } + bzero(desc, descsize * NFE_TX_RING_COUNT); + + bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); +} + + +static void +nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) +{ + struct nfe_tx_data *data; + void *desc; + int i, descsize; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc = ring->desc64; + descsize = sizeof (struct nfe_desc64); + } else { + desc = ring->desc32; + descsize = sizeof (struct nfe_desc32); + } + + for (i = 0; i < NFE_TX_RING_COUNT; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map); + m_freem(data->m); + data->m = NULL; + } + if (data->tx_data_map != NULL) { + bus_dmamap_destroy(ring->tx_data_tag, + data->tx_data_map); + data->tx_data_map = NULL; + } + } + + if (ring->tx_data_tag != NULL) { + bus_dma_tag_destroy(ring->tx_data_tag); + ring->tx_data_tag = NULL; + } + + if (desc != NULL) { + bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map); + bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map); + ring->desc64 = NULL; + ring->desc32 = NULL; + ring->tx_desc_map = NULL; + bus_dma_tag_destroy(ring->tx_desc_tag); + ring->tx_desc_tag = NULL; + } +} + +#ifdef DEVICE_POLLING +static poll_handler_t nfe_poll; + + +static void +nfe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) +{ + struct nfe_softc *sc = ifp->if_softc; + uint32_t r; + + NFE_LOCK(sc); + + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + NFE_UNLOCK(sc); + return; + } + + if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) + nfe_jrxeof(sc, count); + else + nfe_rxeof(sc, count); + nfe_txeof(sc); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + taskqueue_enqueue_fast(taskqueue_fast, &sc->nfe_tx_task); + + if (cmd == POLL_AND_CHECK_STATUS) { + if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { + NFE_UNLOCK(sc); + return; + } + NFE_WRITE(sc, sc->nfe_irq_status, r); + + if (r & NFE_IRQ_LINK) { + NFE_READ(sc, NFE_PHY_STATUS); + NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); + DPRINTF(sc, "link state changed\n"); + } + } + NFE_UNLOCK(sc); +} +#endif /* DEVICE_POLLING */ + +static void +nfe_set_intr(struct nfe_softc *sc) +{ + + if (sc->nfe_msi != 0) + NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); +} + + +/* In MSIX, a write to mask reegisters behaves as XOR. */ +static __inline void +nfe_enable_intr(struct nfe_softc *sc) +{ + + if (sc->nfe_msix != 0) { + /* XXX Should have a better way to enable interrupts! */ + if (NFE_READ(sc, sc->nfe_irq_mask) == 0) + NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); + } else + NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); +} + + +static __inline void +nfe_disable_intr(struct nfe_softc *sc) +{ + + if (sc->nfe_msix != 0) { + /* XXX Should have a better way to disable interrupts! */ + if (NFE_READ(sc, sc->nfe_irq_mask) != 0) + NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); + } else + NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); +} + + +static int +nfe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct nfe_softc *sc; + struct ifreq *ifr; + struct mii_data *mii; + int error, init, mask; + + sc = ifp->if_softc; + ifr = (struct ifreq *) data; + error = 0; + init = 0; + switch (cmd) { + case SIOCSIFMTU: + if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU) + error = EINVAL; + else if (ifp->if_mtu != ifr->ifr_mtu) { + if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) || + (sc->nfe_jumbo_disable != 0)) && + ifr->ifr_mtu > ETHERMTU) + error = EINVAL; + else { + NFE_LOCK(sc); + ifp->if_mtu = ifr->ifr_mtu; + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) + nfe_init_locked(sc); + NFE_UNLOCK(sc); + } + } + break; + case SIOCSIFFLAGS: + NFE_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + /* + * If only the PROMISC or ALLMULTI flag changes, then + * don't do a full re-init of the chip, just update + * the Rx filter. + */ + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && + ((ifp->if_flags ^ sc->nfe_if_flags) & + (IFF_ALLMULTI | IFF_PROMISC)) != 0) + nfe_setmulti(sc); + else + nfe_init_locked(sc); + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + nfe_stop(ifp); + } + sc->nfe_if_flags = ifp->if_flags; + NFE_UNLOCK(sc); + error = 0; + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + NFE_LOCK(sc); + nfe_setmulti(sc); + NFE_UNLOCK(sc); + error = 0; + } + break; + case SIOCSIFMEDIA: + case SIOCGIFMEDIA: + mii = device_get_softc(sc->nfe_miibus); + error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); + break; + case SIOCSIFCAP: + mask = ifr->ifr_reqcap ^ ifp->if_capenable; +#ifdef DEVICE_POLLING + if ((mask & IFCAP_POLLING) != 0) { + if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { + error = ether_poll_register(nfe_poll, ifp); + if (error) + break; + NFE_LOCK(sc); + nfe_disable_intr(sc); + ifp->if_capenable |= IFCAP_POLLING; + NFE_UNLOCK(sc); + } else { + error = ether_poll_deregister(ifp); + /* Enable interrupt even in error case */ + NFE_LOCK(sc); + nfe_enable_intr(sc); + ifp->if_capenable &= ~IFCAP_POLLING; + NFE_UNLOCK(sc); + } + } +#endif /* DEVICE_POLLING */ + if ((sc->nfe_flags & NFE_HW_CSUM) != 0 && + (mask & IFCAP_HWCSUM) != 0) { + ifp->if_capenable ^= IFCAP_HWCSUM; + if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && + (IFCAP_TXCSUM & ifp->if_capabilities) != 0) + ifp->if_hwassist |= NFE_CSUM_FEATURES; + else + ifp->if_hwassist &= ~NFE_CSUM_FEATURES; + init++; + } + if ((sc->nfe_flags & NFE_HW_VLAN) != 0 && + (mask & IFCAP_VLAN_HWTAGGING) != 0) { + ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; + init++; + } + /* + * XXX + * It seems that VLAN stripping requires Rx checksum offload. + * Unfortunately FreeBSD has no way to disable only Rx side + * VLAN stripping. So when we know Rx checksum offload is + * disabled turn entire hardware VLAN assist off. + */ + if ((sc->nfe_flags & (NFE_HW_CSUM | NFE_HW_VLAN)) == + (NFE_HW_CSUM | NFE_HW_VLAN)) { + if ((ifp->if_capenable & IFCAP_RXCSUM) == 0) + ifp->if_capenable &= ~IFCAP_VLAN_HWTAGGING; + } + + if ((sc->nfe_flags & NFE_HW_CSUM) != 0 && + (mask & IFCAP_TSO4) != 0) { + ifp->if_capenable ^= IFCAP_TSO4; + if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && + (IFCAP_TSO4 & ifp->if_capabilities) != 0) + ifp->if_hwassist |= CSUM_TSO; + else + ifp->if_hwassist &= ~CSUM_TSO; + } + + if (init > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + nfe_init(sc); + } + if ((sc->nfe_flags & NFE_HW_VLAN) != 0) + VLAN_CAPABILITIES(ifp); + break; + default: + error = ether_ioctl(ifp, cmd, data); + break; + } + + return (error); +} + + +static int +nfe_intr(void *arg) +{ + struct nfe_softc *sc; + uint32_t status; + + sc = (struct nfe_softc *)arg; + + status = NFE_READ(sc, sc->nfe_irq_status); + if (status == 0 || status == 0xffffffff) + return (FILTER_STRAY); + nfe_disable_intr(sc); + taskqueue_enqueue_fast(taskqueue_fast, &sc->nfe_int_task); + + return (FILTER_HANDLED); +} + + +static void +nfe_int_task(void *arg, int pending) +{ + struct nfe_softc *sc = arg; + struct ifnet *ifp = sc->nfe_ifp; + uint32_t r; + int domore; + + NFE_LOCK(sc); + + if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { + nfe_enable_intr(sc); + NFE_UNLOCK(sc); + return; /* not for us */ + } + NFE_WRITE(sc, sc->nfe_irq_status, r); + + DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r); + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) { + NFE_UNLOCK(sc); + return; + } +#endif + + if (r & NFE_IRQ_LINK) { + NFE_READ(sc, NFE_PHY_STATUS); + NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); + DPRINTF(sc, "link state changed\n"); + } + + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + NFE_UNLOCK(sc); + nfe_enable_intr(sc); + return; + } + + domore = 0; + /* check Rx ring */ + if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) + domore = nfe_jrxeof(sc, sc->nfe_process_limit); + else + domore = nfe_rxeof(sc, sc->nfe_process_limit); + /* check Tx ring */ + nfe_txeof(sc); + + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + taskqueue_enqueue_fast(taskqueue_fast, &sc->nfe_tx_task); + + NFE_UNLOCK(sc); + + if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) { + taskqueue_enqueue_fast(taskqueue_fast, &sc->nfe_int_task); + return; + } + + /* Reenable interrupts. */ + nfe_enable_intr(sc); +} + + +static __inline void +nfe_discard_rxbuf(struct nfe_softc *sc, int idx) +{ + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + struct nfe_rx_data *data; + struct mbuf *m; + + data = &sc->rxq.data[idx]; + m = data->m; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->rxq.desc64[idx]; + /* VLAN packet may have overwritten it. */ + desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); + desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); + desc64->length = htole16(m->m_len); + desc64->flags = htole16(NFE_RX_READY); + } else { + desc32 = &sc->rxq.desc32[idx]; + desc32->length = htole16(m->m_len); + desc32->flags = htole16(NFE_RX_READY); + } +} + + +static __inline void +nfe_discard_jrxbuf(struct nfe_softc *sc, int idx) +{ + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + struct nfe_rx_data *data; + struct mbuf *m; + + data = &sc->jrxq.jdata[idx]; + m = data->m; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->jrxq.jdesc64[idx]; + /* VLAN packet may have overwritten it. */ + desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); + desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); + desc64->length = htole16(m->m_len); + desc64->flags = htole16(NFE_RX_READY); + } else { + desc32 = &sc->jrxq.jdesc32[idx]; + desc32->length = htole16(m->m_len); + desc32->flags = htole16(NFE_RX_READY); + } +} + + +static int +nfe_newbuf(struct nfe_softc *sc, int idx) +{ + struct nfe_rx_data *data; + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + struct mbuf *m; + bus_dma_segment_t segs[1]; + bus_dmamap_t map; + int nsegs; + + m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (m == NULL) + return (ENOBUFS); + + m->m_len = m->m_pkthdr.len = MCLBYTES; + m_adj(m, ETHER_ALIGN); + + if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map, + m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { + m_freem(m); + return (ENOBUFS); + } + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); + + data = &sc->rxq.data[idx]; + if (data->m != NULL) { + bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map); + } + map = data->rx_data_map; + data->rx_data_map = sc->rxq.rx_spare_map; + sc->rxq.rx_spare_map = map; + bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, + BUS_DMASYNC_PREREAD); + data->paddr = segs[0].ds_addr; + data->m = m; + /* update mapping address in h/w descriptor */ + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->rxq.desc64[idx]; + desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); + desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); + desc64->length = htole16(segs[0].ds_len); + desc64->flags = htole16(NFE_RX_READY); + } else { + desc32 = &sc->rxq.desc32[idx]; + desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); + desc32->length = htole16(segs[0].ds_len); + desc32->flags = htole16(NFE_RX_READY); + } + + return (0); +} + + +static int +nfe_jnewbuf(struct nfe_softc *sc, int idx) +{ + struct nfe_rx_data *data; + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + struct mbuf *m; + bus_dma_segment_t segs[1]; + bus_dmamap_t map; + int nsegs; + void *buf; + + MGETHDR(m, M_DONTWAIT, MT_DATA); + if (m == NULL) + return (ENOBUFS); + buf = nfe_jalloc(sc); + if (buf == NULL) { + m_freem(m); + return (ENOBUFS); + } + /* Attach the buffer to the mbuf. */ + MEXTADD(m, buf, NFE_JLEN, nfe_jfree, (struct nfe_softc *)sc, 0, + EXT_NET_DRV); + if ((m->m_flags & M_EXT) == 0) { + m_freem(m); + return (ENOBUFS); + } + m->m_pkthdr.len = m->m_len = NFE_JLEN; + m_adj(m, ETHER_ALIGN); + + if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag, + sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { + m_freem(m); + return (ENOBUFS); + } + KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); + + data = &sc->jrxq.jdata[idx]; + if (data->m != NULL) { + bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map); + } + map = data->rx_data_map; + data->rx_data_map = sc->jrxq.jrx_spare_map; + sc->jrxq.jrx_spare_map = map; + bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, + BUS_DMASYNC_PREREAD); + data->paddr = segs[0].ds_addr; + data->m = m; + /* update mapping address in h/w descriptor */ + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->jrxq.jdesc64[idx]; + desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); + desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); + desc64->length = htole16(segs[0].ds_len); + desc64->flags = htole16(NFE_RX_READY); + } else { + desc32 = &sc->jrxq.jdesc32[idx]; + desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); + desc32->length = htole16(segs[0].ds_len); + desc32->flags = htole16(NFE_RX_READY); + } + + return (0); +} + + +static int +nfe_rxeof(struct nfe_softc *sc, int count) +{ + struct ifnet *ifp = sc->nfe_ifp; + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + struct nfe_rx_data *data; + struct mbuf *m; + uint16_t flags; + int len, prog; + uint32_t vtag = 0; + + NFE_LOCK_ASSERT(sc); + + bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, + BUS_DMASYNC_POSTREAD); + + for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) { + if (count <= 0) + break; + count--; + + data = &sc->rxq.data[sc->rxq.cur]; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->rxq.desc64[sc->rxq.cur]; + vtag = le32toh(desc64->physaddr[1]); + flags = le16toh(desc64->flags); + len = le16toh(desc64->length) & NFE_RX_LEN_MASK; + } else { + desc32 = &sc->rxq.desc32[sc->rxq.cur]; + flags = le16toh(desc32->flags); + len = le16toh(desc32->length) & NFE_RX_LEN_MASK; + } + + if (flags & NFE_RX_READY) + break; + prog++; + if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { + if (!(flags & NFE_RX_VALID_V1)) { + ifp->if_ierrors++; + nfe_discard_rxbuf(sc, sc->rxq.cur); + continue; + } + if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { + flags &= ~NFE_RX_ERROR; + len--; /* fix buffer length */ + } + } else { + if (!(flags & NFE_RX_VALID_V2)) { + ifp->if_ierrors++; + nfe_discard_rxbuf(sc, sc->rxq.cur); + continue; + } + + if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { + flags &= ~NFE_RX_ERROR; + len--; /* fix buffer length */ + } + } + + if (flags & NFE_RX_ERROR) { + ifp->if_ierrors++; + nfe_discard_rxbuf(sc, sc->rxq.cur); + continue; + } + + m = data->m; + if (nfe_newbuf(sc, sc->rxq.cur) != 0) { + ifp->if_iqdrops++; + nfe_discard_rxbuf(sc, sc->rxq.cur); + continue; + } + + if ((vtag & NFE_RX_VTAG) != 0 && + (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { + m->m_pkthdr.ether_vtag = vtag & 0xffff; + m->m_flags |= M_VLANTAG; + } + + m->m_pkthdr.len = m->m_len = len; + m->m_pkthdr.rcvif = ifp; + + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { + if ((flags & NFE_RX_IP_CSUMOK) != 0) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + if ((flags & NFE_RX_TCP_CSUMOK) != 0 || + (flags & NFE_RX_UDP_CSUMOK) != 0) { + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID | CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + } + + ifp->if_ipackets++; + + NFE_UNLOCK(sc); + (*ifp->if_input)(ifp, m); + NFE_LOCK(sc); + } + + if (prog > 0) + bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (count > 0 ? 0 : EAGAIN); +} + + +static int +nfe_jrxeof(struct nfe_softc *sc, int count) +{ + struct ifnet *ifp = sc->nfe_ifp; + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + struct nfe_rx_data *data; + struct mbuf *m; + uint16_t flags; + int len, prog; + uint32_t vtag = 0; + + NFE_LOCK_ASSERT(sc); + + bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, + BUS_DMASYNC_POSTREAD); + + for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT), + vtag = 0) { + if (count <= 0) + break; + count--; + + data = &sc->jrxq.jdata[sc->jrxq.jcur]; + + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur]; + vtag = le32toh(desc64->physaddr[1]); + flags = le16toh(desc64->flags); + len = le16toh(desc64->length) & NFE_RX_LEN_MASK; + } else { + desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur]; + flags = le16toh(desc32->flags); + len = le16toh(desc32->length) & NFE_RX_LEN_MASK; + } + + if (flags & NFE_RX_READY) + break; + prog++; + if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { + if (!(flags & NFE_RX_VALID_V1)) { + ifp->if_ierrors++; + nfe_discard_jrxbuf(sc, sc->jrxq.jcur); + continue; + } + if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { + flags &= ~NFE_RX_ERROR; + len--; /* fix buffer length */ + } + } else { + if (!(flags & NFE_RX_VALID_V2)) { + ifp->if_ierrors++; + nfe_discard_jrxbuf(sc, sc->jrxq.jcur); + continue; + } + + if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { + flags &= ~NFE_RX_ERROR; + len--; /* fix buffer length */ + } + } + + if (flags & NFE_RX_ERROR) { + ifp->if_ierrors++; + nfe_discard_jrxbuf(sc, sc->jrxq.jcur); + continue; + } + + m = data->m; + if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) { + ifp->if_iqdrops++; + nfe_discard_jrxbuf(sc, sc->jrxq.jcur); + continue; + } + + if ((vtag & NFE_RX_VTAG) != 0 && + (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { + m->m_pkthdr.ether_vtag = vtag & 0xffff; + m->m_flags |= M_VLANTAG; + } + + m->m_pkthdr.len = m->m_len = len; + m->m_pkthdr.rcvif = ifp; + + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { + if ((flags & NFE_RX_IP_CSUMOK) != 0) { + m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; + m->m_pkthdr.csum_flags |= CSUM_IP_VALID; + if ((flags & NFE_RX_TCP_CSUMOK) != 0 || + (flags & NFE_RX_UDP_CSUMOK) != 0) { + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID | CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + } + + ifp->if_ipackets++; + + NFE_UNLOCK(sc); + (*ifp->if_input)(ifp, m); + NFE_LOCK(sc); + } + + if (prog > 0) + bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + return (count > 0 ? 0 : EAGAIN); +} + + +static void +nfe_txeof(struct nfe_softc *sc) +{ + struct ifnet *ifp = sc->nfe_ifp; + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + struct nfe_tx_data *data = NULL; + uint16_t flags; + int cons, prog; + + NFE_LOCK_ASSERT(sc); + + bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, + BUS_DMASYNC_POSTREAD); + + prog = 0; + for (cons = sc->txq.next; cons != sc->txq.cur; + NFE_INC(cons, NFE_TX_RING_COUNT)) { + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->txq.desc64[cons]; + flags = le16toh(desc64->flags); + } else { + desc32 = &sc->txq.desc32[cons]; + flags = le16toh(desc32->flags); + } + + if (flags & NFE_TX_VALID) + break; + + prog++; + sc->txq.queued--; + data = &sc->txq.data[cons]; + + if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { + if ((flags & NFE_TX_LASTFRAG_V1) == 0) + continue; + if ((flags & NFE_TX_ERROR_V1) != 0) { + device_printf(sc->nfe_dev, + "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR); + + ifp->if_oerrors++; + } else + ifp->if_opackets++; + } else { + if ((flags & NFE_TX_LASTFRAG_V2) == 0) + continue; + if ((flags & NFE_TX_ERROR_V2) != 0) { + device_printf(sc->nfe_dev, + "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR); + ifp->if_oerrors++; + } else + ifp->if_opackets++; + } + + /* last fragment of the mbuf chain transmitted */ + KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__)); + bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map); + m_freem(data->m); + data->m = NULL; + } + + if (prog > 0) { + sc->nfe_force_tx = 0; + sc->txq.next = cons; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + if (sc->txq.queued == 0) + sc->nfe_watchdog_timer = 0; + } +} + +/* + * It's copy of ath_defrag(ath(4)). + * + * Defragment an mbuf chain, returning at most maxfrags separate + * mbufs+clusters. If this is not possible NULL is returned and + * the original mbuf chain is left in it's present (potentially + * modified) state. We use two techniques: collapsing consecutive + * mbufs and replacing consecutive mbufs by a cluster. + */ +static struct mbuf * +nfe_defrag(struct mbuf *m0, int how, int maxfrags) +{ + struct mbuf *m, *n, *n2, **prev; + u_int curfrags; + + /* + * Calculate the current number of frags. + */ + curfrags = 0; + for (m = m0; m != NULL; m = m->m_next) + curfrags++; + /* + * First, try to collapse mbufs. Note that we always collapse + * towards the front so we don't need to deal with moving the + * pkthdr. This may be suboptimal if the first mbuf has much + * less data than the following. + */ + m = m0; +again: + for (;;) { + n = m->m_next; + if (n == NULL) + break; + if ((m->m_flags & M_RDONLY) == 0 && + n->m_len < M_TRAILINGSPACE(m)) { + bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, + n->m_len); + m->m_len += n->m_len; + m->m_next = n->m_next; + m_free(n); + if (--curfrags <= maxfrags) + return (m0); + } else + m = n; + } + KASSERT(maxfrags > 1, + ("maxfrags %u, but normal collapse failed", maxfrags)); + /* + * Collapse consecutive mbufs to a cluster. + */ + prev = &m0->m_next; /* NB: not the first mbuf */ + while ((n = *prev) != NULL) { + if ((n2 = n->m_next) != NULL && + n->m_len + n2->m_len < MCLBYTES) { + m = m_getcl(how, MT_DATA, 0); + if (m == NULL) + goto bad; + bcopy(mtod(n, void *), mtod(m, void *), n->m_len); + bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, + n2->m_len); + m->m_len = n->m_len + n2->m_len; + m->m_next = n2->m_next; + *prev = m; + m_free(n); + m_free(n2); + if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ + return m0; + /* + * Still not there, try the normal collapse + * again before we allocate another cluster. + */ + goto again; + } + prev = &n->m_next; + } + /* + * No place where we can collapse to a cluster; punt. + * This can occur if, for example, you request 2 frags + * but the packet requires that both be clusters (we + * never reallocate the first mbuf to avoid moving the + * packet header). + */ +bad: + return (NULL); +} + + +static int +nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) +{ + struct nfe_desc32 *desc32 = NULL; + struct nfe_desc64 *desc64 = NULL; + bus_dmamap_t map; + bus_dma_segment_t segs[NFE_MAX_SCATTER]; + int error, i, nsegs, prod, si; + uint32_t tso_segsz; + uint16_t cflags, flags; + struct mbuf *m; + + prod = si = sc->txq.cur; + map = sc->txq.data[prod].tx_data_map; + + error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, + &nsegs, BUS_DMA_NOWAIT); + if (error == EFBIG) { + m = nfe_defrag(*m_head, M_DONTWAIT, NFE_MAX_SCATTER); + if (m == NULL) { + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + *m_head = m; + error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, + *m_head, segs, &nsegs, BUS_DMA_NOWAIT); + if (error != 0) { + m_freem(*m_head); + *m_head = NULL; + return (ENOBUFS); + } + } else if (error != 0) + return (error); + if (nsegs == 0) { + m_freem(*m_head); + *m_head = NULL; + return (EIO); + } + + if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) { + bus_dmamap_unload(sc->txq.tx_data_tag, map); + return (ENOBUFS); + } + + m = *m_head; + cflags = flags = 0; + tso_segsz = 0; + if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) { + if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) + cflags |= NFE_TX_IP_CSUM; + if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) + cflags |= NFE_TX_TCP_UDP_CSUM; + if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) + cflags |= NFE_TX_TCP_UDP_CSUM; + } + if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { + tso_segsz = (uint32_t)m->m_pkthdr.tso_segsz << + NFE_TX_TSO_SHIFT; + cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); + cflags |= NFE_TX_TSO; + } + + for (i = 0; i < nsegs; i++) { + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64 = &sc->txq.desc64[prod]; + desc64->physaddr[0] = + htole32(NFE_ADDR_HI(segs[i].ds_addr)); + desc64->physaddr[1] = + htole32(NFE_ADDR_LO(segs[i].ds_addr)); + desc64->vtag = 0; + desc64->length = htole16(segs[i].ds_len - 1); + desc64->flags = htole16(flags); + } else { + desc32 = &sc->txq.desc32[prod]; + desc32->physaddr = + htole32(NFE_ADDR_LO(segs[i].ds_addr)); + desc32->length = htole16(segs[i].ds_len - 1); + desc32->flags = htole16(flags); + } + + /* + * Setting of the valid bit in the first descriptor is + * deferred until the whole chain is fully setup. + */ + flags |= NFE_TX_VALID; + + sc->txq.queued++; + NFE_INC(prod, NFE_TX_RING_COUNT); + } + + /* + * the whole mbuf chain has been DMA mapped, fix last/first descriptor. + * csum flags, vtag and TSO belong to the first fragment only. + */ + if (sc->nfe_flags & NFE_40BIT_ADDR) { + desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); + desc64 = &sc->txq.desc64[si]; + if ((m->m_flags & M_VLANTAG) != 0) + desc64->vtag = htole32(NFE_TX_VTAG | + m->m_pkthdr.ether_vtag); + if (tso_segsz != 0) { + /* + * XXX + * The following indicates the descriptor element + * is a 32bit quantity. + */ + desc64->length |= htole16((uint16_t)tso_segsz); + desc64->flags |= htole16(tso_segsz >> 16); + } + /* + * finally, set the valid/checksum/TSO bit in the first + * descriptor. + */ + desc64->flags |= htole16(NFE_TX_VALID | cflags); + } else { + if (sc->nfe_flags & NFE_JUMBO_SUP) + desc32->flags |= htole16(NFE_TX_LASTFRAG_V2); + else + desc32->flags |= htole16(NFE_TX_LASTFRAG_V1); + desc32 = &sc->txq.desc32[si]; + if (tso_segsz != 0) { + /* + * XXX + * The following indicates the descriptor element + * is a 32bit quantity. + */ + desc32->length |= htole16((uint16_t)tso_segsz); + desc32->flags |= htole16(tso_segsz >> 16); + } + /* + * finally, set the valid/checksum/TSO bit in the first + * descriptor. + */ + desc32->flags |= htole16(NFE_TX_VALID | cflags); + } + + sc->txq.cur = prod; + prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT; + sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map; + sc->txq.data[prod].tx_data_map = map; + sc->txq.data[prod].m = m; + + bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE); + + return (0); +} + + +static void +nfe_setmulti(struct nfe_softc *sc) +{ + struct ifnet *ifp = sc->nfe_ifp; + struct ifmultiaddr *ifma; + int i; + uint32_t filter; + uint8_t addr[ETHER_ADDR_LEN], mask[ETHER_ADDR_LEN]; + uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = { + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }; + + NFE_LOCK_ASSERT(sc); + + if ((ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { + bzero(addr, ETHER_ADDR_LEN); + bzero(mask, ETHER_ADDR_LEN); + goto done; + } + + bcopy(etherbroadcastaddr, addr, ETHER_ADDR_LEN); + bcopy(etherbroadcastaddr, mask, ETHER_ADDR_LEN); + + IF_ADDR_LOCK(ifp); + TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { + u_char *addrp; + + if (ifma->ifma_addr->sa_family != AF_LINK) + continue; + + addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); + for (i = 0; i < ETHER_ADDR_LEN; i++) { + u_int8_t mcaddr = addrp[i]; + addr[i] &= mcaddr; + mask[i] &= ~mcaddr; + } + } + IF_ADDR_UNLOCK(ifp); + + for (i = 0; i < ETHER_ADDR_LEN; i++) { + mask[i] |= addr[i]; + } + +done: + addr[0] |= 0x01; /* make sure multicast bit is set */ + + NFE_WRITE(sc, NFE_MULTIADDR_HI, + addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); + NFE_WRITE(sc, NFE_MULTIADDR_LO, + addr[5] << 8 | addr[4]); + NFE_WRITE(sc, NFE_MULTIMASK_HI, + mask[3] << 24 | mask[2] << 16 | mask[1] << 8 | mask[0]); + NFE_WRITE(sc, NFE_MULTIMASK_LO, + mask[5] << 8 | mask[4]); + + filter = NFE_READ(sc, NFE_RXFILTER); + filter &= NFE_PFF_RX_PAUSE; + filter |= NFE_RXFILTER_MAGIC; + filter |= (ifp->if_flags & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M; + NFE_WRITE(sc, NFE_RXFILTER, filter); +} + + +static void +nfe_tx_task(void *arg, int pending) +{ + struct ifnet *ifp; + + ifp = (struct ifnet *)arg; + nfe_start(ifp); +} + + +static void +nfe_start(struct ifnet *ifp) +{ + struct nfe_softc *sc = ifp->if_softc; + struct mbuf *m0; + int enq; + + NFE_LOCK(sc); + + if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != + IFF_DRV_RUNNING || sc->nfe_link == 0) { + NFE_UNLOCK(sc); + return; + } + + for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); + if (m0 == NULL) + break; + + if (nfe_encap(sc, &m0) != 0) { + if (m0 == NULL) + break; + IFQ_DRV_PREPEND(&ifp->if_snd, m0); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + enq++; + ETHER_BPF_MTAP(ifp, m0); + } + + if (enq > 0) { + bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* kick Tx */ + NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); + + /* + * Set a timeout in case the chip goes out to lunch. + */ + sc->nfe_watchdog_timer = 5; + } + + NFE_UNLOCK(sc); +} + + +static void +nfe_watchdog(struct ifnet *ifp) +{ + struct nfe_softc *sc = ifp->if_softc; + + if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer) + return; + + /* Check if we've lost Tx completion interrupt. */ + nfe_txeof(sc); + if (sc->txq.queued == 0) { + if_printf(ifp, "watchdog timeout (missed Tx interrupts) " + "-- recovering\n"); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) + taskqueue_enqueue_fast(taskqueue_fast, + &sc->nfe_tx_task); + return; + } + /* Check if we've lost start Tx command. */ + sc->nfe_force_tx++; + if (sc->nfe_force_tx <= 3) { + /* + * If this is the case for watchdog timeout, the following + * code should go to nfe_txeof(). + */ + NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); + return; + } + sc->nfe_force_tx = 0; + + if_printf(ifp, "watchdog timeout\n"); + + ifp->if_drv_flags &= ~IFF_DRV_RUNNING; + ifp->if_oerrors++; + nfe_init_locked(sc); +} + + +static void +nfe_init(void *xsc) +{ + struct nfe_softc *sc = xsc; + + NFE_LOCK(sc); + nfe_init_locked(sc); + NFE_UNLOCK(sc); +} + + +static void +nfe_init_locked(void *xsc) +{ + struct nfe_softc *sc = xsc; + struct ifnet *ifp = sc->nfe_ifp; + struct mii_data *mii; + uint32_t val; + int error; + + NFE_LOCK_ASSERT(sc); + + mii = device_get_softc(sc->nfe_miibus); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + return; + + nfe_stop(ifp); + + sc->nfe_framesize = ifp->if_mtu + NFE_RX_HEADERS; + + nfe_init_tx_ring(sc, &sc->txq); + if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN)) + error = nfe_init_jrx_ring(sc, &sc->jrxq); + else + error = nfe_init_rx_ring(sc, &sc->rxq); + if (error != 0) { + device_printf(sc->nfe_dev, + "initialization failed: no memory for rx buffers\n"); + nfe_stop(ifp); + return; + } + + val = 0; + if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0) + val |= NFE_MAC_ADDR_INORDER; + NFE_WRITE(sc, NFE_TX_UNK, val); + NFE_WRITE(sc, NFE_STATUS, 0); + + if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) + NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE); + + sc->rxtxctl = NFE_RXTX_BIT2; + if (sc->nfe_flags & NFE_40BIT_ADDR) + sc->rxtxctl |= NFE_RXTX_V3MAGIC; + else if (sc->nfe_flags & NFE_JUMBO_SUP) + sc->rxtxctl |= NFE_RXTX_V2MAGIC; + + if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) + sc->rxtxctl |= NFE_RXTX_RXCSUM; + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) + sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; + + NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); + DELAY(10); + NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); + + if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) + NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); + else + NFE_WRITE(sc, NFE_VTAG_CTL, 0); + + NFE_WRITE(sc, NFE_SETUP_R6, 0); + + /* set MAC address */ + nfe_set_macaddr(sc, IF_LLADDR(ifp)); + + /* tell MAC where rings are in memory */ + if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) { + NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, + NFE_ADDR_HI(sc->jrxq.jphysaddr)); + NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, + NFE_ADDR_LO(sc->jrxq.jphysaddr)); + } else { + NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, + NFE_ADDR_HI(sc->rxq.physaddr)); + NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, + NFE_ADDR_LO(sc->rxq.physaddr)); + } + NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr)); + NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr)); + + NFE_WRITE(sc, NFE_RING_SIZE, + (NFE_RX_RING_COUNT - 1) << 16 | + (NFE_TX_RING_COUNT - 1)); + + NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize); + + /* force MAC to wakeup */ + val = NFE_READ(sc, NFE_PWR_STATE); + if ((val & NFE_PWR_WAKEUP) == 0) + NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP); + DELAY(10); + val = NFE_READ(sc, NFE_PWR_STATE); + NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID); + +#if 1 + /* configure interrupts coalescing/mitigation */ + NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); +#else + /* no interrupt mitigation: one interrupt per packet */ + NFE_WRITE(sc, NFE_IMTIMER, 970); +#endif + + NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100); + NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); + NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); + + /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ + NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); + + NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); + NFE_WRITE(sc, NFE_WOL_CTL, NFE_WOL_MAGIC); + + sc->rxtxctl &= ~NFE_RXTX_BIT2; + NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); + DELAY(10); + NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); + + /* set Rx filter */ + nfe_setmulti(sc); + + /* enable Rx */ + NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); + + /* enable Tx */ + NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); + + NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); + +#ifdef DEVICE_POLLING + if (ifp->if_capenable & IFCAP_POLLING) + nfe_disable_intr(sc); + else +#endif + nfe_set_intr(sc); + nfe_enable_intr(sc); /* enable interrupts */ + + ifp->if_drv_flags |= IFF_DRV_RUNNING; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + sc->nfe_link = 0; + mii_mediachg(mii); + + callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); +} + + +static void +nfe_stop(struct ifnet *ifp) +{ + struct nfe_softc *sc = ifp->if_softc; + struct nfe_rx_ring *rx_ring; + struct nfe_jrx_ring *jrx_ring; + struct nfe_tx_ring *tx_ring; + struct nfe_rx_data *rdata; + struct nfe_tx_data *tdata; + int i; + + NFE_LOCK_ASSERT(sc); + + sc->nfe_watchdog_timer = 0; + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + + callout_stop(&sc->nfe_stat_ch); + + /* abort Tx */ + NFE_WRITE(sc, NFE_TX_CTL, 0); + + /* disable Rx */ + NFE_WRITE(sc, NFE_RX_CTL, 0); + + /* disable interrupts */ + nfe_disable_intr(sc); + + sc->nfe_link = 0; + + /* free Rx and Tx mbufs still in the queues. */ + rx_ring = &sc->rxq; + for (i = 0; i < NFE_RX_RING_COUNT; i++) { + rdata = &rx_ring->data[i]; + if (rdata->m != NULL) { + bus_dmamap_sync(rx_ring->rx_data_tag, + rdata->rx_data_map, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(rx_ring->rx_data_tag, + rdata->rx_data_map); + m_freem(rdata->m); + rdata->m = NULL; + } + } + + if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) { + jrx_ring = &sc->jrxq; + for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { + rdata = &jrx_ring->jdata[i]; + if (rdata->m != NULL) { + bus_dmamap_sync(jrx_ring->jrx_data_tag, + rdata->rx_data_map, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(jrx_ring->jrx_data_tag, + rdata->rx_data_map); + m_freem(rdata->m); + rdata->m = NULL; + } + } + } + + tx_ring = &sc->txq; + for (i = 0; i < NFE_RX_RING_COUNT; i++) { + tdata = &tx_ring->data[i]; + if (tdata->m != NULL) { + bus_dmamap_sync(tx_ring->tx_data_tag, + tdata->tx_data_map, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(tx_ring->tx_data_tag, + tdata->tx_data_map); + m_freem(tdata->m); + tdata->m = NULL; + } + } +} + + +static int +nfe_ifmedia_upd(struct ifnet *ifp) +{ + struct nfe_softc *sc = ifp->if_softc; + struct mii_data *mii; + + NFE_LOCK(sc); + mii = device_get_softc(sc->nfe_miibus); + mii_mediachg(mii); + NFE_UNLOCK(sc); + + return (0); +} + + +static void +nfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) +{ + struct nfe_softc *sc; + struct mii_data *mii; + + sc = ifp->if_softc; + + NFE_LOCK(sc); + mii = device_get_softc(sc->nfe_miibus); + mii_pollstat(mii); + NFE_UNLOCK(sc); + + ifmr->ifm_active = mii->mii_media_active; + ifmr->ifm_status = mii->mii_media_status; +} + + +void +nfe_tick(void *xsc) +{ + struct nfe_softc *sc; + struct mii_data *mii; + struct ifnet *ifp; + + sc = (struct nfe_softc *)xsc; + + NFE_LOCK_ASSERT(sc); + + ifp = sc->nfe_ifp; + + mii = device_get_softc(sc->nfe_miibus); + mii_tick(mii); + nfe_watchdog(ifp); + callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); +} + + +static void +nfe_shutdown(device_t dev) +{ + struct nfe_softc *sc; + struct ifnet *ifp; + + sc = device_get_softc(dev); + + NFE_LOCK(sc); + ifp = sc->nfe_ifp; + nfe_stop(ifp); + /* nfe_reset(sc); */ + NFE_UNLOCK(sc); +} + + +static void +nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) +{ + uint32_t val; + + if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { + val = NFE_READ(sc, NFE_MACADDR_LO); + addr[0] = (val >> 8) & 0xff; + addr[1] = (val & 0xff); + + val = NFE_READ(sc, NFE_MACADDR_HI); + addr[2] = (val >> 24) & 0xff; + addr[3] = (val >> 16) & 0xff; + addr[4] = (val >> 8) & 0xff; + addr[5] = (val & 0xff); + } else { + val = NFE_READ(sc, NFE_MACADDR_LO); + addr[5] = (val >> 8) & 0xff; + addr[4] = (val & 0xff); + + val = NFE_READ(sc, NFE_MACADDR_HI); + addr[3] = (val >> 24) & 0xff; + addr[2] = (val >> 16) & 0xff; + addr[1] = (val >> 8) & 0xff; + addr[0] = (val & 0xff); + } +} + + +static void +nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr) +{ + + NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]); + NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 | + addr[1] << 8 | addr[0]); +} + + +/* + * Map a single buffer address. + */ + +static void +nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + struct nfe_dmamap_arg *ctx; + + if (error != 0) + return; + + KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); + + ctx = (struct nfe_dmamap_arg *)arg; + ctx->nfe_busaddr = segs[0].ds_addr; +} + + +static int +sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) +{ + int error, value; + + if (!arg1) + return (EINVAL); + value = *(int *)arg1; + error = sysctl_handle_int(oidp, &value, 0, req); + if (error || !req->newptr) + return (error); + if (value < low || value > high) + return (EINVAL); + *(int *)arg1 = value; + + return (0); +} + + +static int +sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS) +{ + + return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN, + NFE_PROC_MAX)); +} diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h new file mode 100644 index 0000000000..27756e309c --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfereg.h @@ -0,0 +1,322 @@ +/* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */ + +/*- + * Copyright (c) 2005 Jonathan Gray + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD: src/sys/dev/nfe/if_nfereg.h,v 1.10 2007/06/12 10:51:47 yongari Exp $ + */ + +#define NFE_RX_RING_COUNT 256 +#define NFE_JUMBO_RX_RING_COUNT NFE_RX_RING_COUNT +#define NFE_TX_RING_COUNT 256 + +#define NFE_PROC_DEFAULT ((NFE_RX_RING_COUNT * 3) / 4) +#define NFE_PROC_MIN 50 +#define NFE_PROC_MAX (NFE_RX_RING_COUNT - 1) + +#define NFE_INC(x, y) (x) = ((x) + 1) % y + +/* RX/TX MAC addr + type + VLAN + align + slack */ +#define NFE_RX_HEADERS 64 + +/* Maximum MTU size. */ +#define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */ +#define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */ + +#define NFE_JUMBO_FRAMELEN NV_PKTLIMIT_2 +#define NFE_JUMBO_MTU \ + (NFE_JUMBO_FRAMELEN - NFE_RX_HEADERS) +#define NFE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) +#define NFE_JSLOTS ((NFE_JUMBO_RX_RING_COUNT * 3) / 2) + +#define NFE_JRAWLEN (NFE_JUMBO_FRAMELEN + ETHER_ALIGN) +#define NFE_JLEN \ + (NFE_JRAWLEN + (sizeof(uint64_t) - (NFE_JRAWLEN % sizeof(uint64_t)))) +#define NFE_JPAGESZ PAGE_SIZE +#define NFE_RESID \ + (NFE_JPAGESZ - (NFE_JLEN * NFE_JSLOTS) % NFE_JPAGESZ) +#define NFE_JMEM ((NFE_JLEN * NFE_JSLOTS) + NFE_RESID) + +#define NFE_MAX_SCATTER 32 +#define NFE_TSO_MAXSGSIZE 4096 +#define NFE_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) + +#define NFE_IRQ_STATUS 0x000 +#define NFE_IRQ_MASK 0x004 +#define NFE_SETUP_R6 0x008 +#define NFE_IMTIMER 0x00c +#define NFE_MSI_MAP0 0x020 +#define NFE_MSI_MAP1 0x024 +#define NFE_MSI_IRQ_MASK 0x030 +#define NFE_MAC_RESET 0x03c +#define NFE_MISC1 0x080 +#define NFE_TX_CTL 0x084 +#define NFE_TX_STATUS 0x088 +#define NFE_RXFILTER 0x08c +#define NFE_RXBUFSZ 0x090 +#define NFE_RX_CTL 0x094 +#define NFE_RX_STATUS 0x098 +#define NFE_RNDSEED 0x09c +#define NFE_SETUP_R1 0x0a0 +#define NFE_SETUP_R2 0x0a4 +#define NFE_MACADDR_HI 0x0a8 +#define NFE_MACADDR_LO 0x0ac +#define NFE_MULTIADDR_HI 0x0b0 +#define NFE_MULTIADDR_LO 0x0b4 +#define NFE_MULTIMASK_HI 0x0b8 +#define NFE_MULTIMASK_LO 0x0bc +#define NFE_PHY_IFACE 0x0c0 +#define NFE_TX_RING_ADDR_LO 0x100 +#define NFE_RX_RING_ADDR_LO 0x104 +#define NFE_RING_SIZE 0x108 +#define NFE_TX_UNK 0x10c +#define NFE_LINKSPEED 0x110 +#define NFE_SETUP_R5 0x130 +#define NFE_SETUP_R3 0x13C +#define NFE_SETUP_R7 0x140 +#define NFE_RXTX_CTL 0x144 +#define NFE_TX_RING_ADDR_HI 0x148 +#define NFE_RX_RING_ADDR_HI 0x14c +#define NFE_TX_PAUSE_FRAME 0x170 +#define NFE_PHY_STATUS 0x180 +#define NFE_SETUP_R4 0x184 +#define NFE_STATUS 0x188 +#define NFE_PHY_SPEED 0x18c +#define NFE_PHY_CTL 0x190 +#define NFE_PHY_DATA 0x194 +#define NFE_WOL_CTL 0x200 +#define NFE_PATTERN_CRC 0x204 +#define NFE_PATTERN_MASK 0x208 +#define NFE_PWR_CAP 0x268 +#define NFE_PWR_STATE 0x26c +#define NFE_VTAG_CTL 0x300 +#define NFE_MSIX_MAP0 0x3e0 +#define NFE_MSIX_MAP1 0x3e4 +#define NFE_MSIX_IRQ_STATUS 0x3f0 +#define NFE_PWR2_CTL 0x600 + +#define NFE_MAC_RESET_MAGIC 0x00f3 + +#define NFE_MAC_ADDR_INORDER 0x8000 + +#define NFE_PHY_ERROR 0x00001 +#define NFE_PHY_WRITE 0x00400 +#define NFE_PHY_BUSY 0x08000 +#define NFE_PHYADD_SHIFT 5 + +#define NFE_STATUS_MAGIC 0x140000 + +#define NFE_R1_MAGIC_1000 0x14050f +#define NFE_R1_MAGIC_10_100 0x16070f +#define NFE_R1_MAGIC_DEFAULT 0x15050f +#define NFE_R2_MAGIC 0x16 +#define NFE_R4_MAGIC 0x08 +#define NFE_R6_MAGIC 0x03 +#define NFE_WOL_MAGIC 0x1111 +#define NFE_RX_START 0x01 +#define NFE_TX_START 0x01 + +#define NFE_IRQ_RXERR 0x0001 +#define NFE_IRQ_RX 0x0002 +#define NFE_IRQ_RX_NOBUF 0x0004 +#define NFE_IRQ_TXERR 0x0008 +#define NFE_IRQ_TX_DONE 0x0010 +#define NFE_IRQ_TIMER 0x0020 +#define NFE_IRQ_LINK 0x0040 +#define NFE_IRQ_TXERR2 0x0080 +#define NFE_IRQ_TX1 0x0100 + +#define NFE_IRQ_WANTED \ + (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \ + NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \ + NFE_IRQ_LINK) + +#define NFE_RXTX_KICKTX 0x0001 +#define NFE_RXTX_BIT1 0x0002 +#define NFE_RXTX_BIT2 0x0004 +#define NFE_RXTX_RESET 0x0010 +#define NFE_RXTX_VTAG_STRIP 0x0040 +#define NFE_RXTX_VTAG_INSERT 0x0080 +#define NFE_RXTX_RXCSUM 0x0400 +#define NFE_RXTX_V2MAGIC 0x2100 +#define NFE_RXTX_V3MAGIC 0x2200 +#define NFE_RXFILTER_MAGIC 0x007f0000 +#define NFE_PFF_RX_PAUSE (1 << 3) +#define NFE_PFF_LOOPBACK (1 << 4) +#define NFE_PFF_U2M (1 << 5) +#define NFE_PFF_PROMISC (1 << 7) +#define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) + +/* default interrupt moderation timer of 128us */ +#define NFE_IM_DEFAULT ((128 * 100) / 1024) + +#define NFE_VTAG_ENABLE (1 << 13) + +#define NFE_PWR_VALID (1 << 8) +#define NFE_PWR_WAKEUP (1 << 15) + +#define NFE_PWR2_WAKEUP_MASK 0x0f11 +#define NFE_PWR2_REVA3 (1 << 0) + +#define NFE_MEDIA_SET 0x10000 +#define NFE_MEDIA_1000T 0x00032 +#define NFE_MEDIA_100TX 0x00064 +#define NFE_MEDIA_10T 0x003e8 + +#define NFE_PHY_100TX (1 << 0) +#define NFE_PHY_1000T (1 << 1) +#define NFE_PHY_HDX (1 << 8) + +#define NFE_MISC1_MAGIC 0x003b0f3c +#define NFE_MISC1_TX_PAUSE (1 << 0) +#define NFE_MISC1_HDX (1 << 1) + +#define NFE_TX_PAUSE_FRAME_DISABLE 0x1ff0080 +#define NFE_TX_PAUSE_FRAME_ENABLE 0x0c00030 + +#define NFE_SEED_MASK 0x0003ff00 +#define NFE_SEED_10T 0x00007f00 +#define NFE_SEED_100TX 0x00002d00 +#define NFE_SEED_1000T 0x00007400 + +#define NFE_MSI_MESSAGES 8 +#define NFE_MSI_VECTOR_0_ENABLED 0x01 + +/* + * It seems that nForce supports only the lower 40 bits of a DMA address. + */ +#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) +#define NFE_DMA_MAXADDR BUS_SPACE_MAXADDR +#else +#define NFE_DMA_MAXADDR 0xFFFFFFFFFF +#endif + +#define NFE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) +#define NFE_ADDR_HI(x) ((u_int64_t) (x) >> 32) + +/* Rx/Tx descriptor */ +struct nfe_desc32 { + uint32_t physaddr; + uint16_t length; + uint16_t flags; +#define NFE_RX_FIXME_V1 0x6004 +#define NFE_RX_VALID_V1 (1 << 0) +#define NFE_TX_ERROR_V1 0x7808 +#define NFE_TX_LASTFRAG_V1 (1 << 0) +#define NFE_RX_ERROR1_V1 (1<<7) +#define NFE_RX_ERROR2_V1 (1<<8) +#define NFE_RX_ERROR3_V1 (1<<9) +#define NFE_RX_ERROR4_V1 (1<<10) +} __packed; + +#define NFE_V1_TXERR "\020" \ + "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \ + "\08FORCEDINT\03RETRY\00LASTPACKET" + +/* V2 Rx/Tx descriptor */ +struct nfe_desc64 { + uint32_t physaddr[2]; + uint32_t vtag; +#define NFE_RX_VTAG (1 << 16) +#define NFE_TX_VTAG (1 << 18) + uint16_t length; + uint16_t flags; +#define NFE_RX_FIXME_V2 0x4300 +#define NFE_RX_VALID_V2 (1 << 13) +#define NFE_TX_ERROR_V2 0x5c04 +#define NFE_TX_LASTFRAG_V2 (1 << 13) +#define NFE_RX_ERROR1_V2 (1<<2) +#define NFE_RX_ERROR2_V2 (1<<3) +#define NFE_RX_ERROR3_V2 (1<<4) +#define NFE_RX_ERROR4_V2 (1<<5) +} __packed; + +#define NFE_V2_TXERR "\020" \ + "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY" + +#define NFE_RING_ALIGN (sizeof(struct nfe_desc64)) + +/* flags common to V1/V2 descriptors */ +#define NFE_RX_UDP_CSUMOK (1 << 10) +#define NFE_RX_TCP_CSUMOK (1 << 11) +#define NFE_RX_IP_CSUMOK (1 << 12) +#define NFE_RX_ERROR (1 << 14) +#define NFE_RX_READY (1 << 15) +#define NFE_RX_LEN_MASK 0x3fff +#define NFE_TX_TCP_UDP_CSUM (1 << 10) +#define NFE_TX_IP_CSUM (1 << 11) +#define NFE_TX_TSO (1 << 12) +#define NFE_TX_TSO_SHIFT 14 +#define NFE_TX_VALID (1 << 15) + +#define NFE_READ(sc, reg) \ + bus_read_4((sc)->nfe_res[0], (reg)) + +#define NFE_WRITE(sc, reg, val) \ + bus_write_4((sc)->nfe_res[0], (reg), (val)) + +#define NFE_TIMEOUT 1000 + +#ifndef PCI_VENDOR_NVIDIA +#define PCI_VENDOR_NVIDIA 0x10DE +#endif + +#define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3 +#define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066 +#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6 +#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086 +#define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C +#define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6 +#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF +#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056 +#define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057 +#define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037 +#define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038 +#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268 +#define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269 +#define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372 +#define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373 +#define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5 +#define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6 +#define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee +#define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef +#define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450 +#define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451 +#define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452 +#define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453 +#define PCI_PRODUCT_NVIDIA_MCP67_LAN1 0x054c +#define PCI_PRODUCT_NVIDIA_MCP67_LAN2 0x054d +#define PCI_PRODUCT_NVIDIA_MCP67_LAN3 0x054e +#define PCI_PRODUCT_NVIDIA_MCP67_LAN4 0x054f + +#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 +#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 +#define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN +#define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 +#define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 +#define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 +#define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 + +#define NFE_DEBUG 0x0000 +#define NFE_DEBUG_INIT 0x0001 +#define NFE_DEBUG_RUNNING 0x0002 +#define NFE_DEBUG_DEINIT 0x0004 +#define NFE_DEBUG_IOCTL 0x0008 +#define NFE_DEBUG_INTERRUPT 0x0010 +#define NFE_DEBUG_API 0x0020 +#define NFE_DEBUG_LOCK 0x0040 +#define NFE_DEBUG_BROKEN 0x0080 +#define NFE_DEBUG_MII 0x0100 +#define NFE_DEBUG_ALL 0xFFFF diff --git a/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfevar.h b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfevar.h new file mode 100644 index 0000000000..8186bd307f --- /dev/null +++ b/src/add-ons/kernel/drivers/network/nforce/dev/nfe/if_nfevar.h @@ -0,0 +1,138 @@ +/* $OpenBSD: if_nfevar.h,v 1.11 2006/02/19 13:57:02 damien Exp $ */ + +/*- + * Copyright (c) 2005 Jonathan Gray + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * $FreeBSD: src/sys/dev/nfe/if_nfevar.h,v 1.5 2007/07/24 01:11:00 yongari Exp $ + */ + +struct nfe_tx_data { + bus_dmamap_t tx_data_map; + struct mbuf *m; +}; + +struct nfe_tx_ring { + bus_dma_tag_t tx_desc_tag; + bus_dmamap_t tx_desc_map; + bus_addr_t physaddr; + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + bus_dma_tag_t tx_data_tag; + struct nfe_tx_data data[NFE_TX_RING_COUNT]; + int queued; + int cur; + int next; +}; + +struct nfe_jpool_entry { + int slot; + SLIST_ENTRY(nfe_jpool_entry) jpool_entries; +}; + +struct nfe_rx_data { + bus_dmamap_t rx_data_map; + bus_addr_t paddr; + struct mbuf *m; +}; + +struct nfe_rx_ring { + bus_dma_tag_t rx_desc_tag; + bus_dmamap_t rx_desc_map; + bus_addr_t physaddr; + struct nfe_desc32 *desc32; + struct nfe_desc64 *desc64; + bus_dma_tag_t rx_data_tag; + bus_dmamap_t rx_spare_map; + struct nfe_rx_data data[NFE_RX_RING_COUNT]; + int cur; + int next; +}; + +struct nfe_jrx_ring { + bus_dma_tag_t jrx_desc_tag; + bus_dmamap_t jrx_desc_map; + bus_dma_tag_t jrx_jumbo_tag; + bus_dmamap_t jrx_jumbo_map; + void *jpool; + caddr_t jslots[NFE_JSLOTS]; + bus_addr_t jphysaddr; + struct nfe_desc32 *jdesc32; + struct nfe_desc64 *jdesc64; + bus_dma_tag_t jrx_data_tag; + bus_dmamap_t jrx_spare_map; + struct nfe_rx_data jdata[NFE_JUMBO_RX_RING_COUNT]; + int jcur; + int jnext; +}; + +struct nfe_softc { + struct ifnet *nfe_ifp; + device_t nfe_dev; + uint16_t nfe_devid; + uint16_t nfe_revid; + device_t nfe_miibus; + struct mtx nfe_mtx; + struct resource *nfe_res[1]; + struct resource *nfe_msix_res; + struct resource *nfe_msix_pba_res; + struct resource *nfe_irq[NFE_MSI_MESSAGES]; + void *nfe_intrhand[NFE_MSI_MESSAGES]; + struct callout nfe_stat_ch; + int nfe_watchdog_timer; + + bus_dma_tag_t nfe_parent_tag; + + int nfe_if_flags; + uint32_t nfe_flags; +#define NFE_JUMBO_SUP 0x0001 +#define NFE_40BIT_ADDR 0x0002 +#define NFE_HW_CSUM 0x0004 +#define NFE_HW_VLAN 0x0008 +#define NFE_PWR_MGMT 0x0010 +#define NFE_CORRECT_MACADDR 0x0020 +#define NFE_TX_FLOW_CTRL 0x0040 + int nfe_jumbo_disable; + uint32_t rxtxctl; + uint8_t mii_phyaddr; + uint8_t eaddr[ETHER_ADDR_LEN]; + struct taskqueue *nfe_tq; + struct task nfe_int_task; + struct task nfe_tx_task; + struct task nfe_link_task; + int nfe_link; + int nfe_suspended; + int nfe_framesize; + int nfe_process_limit; + int nfe_force_tx; + uint32_t nfe_irq_status; + uint32_t nfe_irq_mask; + uint32_t nfe_intrs; + uint32_t nfe_nointrs; + uint32_t nfe_msi; + uint32_t nfe_msix; + + struct nfe_tx_ring txq; + struct nfe_rx_ring rxq; + struct nfe_jrx_ring jrxq; + SLIST_HEAD(__nfe_jfreehead, nfe_jpool_entry) nfe_jfree_listhead; + SLIST_HEAD(__nfe_jinusehead, nfe_jpool_entry) nfe_jinuse_listhead; + struct mtx nfe_jlist_mtx; +}; + +struct nfe_type { + uint16_t vid_id; + uint16_t dev_id; + char *name; +};