i2p/haiku-beta6
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel_extreme: program the DPLL_SEL register on SandyBridge

Browse Source 
We need to assign PLLs to pipes and transcoders. The assignments on
previous generations were fixed, but now it's up to us to set it up.

Do the simplest thing for now: assign PLL1 to pipe A and PLL2 to pipe B.
This commit is contained in:
Adrien Destugues
2020-03-08 16:01:43 +01:00
parent 7991d1b79d
commit 168aff90a7
2 changed files with 35 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/intel_extreme/intel_extreme.h
+1
View File
@@ -723,6 +723,7 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
#define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
#define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED)
// Ironlake PCH reference clk control
#define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)