PCI: fix ram_address() to use phys_addr_t

Since it handles physical address it should really be this.

It's not like many drivers actually used it anyway. It shouldn't harm
compatibility, drivers calling it with only 32bit would leave garbage in
the higher bits but since on x86 it's a noop anyway, it would end up in
the MSB register tha's ignored because it expects a 32bit result.

headers/os/drivers/PCI.h

@@ -146,7 +146,7 @@ struct pci_module_info {
 						uint32	value		/* value to write */
 					);
 
-	void *			(*ram_address) (const void *physical_address_in_system_memory);
+	phys_addr_t		(*ram_address) (phys_addr_t physical_address_in_system_memory);
 
 	status_t		(*find_pci_capability) (
 						uchar	bus,

headers/os/drivers/bus/PCI.h

@@ -25,7 +25,7 @@ typedef struct pci_device_module_info {
 	void	(*write_io_32)(pci_device *device, addr_t mappedIOAddress,
 				uint32 value);
 
-	void	*(*ram_address)(pci_device *device, const void *physicalAddress);
+	phys_addr_t	(*ram_address)(pci_device *device, phys_addr_t physicalAddress);
 
 	uint32	(*read_pci_config)(pci_device *device, uint16 offset,
 				uint8 size);

src/add-ons/kernel/bus_managers/pci/arch/arm/pci_controller.cpp

@@ -20,8 +20,8 @@ pci_controller_init(void)
 }
 
 
-void *
-pci_ram_address(const void *physical_address_in_system_memory)
+phys_addr_t
+pci_ram_address(phys_addr_t physical_address_in_system_memory)
 {
-	return (void *)physical_address_in_system_memory;
+	return physical_address_in_system_memory;
 }

src/add-ons/kernel/bus_managers/pci/arch/m68k/pci_controller.cpp

@@ -44,8 +44,8 @@ pci_controller_init(void)
 }
 
 
-void *
-pci_ram_address(const void *physical_address_in_system_memory)
+phys_addr_t
+pci_ram_address(phys_addr_t physical_address_in_system_memory)
 {
-	return (void *)physical_address_in_system_memory;
+	return physical_address_in_system_memory;
 }

src/add-ons/kernel/bus_managers/pci/arch/ppc/pci_controller.cpp

@@ -29,8 +29,8 @@ pci_controller_init(void)
 }
 
 
-void *
-pci_ram_address(const void *physical_address_in_system_memory)
+phys_addr_t
+pci_ram_address(phys_addr_t physical_address_in_system_memory)
 {
-	return (void *)physical_address_in_system_memory;
+	return physical_address_in_system_memory;
 }

src/add-ons/kernel/bus_managers/pci/arch/x86/pci_controller.cpp

@@ -269,10 +269,10 @@ pci_mechpcie_get_max_bus_devices(void *cookie, int32 *count)
 }
 
 
-void *
-pci_ram_address(const void *physical_address_in_system_memory)
+phys_addr_t
+pci_ram_address(phys_addr_t physical_address_in_system_memory)
 {
-	return (void *)physical_address_in_system_memory;
+	return physical_address_in_system_memory;
 }
 
 

src/add-ons/kernel/bus_managers/pci/pci.cpp

@@ -1301,8 +1301,8 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
 					&dev->info.u.h0.base_register_sizes[i],
 					&dev->info.u.h0.base_register_flags[i],
 					i < 5 ? &dev->info.u.h0.base_registers_pci[i + 1] : NULL);
-				dev->info.u.h0.base_registers[i] = (addr_t)pci_ram_address(
-					(void *)(addr_t)dev->info.u.h0.base_registers_pci[i]);
+				dev->info.u.h0.base_registers[i] = (uint32)pci_ram_address(
+					dev->info.u.h0.base_registers_pci[i]);
 				i += barSize;
 			}
 
@@ -1310,8 +1310,8 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
 				PCI_command, 2, pcicmd);
 
-			dev->info.u.h0.rom_base = (addr_t)pci_ram_address(
-				(void *)(addr_t)dev->info.u.h0.rom_base_pci);
+			dev->info.u.h0.rom_base = (uint32)pci_ram_address(
+				dev->info.u.h0.rom_base_pci);
 
 			dev->info.u.h0.cardbus_cis = ReadConfig(dev->domain, dev->bus,
 				dev->device, dev->function, PCI_cardbus_cis, 4);
@@ -1347,8 +1347,8 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
 					&dev->info.u.h1.base_register_sizes[i],
 					&dev->info.u.h1.base_register_flags[i],
 					i < 5 ? &dev->info.u.h1.base_registers_pci[i + 1] : NULL);
-				dev->info.u.h1.base_registers[i] = (addr_t)pci_ram_address(
-					(void *)(addr_t)dev->info.u.h1.base_registers_pci[i]);
+				dev->info.u.h1.base_registers[i] = (uint32)pci_ram_address(
+					dev->info.u.h1.base_registers_pci[i]);
 				i += barSize;
 			}
 
@@ -1356,8 +1356,8 @@ PCI::_ReadHeaderInfo(PCIDev *dev)
 			WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
 				PCI_command, 2, pcicmd);
 
-			dev->info.u.h1.rom_base = (addr_t)pci_ram_address(
-				(void *)(addr_t)dev->info.u.h1.rom_base_pci);
+			dev->info.u.h1.rom_base = (uint32)pci_ram_address(
+				dev->info.u.h1.rom_base_pci);
 
 			dev->info.u.h1.primary_bus = ReadConfig(dev->domain, dev->bus,
 				dev->device, dev->function, PCI_primary_bus, 1);

src/add-ons/kernel/bus_managers/pci/pci_device.cpp

@@ -80,8 +80,8 @@ pci_device_write_pci_config(pci_device* device, uint16 offset, uint8 size,
 }
 
 
-static void*
-pci_device_ram_address(pci_device* device, const void* physicalAddress)
+static phys_addr_t
+pci_device_ram_address(pci_device* device, phys_addr_t physicalAddress)
 {
 	return pci_ram_address(physicalAddress);
 }

src/add-ons/kernel/bus_managers/pci/pci_private.h

@@ -44,7 +44,7 @@ extern pci_device_module_info gPCIDeviceModule;
 extern "C" {
 #endif
 
-void *		pci_ram_address(const void *physical_address_in_system_memory);
+phys_addr_t		pci_ram_address(phys_addr_t physical_address_in_system_memory);
 
 status_t 	pci_find_capability(uint8 bus, uint8 device, uint8 function,
 	uint8 cap_id, uint8 *offset);