From 18b2b9dab7c9da56624ce742f07ee1b8ffe3d37c Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Tue, 18 Jan 2005 18:37:27 +0000 Subject: [PATCH] The DMA_PUT register is write-only on some cards (confirmed NV11). git-svn-id: file:///srv/svn/repos/haiku/trunk/current@10846 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c index 1aab583a5e..537efc5744 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c @@ -777,6 +777,8 @@ static void nv_start_dma(void) /* note: * the actual FIFO channel that gets activated does not really matter: * all FIFO fill-level info actually points at the same registers. */ + /* note also: + * NV_GENERAL_DMAPUT is a write-only register on some cards (confirmed NV11). */ NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT + si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]) = (si->engine.dma.put << 2); @@ -786,8 +788,7 @@ for (dummy = 0; dummy < 2; dummy++) { LOG(4,("ACC_DMA: get $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET + si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]))); - LOG(4,("ACC_DMA: put $%08x\n", NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT + - si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])]))); + LOG(4,("ACC_DMA: put $%08x\n", si->engine.dma.put)); } }