diff --git a/headers/private/kernel/arch/x86/arch_cpu.h b/headers/private/kernel/arch/x86/arch_cpu.h
index 4365fe13ca..2ce6bd0b4d 100644
--- a/headers/private/kernel/arch/x86/arch_cpu.h
+++ b/headers/private/kernel/arch/x86/arch_cpu.h
@@ -29,6 +29,7 @@
 #define IA32_MSR_SYSENTER_CS			0x174
 #define IA32_MSR_SYSENTER_ESP			0x175
 #define IA32_MSR_SYSENTER_EIP			0x176
+#define IA32_MSR_ENERGY_PERF_BIAS		0x1b0
 #define IA32_MSR_MTRR_DEFAULT_TYPE		0x2ff
 #define IA32_MSR_MTRR_PHYSICAL_BASE_0	0x200
 #define IA32_MSR_MTRR_PHYSICAL_MASK_0	0x201
diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp b/src/system/kernel/arch/x86/arch_cpu.cpp
index 09359b64a4..08f0ed2b27 100644
--- a/src/system/kernel/arch/x86/arch_cpu.cpp
+++ b/src/system/kernel/arch/x86/arch_cpu.cpp
@@ -70,6 +70,16 @@ static const struct cpu_vendor_info vendor_info[VENDOR_NUM] = {
 
 #define K8_CMPHALT				(K8_SMIONCMPHALT | K8_C1EONCMPHALT)
 
+/*
+ * 0 favors highest performance while 15 corresponds to the maximum energy
+ * savings. 7 means balance between performance and energy savings.
+ * Refer to Section 14.3.4 in <Intel 64 and IA-32 Architectures Software
+ * Developer's Manual Volume 3>  for details
+ */
+#define ENERGY_PERF_BIAS_PERFORMANCE	0
+#define ENERGY_PERF_BIAS_BALANCE		7
+#define ENERGY_PERF_BIAS_POWERSAVE		15
+
 struct set_mtrr_parameter {
 	int32	index;
 	uint64	base;
@@ -787,6 +797,16 @@ arch_cpu_init_percpu(kernel_args *args, int cpu)
 		else
 			gCpuIdleFunc = halt_idle;
 	}
+
+	if (x86_check_feature(IA32_FEATURE_EPB, FEATURE_6_ECX)) {
+		uint64 msr = x86_read_msr(IA32_MSR_ENERGY_PERF_BIAS);
+		if ((msr & 0xf) == ENERGY_PERF_BIAS_PERFORMANCE) {
+			msr &= ~0xf;
+			msr |= ENERGY_PERF_BIAS_BALANCE;
+			x86_write_msr(IA32_MSR_ENERGY_PERF_BIAS, msr);
+		}
+	}
+
 	return 0;
 }