diff --git a/headers/private/graphics/nvidia/nv_macros.h b/headers/private/graphics/nvidia/nv_macros.h
index 40af20ccd3..590c9ec2a3 100644
--- a/headers/private/graphics/nvidia/nv_macros.h
+++ b/headers/private/graphics/nvidia/nv_macros.h
@@ -649,6 +649,7 @@
 #define NVDAC_NV10_CURSYNC	0x00680404
 #define NVDAC_PIXPLLC		0x00680508
 #define NVDAC_PLLSEL		0x0068050c
+#define NVDAC_NV30_PLLSETUP	0x00680524
 #define NVDAC_OUTPUT		0x0068052c
 #define NVDAC_PIXPLLC2		0x00680578
 #define NVDAC_NV40_PLLSEL2	0x00680580
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_dac.c b/src/add-ons/accelerants/nvidia/engine/nv_dac.c
index 5ed15e2c4e..11f75c2107 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_dac.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_dac.c
@@ -168,14 +168,24 @@ status_t nv_dac_set_pix_pll(display_mode target)
 
 	/* signal that we actually want to set the mode */
 	result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
-	if (result != B_OK)
-	{
-		return result;
-	}
+	if (result != B_OK) return result;
 
 	/* dump old setup for learning purposes */
 	nv_dac_dump_pix_pll();
 
+	/* some logging for learning purposes */
+	LOG(4,("DAC: current NV30_PLLSETUP settings: $%08x\n", DACR(NV30_PLLSETUP)));
+	/* this register seems to (dis)connect functions blocks and PLLs:
+	 * there seem to be two PLL types per function block (on some cards),
+	 * b16-17 DAC1clk, b18-19 DAC2clk, b20-21 GPUclk, b22-23 MEMclk. */
+	LOG(4,("DAC: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040)));
+
+	/* disable spread spectrum modes for the pixelPLLs _first_ */
+	/* spread spectrum: b0,1 = GPUclk, b2,3 = MEMclk, b4,5 = DAC1clk, b6,7 = DAC2clk;
+	 * b16-19 influence clock routing to digital outputs (internal/external LVDS transmitters?) */
+	if (si->ps.card_arch >= NV30A)
+		DACW(NV30_PLLSETUP, (DACR(NV30_PLLSETUP) & ~0x000000f0));
+
 	/* we offer this option because some panels have very tight restrictions,
 	 * and there's no overlapping settings range that makes them all work.
 	 * note:
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_dac2.c b/src/add-ons/accelerants/nvidia/engine/nv_dac2.c
index babecb3caa..5a1138cff0 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_dac2.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_dac2.c
@@ -171,14 +171,24 @@ status_t nv_dac2_set_pix_pll(display_mode target)
 
 	/* signal that we actually want to set the mode */
 	result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
-	if (result != B_OK)
-	{
-		return result;
-	}
+	if (result != B_OK) return result;
 
 	/* dump old setup for learning purposes */
 	nv_dac2_dump_pix_pll();
 
+	/* some logging for learning purposes */
+	LOG(4,("DAC2: current NV30_PLLSETUP settings: $%08x\n", DACR(NV30_PLLSETUP)));
+	/* this register seems to (dis)connect functions blocks and PLLs:
+	 * there seem to be two PLL types per function block (on some cards),
+	 * b16-17 DAC1clk, b18-19 DAC2clk, b20-21 GPUclk, b22-23 MEMclk. */
+	LOG(4,("DAC2: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040)));
+
+	/* disable spread spectrum modes for the pixelPLLs _first_ */
+	/* spread spectrum: b0,1 = GPUclk, b2,3 = MEMclk, b4,5 = DAC1clk, b6,7 = DAC2clk;
+	 * b16-19 influence clock routing to digital outputs (internal/external LVDS transmitters?) */
+	if (si->ps.card_arch >= NV30A)
+		DACW(NV30_PLLSETUP, (DACR(NV30_PLLSETUP) & ~0x000000f0));
+
 	/* we offer this option because some panels have very tight restrictions,
 	 * and there's no overlapping settings range that makes them all work.
 	 * note:
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c
index ab4c481207..f95bc29d5f 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_general.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c
@@ -92,7 +92,7 @@ status_t nv_general_powerup()
 {
 	status_t status;
 
-	LOG(1,("POWERUP: Haiku nVidia Accelerant 1.02 running.\n"));
+	LOG(1,("POWERUP: Haiku nVidia Accelerant 1.03 running.\n"));
 
 	/* log VBLANK INT usability status */
 	if (si->ps.int_assigned)
diff --git a/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html b/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html
index 85ae3a6b12..1ee09a159b 100644
--- a/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html
+++ b/src/add-ons/kernel/drivers/graphics/nvidia/UPDATE.html
@@ -4,7 +4,7 @@
 </head>
 <body>
 <p><h2>Changes done for each driverversion:</h2></p>
-<p><h1>head (SVN 1.01, Rudolf)</h1></p>
+<p><h1>head (SVN 1.03, Rudolf)</h1></p>
 <ul>
 <li>Fixed driver assuming enabling AGP mode succeeded on some occasions if it did not block it itself. Blocking AGP mode completely via the AGP busmanager (option 'block_agp') resulted in a crashing acceleration engine because it was setup for AGP transfers instead of using PCI transfers. Error was solved with help from user kraton.
 <li>Fixed shared_info struct problem occuring when 3D 'accelerant' is used (tested Alpha 4.1): the TVencoder type definition list apparantly gets some memory assigned these days when done inside the definition of shared_info. Moved encoder list outside the shared_info definition.
@@ -26,7 +26,8 @@
 <li>DDC/EDID fetching now also works on GCC4 binaries due to a fixed fault in the accelerants/common code (which is used for that function);
 <li>Added support for Haiku specific driverhook GET_PREFERRED_DISPLAY_MODE. Laptops should now also startup in native mode automatically at first system boot;
 <li>Rewrote framebuffer memory detection. Accelerant now only uses the amount of RAM mapped by the kerneldriver as maximum. This fixes black screen at app_server startup on a number of GF6xxx and GF7xxx cards;
-<li>Finally(!) fixed PLL selection trouble on NV40 architecture (Geforce 6xxx and 7xxx) cards. Now dualhead should (almost) always work OK, and now low-res bootscreens should nolonger result in 'frequency out of range' messages on DVI connected screens.
+<li>Finally(!) fixed PLL selection trouble on NV40 architecture (Geforce 6xxx and 7xxx) cards. Now dualhead should (almost) always work OK, and now low-res bootscreens should nolonger result in 'frequency out of range' messages on DVI connected screens;
+<li>Fixed shivering display on some systems (confirmed a Geforce 5200 laptop): Pixelclocks should <strong>never</strong> be setup for spread spectrum on analog connections.
 </ul>
 <p><h1>nv_driver 0.80 (Rudolf)</h1></p>
 <ul>