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added locking

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@4860 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
beveloper
2003-09-29 19:06:40 +00:00
parent ee3ca5c227
commit 1aad0f29d1
1 changed files with 12 additions and 0 deletions
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src/add-ons/kernel/bus_managers/pci/arch/x86/pci_config.c
+12
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@@ -123,6 +123,7 @@ uint32
pci_mech1_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size) pci_mech1_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size)
{ {
uint32 result; uint32 result;
cpu_status status;
if (device > 31 || function > 7 || (size != 1 && size != 2 && size != 4) if (device > 31 || function > 7 || (size != 1 && size != 2 && size != 4)
|| (size == 2 && (offset & 3) == 3) || (size == 4 && (offset & 3) != 0)) { || (size == 2 && (offset & 3) == 3) || (size == 4 && (offset & 3) != 0)) {
dprintf("PCI: mech1 can't read config for bus %u, device %u, function %u, offset %u, size %u\n", dprintf("PCI: mech1 can't read config for bus %u, device %u, function %u, offset %u, size %u\n",
@@ -130,6 +131,7 @@ pci_mech1_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uin
return 0xffffffff; return 0xffffffff;
} }
PCI_LOCK_CONFIG(status);
out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT); out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT);
switch (size) { switch (size) {
case 1: case 1:
@@ -144,6 +146,7 @@ pci_mech1_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uin
default: default:
result = 0xffffffff; result = 0xffffffff;
} }
PCI_UNLOCK_CONFIG(status);
return result; return result;
} }
@@ -151,6 +154,7 @@ pci_mech1_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uin
void void
pci_mech1_write_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size, uint32 value) pci_mech1_write_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size, uint32 value)
{ {
cpu_status status;
if (device > 31 || function > 7 || (size != 1 && size != 2 && size != 4) if (device > 31 || function > 7 || (size != 1 && size != 2 && size != 4)
|| (size == 2 && (offset & 3) == 3) || (size == 4 && (offset & 3) != 0)) { || (size == 2 && (offset & 3) == 3) || (size == 4 && (offset & 3) != 0)) {
dprintf("PCI: mech1 can't write config for bus %u, device %u, function %u, offset %u, size %u\n", dprintf("PCI: mech1 can't write config for bus %u, device %u, function %u, offset %u, size %u\n",
@@ -158,6 +162,7 @@ pci_mech1_write_config(uint8 bus, uint8 device, uint8 function, uint8 offset, ui
return; return;
} }
PCI_LOCK_CONFIG(status);
out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT); out32(PCI_MECH1_REQ_DATA(bus, device, function, offset), PCI_MECH1_REQ_PORT);
switch (size) { switch (size) {
case 1: case 1:
@@ -170,6 +175,7 @@ pci_mech1_write_config(uint8 bus, uint8 device, uint8 function, uint8 offset, ui
out32(value, PCI_MECH1_DATA_PORT); out32(value, PCI_MECH1_DATA_PORT);
break; break;
} }
PCI_UNLOCK_CONFIG(status);
} }
@@ -177,12 +183,14 @@ uint32
pci_mech2_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size) pci_mech2_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size)
{ {
uint32 result; uint32 result;
cpu_status status;
if (device > 15 || function > 7 || (size != 1 && size != 2 && size != 4)) { if (device > 15 || function > 7 || (size != 1 && size != 2 && size != 4)) {
dprintf("PCI: mech2 can't read config for bus %u, device %u, function %u, offset %u, size %u\n", dprintf("PCI: mech2 can't read config for bus %u, device %u, function %u, offset %u, size %u\n",
bus, device, function, offset, size); bus, device, function, offset, size);
return 0xffffffff; return 0xffffffff;
} }
PCI_LOCK_CONFIG(status);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT); out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
out8(bus, PCI_MECH2_FORWARD_PORT); out8(bus, PCI_MECH2_FORWARD_PORT);
switch (size) { switch (size) {
@@ -199,6 +207,7 @@ pci_mech2_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uin
result = 0xffffffff; result = 0xffffffff;
} }
out8(0, PCI_MECH2_ENABLE_PORT); out8(0, PCI_MECH2_ENABLE_PORT);
PCI_UNLOCK_CONFIG(status);
return result; return result;
} }
@@ -206,12 +215,14 @@ pci_mech2_read_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uin
void void
pci_mech2_write_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size, uint32 value) pci_mech2_write_config(uint8 bus, uint8 device, uint8 function, uint8 offset, uint8 size, uint32 value)
{ {
cpu_status status;
if (device > 15 || function > 7 || (size != 1 && size != 2 && size != 4)) { if (device > 15 || function > 7 || (size != 1 && size != 2 && size != 4)) {
dprintf("PCI: mech2 can't write config for bus %u, device %u, function %u, offset %u, size %u\n", dprintf("PCI: mech2 can't write config for bus %u, device %u, function %u, offset %u, size %u\n",
bus, device, function, offset, size); bus, device, function, offset, size);
return; return;
} }
PCI_LOCK_CONFIG(status);
out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT); out8((uint8)(0xf0 | (function << 1)), PCI_MECH2_ENABLE_PORT);
out8(bus, PCI_MECH2_FORWARD_PORT); out8(bus, PCI_MECH2_FORWARD_PORT);
switch (size) { switch (size) {
@@ -226,6 +237,7 @@ pci_mech2_write_config(uint8 bus, uint8 device, uint8 function, uint8 offset, ui
break; break;
} }
out8(0, PCI_MECH2_ENABLE_PORT); out8(0, PCI_MECH2_ENABLE_PORT);
PCI_UNLOCK_CONFIG(status);
} }