added via accelerant, a copy of skeleton driver yet.
git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13591 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
@@ -0,0 +1,520 @@
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/*
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Copyright 1999, Be Incorporated. All Rights Reserved.
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This file may be used under the terms of the Be Sample Code License.
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Other authors:
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Mark Watson,
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Apsed,
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Rudolf Cornelissen 11/2002-4/2004
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*/
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#define MODULE_BIT 0x00200000
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#include "acc_std.h"
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/*
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Enable/Disable interrupts. Just a wrapper around the
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ioctl() to the kernel driver.
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*/
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static void interrupt_enable(bool flag) {
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status_t result;
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eng_set_bool_state sbs;
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/* set the magic number so the driver knows we're for real */
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sbs.magic = SKEL_PRIVATE_DATA_MAGIC;
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sbs.do_it = flag;
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/* contact driver and get a pointer to the registers and shared data */
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result = ioctl(fd, ENG_RUN_INTERRUPTS, &sbs, sizeof(sbs));
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}
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/* First validate the mode, then call lots of bit banging stuff to set the mode(s)! */
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status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
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{
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/* BOUNDS WARNING:
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* It's impossible to deviate whatever small amount in a display_mode if the lower
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* and upper limits are the same!
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* Besides:
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* BeOS (tested R5.0.3PE) is failing BWindowScreen::SetFrameBuffer() if PROPOSEMODE
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* returns B_BAD_VALUE!
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* Which means PROPOSEMODE should not return that on anything except on
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* deviations for:
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* display_mode.virtual_width;
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* display_mode.virtual_height;
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* display_mode.timing.h_display;
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* display_mode.timing.v_display;
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* So:
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* We don't use bounds here by making sure bounds and target are the same struct!
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* (See the call to PROPOSE_DISPLAY_MODE below) */
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display_mode /*bounds,*/ target;
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uint8 colour_depth1 = 32;
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// status_t result;
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uint32 startadd,startadd_right;
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// bool display, h, v;
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// bool crt1, crt2, cross;
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/* Adjust mode to valid one and fail if invalid */
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target /*= bounds*/ = *mode_to_set;
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/* show the mode bits */
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LOG(1, ("SETMODE: (ENTER) initial modeflags: $%08x\n", target.flags));
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LOG(1, ("SETMODE: requested target pixelclock %dkHz\n", target.timing.pixel_clock));
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LOG(1, ("SETMODE: requested virtual_width %d, virtual_height %d\n",
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target.virtual_width, target.virtual_height));
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/* See BOUNDS WARNING above... */
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if (PROPOSE_DISPLAY_MODE(&target, &target, &target) == B_ERROR) return B_ERROR;
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/* if not dualhead capable card clear dualhead flags */
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if (!(target.flags & DUALHEAD_CAPABLE))
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{
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target.flags &= ~DUALHEAD_BITS;
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}
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/* if not TVout capable card clear TVout flags */
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if (!(target.flags & TV_CAPABLE))
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{
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target.flags &= ~TV_BITS;
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}
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LOG(1, ("SETMODE: (CONT.) validated command modeflags: $%08x\n", target.flags));
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/* disable interrupts using the kernel driver */
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interrupt_enable(false);
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/* find current DPMS state, then turn off screen(s) */
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// head1_dpms_fetch(&display, &h, &v);
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// head1_dpms(false, false, false);
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// if (si->ps.secondary_head) head2_dpms(false, false, false);
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/*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/
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startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
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/* calculate and set new mode bytes_per_row */
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eng_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode);
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/*Perform the very long mode switch!*/
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if (target.flags & DUALHEAD_BITS) /*if some dualhead mode*/
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{
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uint8 colour_depth2 = colour_depth1;
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/* init display mode for secondary head */
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display_mode target2 = target;
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LOG(1,("SETMODE: setting DUALHEAD mode\n"));
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/* validate flags for secondary TVout */
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// if ((i2c_sec_tv_adapter() != B_OK) && (target2.flags & TV_BITS))
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// {
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// target.flags &= ~TV_BITS;//still needed for some routines...
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// target2.flags &= ~TV_BITS;
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// LOG(1,("SETMODE: blocking TVout: no TVout cable connected!\n"));
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// }
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/* detect which connectors have a CRT connected */
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//fixme: 'hot-plugging' for analog monitors removed: remove code as well;
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//or make it work with digital panels connected as well.
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// crt1 = eng_dac_crt_connected();
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// crt2 = eng_dac2_crt_connected();
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/* connect outputs 'straight-through' */
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// if (crt1)
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// {
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/* connector1 is used as primary output */
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// cross = false;
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// }
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// else
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// {
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// if (crt2)
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/* connector2 is used as primary output */
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// cross = true;
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// else
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/* no CRT detected: assume connector1 is used as primary output */
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// cross = false;
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// }
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/* set output connectors assignment if possible */
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// if ((target.flags & DUALHEAD_BITS) == DUALHEAD_SWITCH)
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/* invert output assignment in switch mode */
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// eng_general_head_select(true);
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// else
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// eng_general_head_select(false);
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/* set the pixel clock PLL(s) */
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LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
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// if (head1_set_pix_pll(target) == B_ERROR)
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// LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n"));
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/* we do not need to set the pixelclock here for a head that's in TVout mode */
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// if (!(target2.flags & TV_BITS))
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// {
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// LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
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// if (head2_set_pix_pll(target2) == B_ERROR)
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// LOG(8,("SETMODE: error setting pixel clock (DAC2)\n"));
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// }
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/*set the colour depth for CRTC1 and the DAC */
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switch(target.space)
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{
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case B_CMAP8:
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colour_depth1 = 8;
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// head1_mode(BPP8, 1.0);
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// head1_depth(BPP8);
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break;
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case B_RGB15_LITTLE:
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colour_depth1 = 16;
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// head1_mode(BPP15, 1.0);
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// head1_depth(BPP15);
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break;
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case B_RGB16_LITTLE:
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colour_depth1 = 16;
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// head1_mode(BPP16, 1.0);
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// head1_depth(BPP16);
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break;
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case B_RGB32_LITTLE:
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colour_depth1 = 32;
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// head1_mode(BPP32, 1.0);
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// head1_depth(BPP32);
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break;
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}
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/*set the colour depth for CRTC2 and DAC2 */
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switch(target2.space)
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{
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case B_CMAP8:
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colour_depth2 = 8;
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// head2_mode(BPP8, 1.0);
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// head2_depth(BPP8);
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break;
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case B_RGB15_LITTLE:
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colour_depth2 = 16;
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// head2_mode(BPP15, 1.0);
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// head2_depth(BPP15);
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break;
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case B_RGB16_LITTLE:
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colour_depth2 = 16;
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// head2_mode(BPP16, 1.0);
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// head2_depth(BPP16);
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break;
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case B_RGB32_LITTLE:
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colour_depth2 = 32;
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// head2_mode(BPP32, 1.0);
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// head2_depth(BPP32);
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break;
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}
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/* check if we are doing interlaced TVout mode */
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si->interlaced_tv_mode = false;
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/* if ((target2.flags & TV_BITS) && (si->ps.card_type >= G450))
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si->interlaced_tv_mode = true;
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*/
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/*set the display(s) pitches*/
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// head1_set_display_pitch ();
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//fixme: seperate for real dualhead modes:
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//we need a secondary si->fbc!
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// head2_set_display_pitch ();
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/*work out where the "right" screen starts*/
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startadd_right = startadd + (target.timing.h_display * (colour_depth1 >> 3));
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/* Tell card what memory to display */
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switch (target.flags & DUALHEAD_BITS)
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{
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case DUALHEAD_ON:
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case DUALHEAD_SWITCH:
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// head1_set_display_start(startadd,colour_depth1);
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// head2_set_display_start(startadd_right,colour_depth2);
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break;
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case DUALHEAD_CLONE:
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// head1_set_display_start(startadd,colour_depth1);
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// head2_set_display_start(startadd,colour_depth2);
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break;
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}
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/* set the timing */
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// head1_set_timing(target);
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/* we do not need to setup CRTC2 here for a head that's in TVout mode */
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// if (!(target2.flags & TV_BITS)) result = head2_set_timing(target2);
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/* TVout support: setup CRTC2 and it's pixelclock */
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// if (si->ps.tvout && (target2.flags & TV_BITS)) maventv_init(target2);
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}
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else /* single head mode */
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{
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status_t status;
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int colour_mode = BPP32;
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/* connect output */
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if (si->ps.secondary_head)
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{
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/* detect which connectors have a CRT connected */
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//fixme: 'hot-plugging' for analog monitors removed: remove code as well;
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//or make it work with digital panels connected as well.
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// crt1 = eng_dac_crt_connected();
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// crt2 = eng_dac2_crt_connected();
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/* connect outputs 'straight-through' */
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// if (crt1)
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// {
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/* connector1 is used as primary output */
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// cross = false;
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// }
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// else
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// {
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// if (crt2)
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/* connector2 is used as primary output */
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// cross = true;
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// else
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/* no CRT detected: assume connector1 is used as primary output */
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// cross = false;
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// }
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/* set output connectors assignment if possible */
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eng_general_head_select(false);
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}
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switch(target.space)
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{
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case B_CMAP8: colour_depth1 = 8; colour_mode = BPP8; break;
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case B_RGB15_LITTLE: colour_depth1 = 16; colour_mode = BPP15; break;
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case B_RGB16_LITTLE: colour_depth1 = 16; colour_mode = BPP16; break;
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case B_RGB32_LITTLE: colour_depth1 = 32; colour_mode = BPP32; break;
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default:
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LOG(8,("SETMODE: Invalid singlehead colour depth 0x%08x\n", target.space));
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return B_ERROR;
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}
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/* set the pixel clock PLL */
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// status = head1_set_pix_pll(target);
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status = B_OK;
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if (status==B_ERROR)
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LOG(8,("CRTC: error setting pixel clock (internal DAC)\n"));
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|
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/* set the colour depth for CRTC1 and the DAC */
|
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/* first set the colordepth */
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// head1_depth(colour_mode);
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/* then(!) program the PAL (<8bit colordepth does not support 8bit PAL) */
|
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// head1_mode(colour_mode,1.0);
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/* set the display pitch */
|
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// head1_set_display_pitch();
|
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|
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/* tell the card what memory to display */
|
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// head1_set_display_start(startadd,colour_depth1);
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/* set the timing */
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// head1_set_timing(target);
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//fixme: shut-off the videoPLL if it exists...
|
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}
|
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/* update driver's mode store */
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si->dm = target;
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/* turn screen one on */
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// head1_dpms(display, h, v);
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/* turn screen two on if a dualhead mode is active */
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// if (target.flags & DUALHEAD_BITS) head2_dpms(display,h,v);
|
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|
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/* set up acceleration for this mode */
|
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// eng_acc_init();
|
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/* set up overlay unit for this mode */
|
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// eng_bes_init();
|
||||
|
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LOG(1,("SETMODE: booted since %f mS\n", system_time()/1000.0));
|
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|
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/* enable interrupts using the kernel driver */
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interrupt_enable(true);
|
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|
||||
/* optimize memory-access if needed */
|
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// head1_mem_priority(colour_depth1);
|
||||
|
||||
/* Tune RAM CAS-latency if needed. Must be done *here*! */
|
||||
eng_set_cas_latency();
|
||||
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
/*
|
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Set which pixel of the virtual frame buffer will show up in the
|
||||
top left corner of the display device. Used for page-flipping
|
||||
games and virtual desktops.
|
||||
*/
|
||||
status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) {
|
||||
uint8 colour_depth;
|
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uint32 startadd,startadd_right;
|
||||
|
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LOG(4,("MOVE_DISPLAY: h %d, v %d\n", h_display_start, v_display_start));
|
||||
|
||||
/* nVidia cards support pixelprecise panning on both heads in all modes:
|
||||
* No stepping granularity needed! */
|
||||
|
||||
/* determine bits used for the colordepth */
|
||||
switch(si->dm.space)
|
||||
{
|
||||
case B_CMAP8:
|
||||
colour_depth=8;
|
||||
break;
|
||||
case B_RGB15_LITTLE:
|
||||
case B_RGB16_LITTLE:
|
||||
colour_depth=16;
|
||||
break;
|
||||
case B_RGB24_LITTLE:
|
||||
colour_depth=24;
|
||||
break;
|
||||
case B_RGB32_LITTLE:
|
||||
colour_depth=32;
|
||||
break;
|
||||
default:
|
||||
return B_ERROR;
|
||||
}
|
||||
|
||||
/* do not run past end of display */
|
||||
switch (si->dm.flags & DUALHEAD_BITS)
|
||||
{
|
||||
case DUALHEAD_ON:
|
||||
case DUALHEAD_SWITCH:
|
||||
if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width)
|
||||
return B_ERROR;
|
||||
break;
|
||||
default:
|
||||
if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width)
|
||||
return B_ERROR;
|
||||
break;
|
||||
}
|
||||
if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height)
|
||||
return B_ERROR;
|
||||
|
||||
/* everybody remember where we parked... */
|
||||
si->dm.h_display_start = h_display_start;
|
||||
si->dm.v_display_start = v_display_start;
|
||||
|
||||
/* actually set the registers */
|
||||
//fixme: seperate both heads: we need a secondary si->fbc!
|
||||
startadd = v_display_start * si->fbc.bytes_per_row;
|
||||
startadd += h_display_start * (colour_depth >> 3);
|
||||
startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer;
|
||||
startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3);
|
||||
|
||||
interrupt_enable(false);
|
||||
|
||||
switch (si->dm.flags & DUALHEAD_BITS)
|
||||
{
|
||||
case DUALHEAD_ON:
|
||||
case DUALHEAD_SWITCH:
|
||||
// head1_set_display_start(startadd,colour_depth);
|
||||
// head2_set_display_start(startadd_right,colour_depth);
|
||||
break;
|
||||
case DUALHEAD_OFF:
|
||||
// head1_set_display_start(startadd,colour_depth);
|
||||
break;
|
||||
case DUALHEAD_CLONE:
|
||||
// head1_set_display_start(startadd,colour_depth);
|
||||
// head2_set_display_start(startadd,colour_depth);
|
||||
break;
|
||||
}
|
||||
|
||||
interrupt_enable(true);
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
/* Set the indexed color palette */
|
||||
void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags) {
|
||||
int i;
|
||||
uint8 *r,*g,*b;
|
||||
|
||||
/* Protect gamma correction when not in CMAP8 */
|
||||
if (si->dm.space != B_CMAP8) return;
|
||||
|
||||
r=si->color_data;
|
||||
g=r+256;
|
||||
b=g+256;
|
||||
|
||||
i=first;
|
||||
while (count--)
|
||||
{
|
||||
r[i]=*color_data++;
|
||||
g[i]=*color_data++;
|
||||
b[i]=*color_data++;
|
||||
i++;
|
||||
}
|
||||
// head1_palette(r,g,b);
|
||||
if (si->dm.flags & DUALHEAD_BITS) head2_palette(r,g,b);
|
||||
}
|
||||
|
||||
/* Put the display into one of the Display Power Management modes. */
|
||||
status_t SET_DPMS_MODE(uint32 dpms_flags) {
|
||||
interrupt_enable(false);
|
||||
|
||||
LOG(4,("SET_DPMS_MODE: 0x%08x\n", dpms_flags));
|
||||
|
||||
if (si->dm.flags & DUALHEAD_BITS) /*dualhead*/
|
||||
{
|
||||
switch(dpms_flags)
|
||||
{
|
||||
case B_DPMS_ON: /* H: on, V: on, display on */
|
||||
// head1_dpms(true, true, true);
|
||||
// if (si->ps.secondary_head) head2_dpms(true, true, true);
|
||||
break;
|
||||
case B_DPMS_STAND_BY:
|
||||
// head1_dpms(false, false, true);
|
||||
// if (si->ps.secondary_head) head2_dpms(false, false, true);
|
||||
break;
|
||||
case B_DPMS_SUSPEND:
|
||||
// head1_dpms(false, true, false);
|
||||
// if (si->ps.secondary_head) head2_dpms(false, true, false);
|
||||
break;
|
||||
case B_DPMS_OFF: /* H: off, V: off, display off */
|
||||
// head1_dpms(false, false, false);
|
||||
// if (si->ps.secondary_head) head2_dpms(false, false, false);
|
||||
break;
|
||||
default:
|
||||
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags));
|
||||
interrupt_enable(true);
|
||||
return B_ERROR;
|
||||
}
|
||||
}
|
||||
else /* singlehead */
|
||||
{
|
||||
switch(dpms_flags)
|
||||
{
|
||||
case B_DPMS_ON: /* H: on, V: on, display on */
|
||||
// head1_dpms(true, true, true);
|
||||
break;
|
||||
case B_DPMS_STAND_BY:
|
||||
// head1_dpms(false, false, true);
|
||||
break;
|
||||
case B_DPMS_SUSPEND:
|
||||
// head1_dpms(false, true, false);
|
||||
break;
|
||||
case B_DPMS_OFF: /* H: off, V: off, display off */
|
||||
// head1_dpms(false, false, false);
|
||||
break;
|
||||
default:
|
||||
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags));
|
||||
interrupt_enable(true);
|
||||
return B_ERROR;
|
||||
}
|
||||
}
|
||||
interrupt_enable(true);
|
||||
return B_OK;
|
||||
}
|
||||
|
||||
/* Report device DPMS capabilities */
|
||||
uint32 DPMS_CAPABILITIES(void) {
|
||||
return (B_DPMS_ON | B_DPMS_STAND_BY | B_DPMS_SUSPEND | B_DPMS_OFF);
|
||||
}
|
||||
|
||||
/* Return the current DPMS mode */
|
||||
uint32 DPMS_MODE(void) {
|
||||
bool display, h, v;
|
||||
|
||||
interrupt_enable(false);
|
||||
// head1_dpms_fetch(&display, &h, &v);
|
||||
display = h = v = true;
|
||||
|
||||
interrupt_enable(true);
|
||||
|
||||
if (display && h && v)
|
||||
return B_DPMS_ON;
|
||||
else if(v)
|
||||
return B_DPMS_STAND_BY;
|
||||
else if(h)
|
||||
return B_DPMS_SUSPEND;
|
||||
else
|
||||
return B_DPMS_OFF;
|
||||
}
|
||||
Reference in New Issue
Block a user