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arm64: Cleanup VMSAv8TranslationMap::FreeTable

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Change-Id: Ib2cb0f728e4ca4b69096b21ae336d43c621a71e7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8421
Haiku-Format: Haiku-format Bot <[email protected]>
Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Owen Anderson
2024-09-30 15:48:51 +00:00
committed by waddlesplash
parent df59dfec3b
commit 1c408b7298
2 changed files with 9 additions and 14 deletions
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src/system/kernel/arch/arm64/VMSAv8TranslationMap.cpp
+8 -12
View File
@@ -141,7 +141,7 @@ VMSAv8TranslationMap::~VMSAv8TranslationMap()
ASSERT(fRefcount == 0); ASSERT(fRefcount == 0);
{ {
ThreadCPUPinner pinner(thread_get_current_thread()); ThreadCPUPinner pinner(thread_get_current_thread());
FreeTable(fPageTable, 0, fInitialLevel, [](int level, uint64_t oldPte) {}); FreeTable(fPageTable, 0, fInitialLevel);
} }
{ {
@@ -277,12 +277,11 @@ VMSAv8TranslationMap::TableFromPa(phys_addr_t pa)
} }
template<typename EntryRemoved>
void void
VMSAv8TranslationMap::FreeTable(phys_addr_t ptPa, uint64_t va, int level, VMSAv8TranslationMap::FreeTable(phys_addr_t ptPa, uint64_t va, int level)
EntryRemoved &&entryRemoved)
{ {
ASSERT(level < 4); ASSERT(level < 4);
InterruptsSpinLocker locker(sAsidLock);
int tableBits = fPageBits - 3; int tableBits = fPageBits - 3;
uint64_t tableSize = 1UL << tableBits; uint64_t tableSize = 1UL << tableBits;
@@ -297,21 +296,18 @@ VMSAv8TranslationMap::FreeTable(phys_addr_t ptPa, uint64_t va, int level,
uint64_t oldPte = (uint64_t) atomic_get_and_set64((int64*) &pt[i], 0); uint64_t oldPte = (uint64_t) atomic_get_and_set64((int64*) &pt[i], 0);
if (level < 3 && (oldPte & kPteTypeMask) == kPteTypeL012Table) { if (level < 3 && (oldPte & kPteTypeMask) == kPteTypeL012Table) {
FreeTable(oldPte & kPteAddrMask, nextVa, level + 1, entryRemoved); FreeTable(oldPte & kPteAddrMask, nextVa, level + 1);
} else if ((oldPte & kPteTypeMask) != 0) { } else if ((oldPte & kPteTypeMask) != 0) {
uint64_t fullVa = (fIsKernel ? ~vaMask : 0) | nextVa; uint64_t fullVa = (fIsKernel ? ~vaMask : 0) | nextVa;
asm("dsb ishst");
asm("tlbi vaae1is, %0" :: "r" ((fullVa >> 12) & kTLBIMask)); // Use this rather than FlushVAIfAccessed so that we don't have to
// Does it correctly flush block entries at level < 3? We don't use them anyway though. // acquire sAsidLock for every entry.
// TODO: Flush only currently used ASID (using vae1is) flush_va_if_accessed(oldPte, nextVa, fASID);
entryRemoved(level, oldPte);
} }
nextVa += entrySize; nextVa += entrySize;
} }
asm("dsb ish");
vm_page* page = vm_lookup_page(ptPa >> fPageBits); vm_page* page = vm_lookup_page(ptPa >> fPageBits);
DEBUG_PAGE_ACCESS_START(page); DEBUG_PAGE_ACCESS_START(page);
vm_page_set_state(page, PAGE_STATE_FREE); vm_page_set_state(page, PAGE_STATE_FREE);
src/system/kernel/arch/arm64/VMSAv8TranslationMap.h
+1 -2
View File
@@ -115,8 +115,7 @@ private:
static uint8_t MairIndex(uint8_t type); static uint8_t MairIndex(uint8_t type);
bool ValidateVa(addr_t va); bool ValidateVa(addr_t va);
uint64_t* TableFromPa(phys_addr_t pa); uint64_t* TableFromPa(phys_addr_t pa);
template<typename EntryRemoved> void FreeTable(phys_addr_t ptPa, uint64_t va, int level);
void FreeTable(phys_addr_t ptPa, uint64_t va, int level, EntryRemoved &&entryRemoved);
phys_addr_t GetOrMakeTable(phys_addr_t ptPa, int level, int index, vm_page_reservation* reservation); phys_addr_t GetOrMakeTable(phys_addr_t ptPa, int level, int index, vm_page_reservation* reservation);
template<typename UpdatePte> template<typename UpdatePte>
void ProcessRange(phys_addr_t ptPa, int level, addr_t va, size_t size, void ProcessRange(phys_addr_t ptPa, int level, addr_t va, size_t size,