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mmu/riscv64: implement global page mapping support

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ASID allocation is not supported yet, so always use ASID 0 for user pages for now.

Change-Id: I021e77dae692c22984bc625dd0588362bece45b7
Reviewed-on: https://review.haiku-os.org/c/haiku/+/6698
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: Adrien Destugues <[email protected]>
Reviewed-by: Alex von Gluck IV <[email protected]>
This commit is contained in:
X512
2023-07-11 17:34:31 +00:00
committed by Alex von Gluck IV
parent ed3d3b1023
commit 1d9ad3fad7
13 changed files with 81 additions and 79 deletions
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headers/private/kernel/arch/riscv64/arch_thread_types.h
+1 -3
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@@ -17,9 +17,8 @@ struct iframe {
uint64 status;
uint64 cause;
uint64 tval;
uint64 align1; // structure need to be 16 byte aligned
uint64 ra;
uint64 ra __attribute__((aligned (16)));
uint64 t6;
uint64 sp;
uint64 gp;
@@ -58,7 +57,6 @@ struct arch_context {
uint64 ra; // 0
uint64 s[12]; // 12
uint64 sp; // 13
uint64 satp; // 14
};
struct fpu_context {
headers/private/system/arch/riscv64/arch_cpu_defs.h
+1 -1
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@@ -256,7 +256,7 @@ static B_ALWAYS_INLINE void FlushTlbPage(uint64 x) {
static B_ALWAYS_INLINE void FlushTlbAllAsid(uint64 asid) {
asm volatile("sfence.vma x0, %0" : : "r" (asid) : "memory");}
static B_ALWAYS_INLINE void FlushTlbPageAsid(uint64 page, uint64 asid) {
asm volatile("sfence.vma %0, %0" : : "r" (page), "r" (asid) : "memory");}
asm volatile("sfence.vma %0, %1" : : "r" (page), "r" (asid) : "memory");}
// flush instruction cache
static B_ALWAYS_INLINE void FenceI() {