From 202ffc8cca9624f276611e0e89884d397729de32 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Mon, 16 Nov 2015 19:58:51 -0600 Subject: [PATCH] intel_extreme: Bump the VLV offset back a bit and fix port defines --- headers/private/graphics/intel_extreme/intel_extreme.h | 6 +++--- .../kernel/drivers/graphics/intel_extreme/intel_extreme.cpp | 3 +-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index fe13f39a16..7f1032146c 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -512,9 +512,9 @@ struct intel_free_graphics_memory { #define PCH_HDMI_PORT_C (0x1150 | REGS_SOUTH_TRANSCODER_PORT) #define PCH_HDMI_PORT_D (0x1160 | REGS_SOUTH_TRANSCODER_PORT) -#define GEN4_HDMI_PORT_B (0x1140 | REGS_NORTH_PIPE_AND_PORT) -#define GEN4_HDMI_PORT_C (0x1160 | REGS_NORTH_PIPE_AND_PORT) -#define CHV_HDMI_PORT_D (0x116C | REGS_NORTH_PIPE_AND_PORT) +#define GEN4_HDMI_PORT_B (0x1140 | REGS_SOUTH_TRANSCODER_PORT) +#define GEN4_HDMI_PORT_C (0x1160 | REGS_SOUTH_TRANSCODER_PORT) +#define CHV_HDMI_PORT_D (0x116C | REGS_SOUTH_TRANSCODER_PORT) // DP_A always @ 6xxxx, DP_B-DP_D move with PCH #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index edbad98fc7..3e630b656b 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp @@ -353,9 +353,8 @@ intel_extreme_init(intel_info &info) // Everything in the display PRM gets +0x180000 if (info.device_type.InGroup(INTEL_GROUP_VLV)) { // "I nearly got violent with the hw guys when they told me..." - blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] += VLV_DISPLAY_BASE; - blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE; blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE; + blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] += VLV_DISPLAY_BASE; } TRACE("REGS_NORTH_SHARED: 0x%X\n",