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rewrote DPMS programming (this time the 'setting' part). Now the new nv.setting 'vga_on_tv' is respected: wich means that VGA output will be turned off by default when you enable TVout on a head (still only head1 supported for TVout). You can preset it to be kept enabled via that setting, although that is considered a tweak which 'might' destroy your (old) screen (offcially non-compatible timing on VGA). It's a handy option to have for singlehead cards though. NOTE: fixed DMA acceleration fault introduced when I added the vga_on_tv option initially (it over-wrote the dma setting!). DMA acc should now be working 'normally' again. Bumped driver to version 0.59. Note: We have a confirmed working Nvidia Geforce 7800 GT PCIe (ID 0x0092). Acceleration is disabled yet on them though.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@14515 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-10-25 13:53:31 +00:00
parent 386b1412fb
commit 20603b95f3
2 changed files with 63 additions and 62 deletions
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src/add-ons/accelerants/nvidia/SetDisplayMode.c
+44 -39
View File
@@ -96,7 +96,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
/* disable TVout if supported */ /* disable TVout if supported */
if (si->ps.tvout) BT_stop_tvout(); if (si->ps.tvout) BT_stop_tvout();
/* turn off screen(s) */ /* turn off screen(s) _after_ TVout is disabled (if applicable) */
head1_dpms(false, false, false); head1_dpms(false, false, false);
if (si->ps.secondary_head) head2_dpms(false, false, false); if (si->ps.secondary_head) head2_dpms(false, false, false);
if (si->ps.tvout) BT_dpms(false); if (si->ps.tvout) BT_dpms(false);
@@ -501,6 +501,8 @@ void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags
/* Put the display into one of the Display Power Management modes. */ /* Put the display into one of the Display Power Management modes. */
status_t SET_DPMS_MODE(uint32 dpms_flags) status_t SET_DPMS_MODE(uint32 dpms_flags)
{ {
bool display, h1h, h1v, h2h, h2v;
interrupt_enable(false); interrupt_enable(false);
LOG(4,("SET_DPMS_MODE: 0x%08x\n", dpms_flags)); LOG(4,("SET_DPMS_MODE: 0x%08x\n", dpms_flags));
@@ -508,69 +510,72 @@ status_t SET_DPMS_MODE(uint32 dpms_flags)
/* note current DPMS state for our reference */ /* note current DPMS state for our reference */
si->dpms_flags = dpms_flags; si->dpms_flags = dpms_flags;
if (si->dm.flags & DUALHEAD_BITS) /*dualhead*/ /* determine signals to send to head(s) */
{ display = h1h = h1v = h2h = h2v = true;
switch(dpms_flags) switch(dpms_flags)
{ {
case B_DPMS_ON: /* H: on, V: on, display on */ case B_DPMS_ON: /* H: on, V: on, display on */
head1_dpms(true, true, true);
if (si->ps.secondary_head) head2_dpms(true, true, true);
if (si->dm.flags & TV_BITS) BT_dpms(true);
break; break;
case B_DPMS_STAND_BY: case B_DPMS_STAND_BY:
head1_dpms(false, false, true); display = h1h = h2h = false;
if (si->ps.secondary_head) head2_dpms(false, false, true);
if (si->dm.flags & TV_BITS) BT_dpms(false);
break; break;
case B_DPMS_SUSPEND: case B_DPMS_SUSPEND:
head1_dpms(false, true, false); display = h1v = h2v = false;
if (si->ps.secondary_head) head2_dpms(false, true, false);
if (si->dm.flags & TV_BITS) BT_dpms(false);
break; break;
case B_DPMS_OFF: /* H: off, V: off, display off */ case B_DPMS_OFF: /* H: off, V: off, display off */
head1_dpms(false, false, false); display = h1h = h1v = h2h = h2v = false;
if (si->ps.secondary_head) head2_dpms(false, false, false);
if (si->dm.flags & TV_BITS) BT_dpms(false);
break; break;
default: default:
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags)); LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags));
interrupt_enable(true); interrupt_enable(true);
return B_ERROR; return B_ERROR;
} }
}
else /* singlehead */ /* CRTC used for TVout needs specific DPMS programming */
//fixme: assuming tvout is on head1, while head assignment is straight!!
if (si->dm.flags & TV_BITS)
{ {
switch(dpms_flags) LOG(4,("SET_DPMS_MODE: tuning DPMS settings for TVout compatibility\n"));
if (!(si->settings.vga_on_tv))
{ {
case B_DPMS_ON: /* H: on, V: on, display on */ /* block VGA output on head displaying on TV */
head1_dpms(true, true, true); /* Note:
if (si->dm.flags & TV_BITS) BT_dpms(true); * this specific sync setting is required: Vsync is used to keep TVout
break; * synchronized to the CRTC 'vertically' (otherwise 'rolling' occurs).
case B_DPMS_STAND_BY: * This leaves Hsync only for shutting off the VGA screen. */
head1_dpms(false, false, true); h1h = false;
if (si->dm.flags & TV_BITS) BT_dpms(false); h1v = true;
break; }
case B_DPMS_SUSPEND: else
head1_dpms(false, true, false); {
if (si->dm.flags & TV_BITS) BT_dpms(false); /* when concurrent VGA is used alongside TVout on a head, DPMS is safest
break; * applied this way: Vsync is needed for stopping TVout successfully when
case B_DPMS_OFF: /* H: off, V: off, display off */ * a (new) modeswitch occurs.
head1_dpms(false, false, false); * (see routine BT_stop_tvout() in nv_brooktreetv.c) */
if (si->dm.flags & TV_BITS) BT_dpms(false); /* Note:
break; * applying 'normal' DPMS here and forcing Vsync on in the above mentioned
default: * routine seems to not always be enough: sometimes image generation will
LOG(8,("SET: Invalid DPMS settings (DH) 0x%08x\n", dpms_flags)); * not resume in that case. */
interrupt_enable(true); h1h = display;
return B_ERROR; h1v = true;
} }
} }
/* issue actual DPMS commands as far as applicable */
head1_dpms(display, h1h, h1v);
if ((si->ps.secondary_head) && (si->dm.flags & DUALHEAD_BITS))
head2_dpms(display, h2h, h2v);
if (si->dm.flags & TV_BITS)
BT_dpms(display);
interrupt_enable(true); interrupt_enable(true);
return B_OK; return B_OK;
} }
/* Report device DPMS capabilities */ /* Report device DPMS capabilities */
uint32 DPMS_CAPABILITIES(void) { uint32 DPMS_CAPABILITIES(void)
{
return (B_DPMS_ON | B_DPMS_STAND_BY | B_DPMS_SUSPEND | B_DPMS_OFF); return (B_DPMS_ON | B_DPMS_STAND_BY | B_DPMS_SUSPEND | B_DPMS_OFF);
} }
src/add-ons/accelerants/nvidia/engine/nv_brooktreetv.c
+4 -8
View File
@@ -1614,7 +1614,7 @@ static status_t BT_start_tvout(void)
/* tell GPU to use pixelclock from TVencoder instead of using internal source */ /* tell GPU to use pixelclock from TVencoder instead of using internal source */
/* (nessecary or display will 'shiver' on both TV and VGA.) */ /* (nessecary or display will 'shiver' on both TV and VGA.) */
if (si->ps.secondary_head) if (si->ps.secondary_head)
//fixme: assuming TVout is on primary head!! //fixme: assuming TVout is on crtc1!!
DACW(PLLSEL, 0x20030f00); DACW(PLLSEL, 0x20030f00);
else else
DACW(PLLSEL, 0x00030700); DACW(PLLSEL, 0x00030700);
@@ -1651,14 +1651,13 @@ status_t BT_stop_tvout(void)
/* enable access to primary head */ /* enable access to primary head */
set_crtc_owner(0); set_crtc_owner(0);
/* switch on VGA monitor HSYNC and VSYNC */
//fixme: is this needed?
CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x3f));
/* wait for one image to be generated to make sure VGA has kicked in and is /* wait for one image to be generated to make sure VGA has kicked in and is
* running OK before continuing... * running OK before continuing...
* (Kicking in will fail often if we do not wait here) */ * (Kicking in will fail often if we do not wait here) */
/* Note:
* The used CRTC's Vsync is required to be enabled here. The DPMS state
* programming in the driver makes sure this is the case. */
/* make sure we are 'in' active VGA picture */ /* make sure we are 'in' active VGA picture */
while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1); while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1);
@@ -1799,8 +1798,5 @@ if (si->ps.secondary_head && (si->ps.card_type > NV15))
/* now set GPU CRTC to slave mode */ /* now set GPU CRTC to slave mode */
BT_start_tvout(); BT_start_tvout();
//fixme: add code to disable VGA screen when TVout enabled
//(use via nv.setting preset)
return B_OK; return B_OK;
} }