From 217c0b1d48b152376e738e2d6355854f4b872fa7 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Fri, 27 May 2011 02:14:54 +0000 Subject: [PATCH] Add surface address high handling; set primary and secondary surface frame buffer offset git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41769 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../private/graphics/radeon_hd/radeon_hd.h | 5 +++++ .../accelerants/radeon_hd/accelerant.cpp | 20 +++++++++++++++++++ .../accelerants/radeon_hd/accelerant.h | 3 +++ src/add-ons/accelerants/radeon_hd/mode.cpp | 14 +++++++++++-- 4 files changed, 40 insertions(+), 2 deletions(-) diff --git a/headers/private/graphics/radeon_hd/radeon_hd.h b/headers/private/graphics/radeon_hd/radeon_hd.h index d511b8b229..cdfbe6943d 100644 --- a/headers/private/graphics/radeon_hd/radeon_hd.h +++ b/headers/private/graphics/radeon_hd/radeon_hd.h @@ -149,6 +149,11 @@ struct radeon_free_graphics_memory { #define R6XX_CONFIG_APER_SIZE 0x5430 // r600> #define OLD_CONFIG_APER_SIZE 0x0108 // grphSwapControl = offset + EVERGREEN_GRPH_SWAP_CONTROL; gRegister->grphPrimarySurfaceAddr = offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS; + gRegister->grphSecondarySurfaceAddr + = offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS; + + gRegister->grphPrimarySurfaceAddrHigh + = offset + EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + gRegister->grphSecondarySurfaceAddrHigh + = offset + EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; + gRegister->grphPitch = offset + EVERGREEN_GRPH_PITCH; gRegister->grphSurfaceOffsetX = offset + EVERGREEN_GRPH_SURFACE_OFFSET_X; @@ -219,6 +227,18 @@ init_registers(uint8 crtid) gRegister->grphPrimarySurfaceAddr = (crtid == 1) ? D2GRPH_PRIMARY_SURFACE_ADDRESS : D1GRPH_PRIMARY_SURFACE_ADDRESS; + gRegister->grphSecondarySurfaceAddr + = (crtid == 1) ? D2GRPH_SECONDARY_SURFACE_ADDRESS + : D1GRPH_SECONDARY_SURFACE_ADDRESS; + + // Surface Address high only used on r770+ + gRegister->grphPrimarySurfaceAddrHigh + = (crtid == 1) ? R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + : R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; + gRegister->grphSecondarySurfaceAddrHigh + = (crtid == 1) ? R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + : R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; + gRegister->grphPitch = (crtid == 1) ? D2GRPH_PITCH : D1GRPH_PITCH; gRegister->grphSurfaceOffsetX diff --git a/src/add-ons/accelerants/radeon_hd/accelerant.h b/src/add-ons/accelerants/radeon_hd/accelerant.h index a0f5431914..ac97ed8207 100644 --- a/src/add-ons/accelerants/radeon_hd/accelerant.h +++ b/src/add-ons/accelerants/radeon_hd/accelerant.h @@ -43,6 +43,9 @@ struct register_info { uint16_t grphControl; uint16_t grphSwapControl; uint16_t grphPrimarySurfaceAddr; + uint16_t grphPrimarySurfaceAddrHigh; + uint16_t grphSecondarySurfaceAddr; + uint16_t grphSecondarySurfaceAddrHigh; uint16_t grphPitch; uint16_t grphSurfaceOffsetX; uint16_t grphSurfaceOffsetY; diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp b/src/add-ons/accelerants/radeon_hd/mode.cpp index 84ada0b512..80dd8a8c46 100644 --- a/src/add-ons/accelerants/radeon_hd/mode.cpp +++ b/src/add-ons/accelerants/radeon_hd/mode.cpp @@ -186,10 +186,20 @@ CardFBSet(display_mode *mode) // framebuffersize = w * h * bpp = fb bits / 8 = bytes needed - uint32 fbAddress = gInfo->shared_info->frame_buffer_phys; + uint64_t fbAddress = gInfo->shared_info->frame_buffer_phys ; + + // Tell GPU which frame buffer address to draw from + if (gInfo->shared_info->device_chipset >= (RADEON_R700 & 0x70)) { + write32(gRegister->grphPrimarySurfaceAddrHigh, + (fbAddress >> 32) & 0xf); + write32(gRegister->grphSecondarySurfaceAddrHigh, + (fbAddress >> 32) & 0xf); + } write32(gRegister->grphPrimarySurfaceAddr, - fbAddress); + fbAddress & 0xffffffff); + write32(gRegister->grphSecondarySurfaceAddr, + fbAddress & 0xffffffff); write32(gRegister->grphPitch, bytesPerRow / 4); write32(gRegister->grphSurfaceOffsetX, 0);