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intel_extreme: some minor fixes

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- Cleanup HEAD_MODE constants. These should be completely removed, now
  that we have a proper notion of pipes and displays. But the DPMS code
  still uses them, for now.
- Fix the ie_pipe command where width and height were swapped and
  missing a +1 to show the actual videomode values
This commit is contained in:
Adrien Destugues
2020-03-13 15:42:03 +01:00
parent 2e99f0e1fe
commit 22ec64553f
7 changed files with 67 additions and 54 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+9 -8
View File
@@ -521,8 +521,10 @@ struct intel_free_graphics_memory {
#define DISPLAY_PLL_POST1_DIVIDE_2 (1UL << 21)
#define DISPLAY_PLL_POST1_DIVISOR_MASK 0x001f0000
#define DISPLAY_PLL_9xx_POST1_DIVISOR_MASK 0x00ff0000
#define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_MASK 0x000000ff
#define DISPLAY_PLL_IGD_POST1_DIVISOR_MASK 0x00ff8000
#define DISPLAY_PLL_POST1_DIVISOR_SHIFT 16
#define DISPLAY_PLL_SNB_FP0_POST1_DIVISOR_SHIFT 0
#define DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT 15
#define DISPLAY_PLL_DIVISOR_1 (1UL << 8)
#define DISPLAY_PLL_N_DIVISOR_MASK 0x001f0000
@@ -647,8 +649,7 @@ struct intel_free_graphics_memory {
// planes
#define INTEL_PIPE_ENABLED (1UL << 31)
#define INTEL_PIPE_CONTROL 0x0008
#define INTEL_PIPE_STATUS 0x0024
#define INTEL_PIPE_STATE (1UL << 30)
#define INTEL_PLANE_OFFSET 0x1000
@@ -719,12 +720,6 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED)
#define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED)
// PLL registers
#define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
#define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
#define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED)
// Ironlake PCH reference clk control
#define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)
#define DREF_CONTROL_MASK 0x7fc3
@@ -749,9 +744,13 @@ struct intel_free_graphics_memory {
#define DREF_SSC4_DISABLE (0 << 0)
#define DREF_SSC4_ENABLE (1 << 0)
// PLL registers
// Multiplier Divisor
#define INTEL_DISPLAY_A_PLL (0x6014 | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)
#define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
#define CHV_DISPLAY_B_PLL_MD (0x603C | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_A_PLL_DIVISOR_0 (0x6040 | REGS_SOUTH_SHARED)
@@ -759,6 +758,8 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_B_PLL_DIVISOR_0 (0x6048 | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL_DIVISOR_1 (0x604c | REGS_SOUTH_SHARED)
#define SNB_DPLL_SEL (0x7000 | REGS_SOUTH_SHARED)
// i2c
#define INTEL_I2C_IO_A (0x5010 | REGS_SOUTH_SHARED)
#define INTEL_I2C_IO_B (0x5014 | REGS_SOUTH_SHARED)