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* Changed the way the device type is tested/set. There shouldn't be any functional

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changes.
* Minor cleanup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@32353 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2009-08-14 13:02:52 +00:00
parent 3f6f17cf36
commit 2384335649
9 changed files with 189 additions and 116 deletions
Download Patch File Download Diff File Expand all files Collapse all files
headers/private/graphics/intel_extreme/intel_extreme.h
+60 -19
View File
@@ -1,5 +1,5 @@
/* /*
* Copyright 2006-2008, Haiku, Inc. All Rights Reserved. * Copyright 2006-2009, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License. * Distributed under the terms of the MIT License.
* *
* Authors: * Authors:
@@ -19,20 +19,61 @@
#define VENDOR_ID_INTEL 0x8086 #define VENDOR_ID_INTEL 0x8086
#define INTEL_TYPE_FAMILY_MASK 0xf000 #define INTEL_TYPE_FAMILY_MASK 0xf000
#define INTEL_TYPE_GROUP_MASK 0x0fff #define INTEL_TYPE_GROUP_MASK 0xfff0
#define INTEL_TYPE_MODEL_MASK 0xffff
// families
#define INTEL_TYPE_7xx 0x1000 #define INTEL_TYPE_7xx 0x1000
#define INTEL_TYPE_8xx 0x2000 #define INTEL_TYPE_8xx 0x2000
#define INTEL_TYPE_9xx 0x4000 #define INTEL_TYPE_9xx 0x4000
#define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0001) // groups
#define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0002) #define INTEL_TYPE_83x (INTEL_TYPE_8xx | 0x0010)
#define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0010) #define INTEL_TYPE_85x (INTEL_TYPE_8xx | 0x0020)
#define INTEL_TYPE_945 (INTEL_TYPE_9xx | 0x0020) #define INTEL_TYPE_91x (INTEL_TYPE_9xx | 0x0040)
#define INTEL_TYPE_965 (INTEL_TYPE_9xx | 0x0030) #define INTEL_TYPE_94x (INTEL_TYPE_9xx | 0x0080)
#define INTEL_TYPE_G33 (INTEL_TYPE_9xx | 0x0040) #define INTEL_TYPE_96x (INTEL_TYPE_9xx | 0x0100)
#define INTEL_TYPE_Gxx (INTEL_TYPE_9xx | 0x0200)
// models
#define INTEL_TYPE_MOBILE 0x0008
#define INTEL_TYPE_915 (INTEL_TYPE_91x)
#define INTEL_TYPE_945 (INTEL_TYPE_94x)
#define INTEL_TYPE_945M (INTEL_TYPE_94x | INTEL_TYPE_MOBILE)
#define INTEL_TYPE_965 (INTEL_TYPE_96x)
#define INTEL_TYPE_965M (INTEL_TYPE_96x | INTEL_TYPE_MOBILE)
#define INTEL_TYPE_G33 (INTEL_TYPE_Gxx)
#define DEVICE_NAME "intel_extreme" #define DEVICE_NAME "intel_extreme"
#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant" #define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
struct DeviceType {
uint32 type;
DeviceType(int t)
{
type = t;
}
DeviceType& operator=(int t)
{
type = t;
return *this;
}
bool InFamily(uint32 family) const
{
return (type & INTEL_TYPE_FAMILY_MASK) == family;
}
bool InGroup(uint32 group) const
{
return (type & INTEL_TYPE_GROUP_MASK) == group;
}
bool IsModel(uint32 model) const
{
return (type & INTEL_TYPE_MODEL_MASK) == model;
}
};
// info about PLL on graphics card // info about PLL on graphics card
struct pll_info { struct pll_info {
uint32 reference_frequency; uint32 reference_frequency;
@@ -48,7 +89,7 @@ struct ring_buffer {
uint32 size; uint32 size;
uint32 position; uint32 position;
uint32 space_left; uint32 space_left;
uint8 *base; uint8* base;
}; };
struct overlay_registers; struct overlay_registers;
@@ -63,9 +104,9 @@ struct intel_shared_info {
uint32 dpms_mode; uint32 dpms_mode;
area_id registers_area; // area of memory mapped registers area_id registers_area; // area of memory mapped registers
uint8 *status_page; uint8* status_page;
addr_t physical_status_page; addr_t physical_status_page;
uint8 *graphics_memory; uint8* graphics_memory;
addr_t physical_graphics_memory; addr_t physical_graphics_memory;
uint32 graphics_memory_size; uint32 graphics_memory_size;
@@ -86,7 +127,7 @@ struct intel_shared_info {
bool hardware_cursor_enabled; bool hardware_cursor_enabled;
sem_id vblank_sem; sem_id vblank_sem;
uint8 *cursor_memory; uint8* cursor_memory;
addr_t physical_cursor_memory; addr_t physical_cursor_memory;
uint32 cursor_buffer_offset; uint32 cursor_buffer_offset;
uint32 cursor_format; uint32 cursor_format;
@@ -94,7 +135,7 @@ struct intel_shared_info {
uint16 cursor_hot_x; uint16 cursor_hot_x;
uint16 cursor_hot_y; uint16 cursor_hot_y;
uint32 device_type; DeviceType device_type;
char device_identifier[32]; char device_identifier[32];
struct pll_info pll_info; struct pll_info pll_info;
}; };
@@ -220,7 +261,7 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_C_DIGITAL 0x61160 #define INTEL_DISPLAY_C_DIGITAL 0x61160
#define INTEL_DISPLAY_LVDS_PORT 0x61180 #define INTEL_DISPLAY_LVDS_PORT 0x61180
#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors #define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
#define LVDS_POST2_RATE_FAST 7 #define LVDS_POST2_RATE_FAST 7
#define LVDS_CLKB_POWER_MASK (3 << 4) #define LVDS_CLKB_POWER_MASK (3 << 4)
#define LVDS_CLKB_POWER_UP (3 << 4) #define LVDS_CLKB_POWER_UP (3 << 4)
#define LVDS_PORT_EN (1 << 31) #define LVDS_PORT_EN (1 << 31)
@@ -575,19 +616,19 @@ struct overlay_registers {
inline bool inline bool
intel_uses_physical_overlay(intel_shared_info &info) intel_uses_physical_overlay(intel_shared_info &info)
{ {
return info.device_type != INTEL_TYPE_G33; return !info.device_type.InGroup(INTEL_TYPE_Gxx);
} }
struct hardware_status { struct hardware_status {
uint32 interrupt_status_register; uint32 interrupt_status_register;
uint32 _reserved0[3]; uint32 _reserved0[3];
void *primary_ring_head_storage; void* primary_ring_head_storage;
uint32 _reserved1[3]; uint32 _reserved1[3];
void *secondary_ring_0_head_storage; void* secondary_ring_0_head_storage;
void *secondary_ring_1_head_storage; void* secondary_ring_1_head_storage;
uint32 _reserved2[2]; uint32 _reserved2[2];
void *binning_head_storage; void* binning_head_storage;
uint32 _reserved3[3]; uint32 _reserved3[3];
uint32 store[1008]; uint32 store[1008];
}; };
src/add-ons/accelerants/intel_extreme/Jamfile
+1 -1
View File
@@ -15,7 +15,7 @@ Addon intel_extreme.accelerant :
memory.cpp memory.cpp
mode.cpp mode.cpp
overlay.cpp overlay.cpp
#overlay_3d_i965.cpp overlay_3d_i965.cpp
: be libaccelerantscommon.a : be libaccelerantscommon.a
; ;
src/add-ons/accelerants/intel_extreme/accelerant.cpp
+25 -21
View File
@@ -1,5 +1,5 @@
/* /*
* Copyright 2006-2008, Haiku, Inc. All Rights Reserved. * Copyright 2006-2009, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License. * Distributed under the terms of the MIT License.
* *
* Authors: * Authors:
@@ -34,17 +34,19 @@ struct accelerant_info *gInfo;
class AreaCloner { class AreaCloner {
public: public:
AreaCloner(); AreaCloner();
~AreaCloner(); ~AreaCloner();
area_id Clone(const char *name, void **_address, uint32 spec, area_id Clone(const char *name, void **_address,
uint32 protection, area_id sourceArea); uint32 spec, uint32 protection,
status_t InitCheck() { return fArea < B_OK ? (status_t)fArea : B_OK; } area_id sourceArea);
void Keep(); status_t InitCheck()
{ return fArea < 0 ? (status_t)fArea : B_OK; }
void Keep();
private: private:
area_id fArea; area_id fArea;
}; };
@@ -57,12 +59,12 @@ AreaCloner::AreaCloner()
AreaCloner::~AreaCloner() AreaCloner::~AreaCloner()
{ {
if (fArea >= B_OK) if (fArea >= 0)
delete_area(fArea); delete_area(fArea);
} }
area_id area_id
AreaCloner::Clone(const char *name, void **_address, uint32 spec, AreaCloner::Clone(const char *name, void **_address, uint32 spec,
uint32 protection, area_id sourceArea) uint32 protection, area_id sourceArea)
{ {
@@ -71,7 +73,7 @@ AreaCloner::Clone(const char *name, void **_address, uint32 spec,
} }
void void
AreaCloner::Keep() AreaCloner::Keep()
{ {
fArea = -1; fArea = -1;
@@ -139,7 +141,7 @@ init_common(int device, bool isClone)
(gInfo->shared_info->graphics_memory (gInfo->shared_info->graphics_memory
+ gInfo->shared_info->overlay_offset); + gInfo->shared_info->overlay_offset);
if (gInfo->shared_info->device_type == INTEL_TYPE_965) { if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) {
// allocate some extra memory for the 3D context // allocate some extra memory for the 3D context
if (intel_allocate_memory(INTEL_i965_3D_CONTEXT_SIZE, if (intel_allocate_memory(INTEL_i965_3D_CONTEXT_SIZE,
B_APERTURE_NON_RESERVED, gInfo->context_base) == B_OK) { B_APERTURE_NON_RESERVED, gInfo->context_base) == B_OK) {
@@ -181,7 +183,7 @@ intel_init_accelerant(int device)
TRACE(("intel_init_accelerant()\n")); TRACE(("intel_init_accelerant()\n"));
status_t status = init_common(device, false); status_t status = init_common(device, false);
if (status != B_OK) if (status != B_OK)
return status; return status;
intel_shared_info &info = *gInfo->shared_info; intel_shared_info &info = *gInfo->shared_info;
@@ -203,8 +205,10 @@ intel_init_accelerant(int device)
uint32 lvds = read32(INTEL_DISPLAY_LVDS_PORT); uint32 lvds = read32(INTEL_DISPLAY_LVDS_PORT);
// If we have an enabled display pipe we save the passed information and assume it is the valid panel size.. // If we have an enabled display pipe we save the passed information and
// Later we query for proper EDID info if it exists, or figure something else out. (Default modes, etc.) // assume it is the valid panel size..
// Later we query for proper EDID info if it exists, or figure something
// else out. (Default modes, etc.)
if ((lvds & DISPLAY_PIPE_ENABLED) != 0) { if ((lvds & DISPLAY_PIPE_ENABLED) != 0) {
save_lvds_mode(); save_lvds_mode();
gInfo->head_mode |= HEAD_MODE_LVDS_PANEL; gInfo->head_mode |= HEAD_MODE_LVDS_PANEL;
@@ -212,7 +216,8 @@ intel_init_accelerant(int device)
TRACE(("head detected: %d\n", gInfo->head_mode)); TRACE(("head detected: %d\n", gInfo->head_mode));
TRACE(("adpa: %08lx, dova: %08lx, dovb: %08lx, lvds: %08lx\n", TRACE(("adpa: %08lx, dova: %08lx, dovb: %08lx, lvds: %08lx\n",
read32(INTEL_DISPLAY_A_ANALOG_PORT), read32(INTEL_DISPLAY_A_DIGITAL_PORT), read32(INTEL_DISPLAY_A_ANALOG_PORT),
read32(INTEL_DISPLAY_A_DIGITAL_PORT),
read32(INTEL_DISPLAY_B_DIGITAL_PORT), read32(INTEL_DISPLAY_LVDS_PORT))); read32(INTEL_DISPLAY_B_DIGITAL_PORT), read32(INTEL_DISPLAY_LVDS_PORT)));
status = create_mode_list(); status = create_mode_list();
@@ -268,7 +273,7 @@ intel_clone_accelerant(void *info)
status = gInfo->mode_list_area = clone_area( status = gInfo->mode_list_area = clone_area(
"intel extreme cloned modes", (void **)&gInfo->mode_list, "intel extreme cloned modes", (void **)&gInfo->mode_list,
B_ANY_ADDRESS, B_READ_AREA, gInfo->shared_info->mode_list_area); B_ANY_ADDRESS, B_READ_AREA, gInfo->shared_info->mode_list_area);
if (status < B_OK) if (status < B_OK)
goto err2; goto err2;
return B_OK; return B_OK;
@@ -310,8 +315,7 @@ intel_get_accelerant_device_info(accelerant_device_info *info)
TRACE(("intel_get_accelerant_device_info()\n")); TRACE(("intel_get_accelerant_device_info()\n"));
info->version = B_ACCELERANT_VERSION; info->version = B_ACCELERANT_VERSION;
strcpy(info->name, strcpy(info->name, gInfo->shared_info->device_type.InFamily(INTEL_TYPE_7xx)
(gInfo->shared_info->device_type & INTEL_TYPE_7xx) != 0
? "Intel Extreme Graphics 1" : "Intel Extreme Graphics 2"); ? "Intel Extreme Graphics 1" : "Intel Extreme Graphics 2");
strcpy(info->chipset, gInfo->shared_info->device_identifier); strcpy(info->chipset, gInfo->shared_info->device_identifier);
strcpy(info->serial_no, "None"); strcpy(info->serial_no, "None");
src/add-ons/accelerants/intel_extreme/accelerant_protos.h
+2
View File
@@ -82,6 +82,8 @@ overlay_token intel_allocate_overlay(void);
status_t intel_release_overlay(overlay_token overlayToken); status_t intel_release_overlay(overlay_token overlayToken);
status_t intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer, status_t intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer,
const overlay_window *window, const overlay_view *view); const overlay_window *window, const overlay_view *view);
status_t i965_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer,
const overlay_window *window, const overlay_view *view);
#ifdef __cplusplus #ifdef __cplusplus
} }
src/add-ons/accelerants/intel_extreme/mode.cpp
+28 -19
View File
@@ -88,7 +88,7 @@ set_i2c_signals(void* cookie, int clock, int data)
uint32 ioRegister = (uint32)cookie; uint32 ioRegister = (uint32)cookie;
uint32 value; uint32 value;
if (gInfo->shared_info->device_type == INTEL_TYPE_83x) { if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_83x)) {
// on these chips, the reserved values are fixed // on these chips, the reserved values are fixed
value = 0; value = 0;
} else { } else {
@@ -130,7 +130,7 @@ set_frame_buffer_base()
surfaceRegister = INTEL_DISPLAY_B_SURFACE; surfaceRegister = INTEL_DISPLAY_B_SURFACE;
} }
if (sharedInfo.device_type == INTEL_TYPE_965) { if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x)) {
write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row write32(baseRegister, mode.v_display_start * sharedInfo.bytes_per_row
+ mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8); + mode.h_display_start * (sharedInfo.bits_per_pixel + 7) / 8);
read32(baseRegister); read32(baseRegister);
@@ -217,7 +217,7 @@ get_pll_limits(pll_limits &limits)
// Note, the limits are taken from the X driver; they have not yet been // Note, the limits are taken from the X driver; they have not yet been
// tested // tested
if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
// TODO: support LVDS output limits as well // TODO: support LVDS output limits as well
// (Update: Output limits are adjusted in the computation (post2=7/14)) // (Update: Output limits are adjusted in the computation (post2=7/14))
// Should move them here! // Should move them here!
@@ -356,7 +356,7 @@ save_lvds_mode(void)
pll_limits limits; pll_limits limits;
get_pll_limits(limits); get_pll_limits(limits);
if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK) divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
>> DISPLAY_PLL_POST1_DIVISOR_SHIFT; >> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
@@ -596,7 +596,7 @@ if (first) {
write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED); write32(INTEL_VGA_DISPLAY_CONTROL, VGA_DISPLAY_DISABLED);
read32(INTEL_VGA_DISPLAY_CONTROL); read32(INTEL_VGA_DISPLAY_CONTROL);
if (gInfo->shared_info->device_type != INTEL_TYPE_85x) { if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_85x)) {
} }
if ((gInfo->head_mode & HEAD_MODE_B_DIGITAL) != 0) { if ((gInfo->head_mode & HEAD_MODE_B_DIGITAL) != 0) {
@@ -604,7 +604,7 @@ if (first) {
compute_pll_divisors(target, divisors, true); compute_pll_divisors(target, divisors, true);
uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL; uint32 dpll = DISPLAY_PLL_NO_VGA_CONTROL;
if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
dpll |= LVDS_PLL_MODE_LVDS; dpll |= LVDS_PLL_MODE_LVDS;
// DPLL mode LVDS for i915+ // DPLL mode LVDS for i915+
} }
@@ -632,9 +632,12 @@ if (first) {
if ((dpll & DISPLAY_PLL_ENABLED) != 0) { if ((dpll & DISPLAY_PLL_ENABLED) != 0) {
write32(INTEL_DISPLAY_B_PLL_DIVISOR_0, write32(INTEL_DISPLAY_B_PLL_DIVISOR_0,
(((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK) (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)
| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) & DISPLAY_PLL_M1_DIVISOR_MASK) & DISPLAY_PLL_N_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK)); | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT)
& DISPLAY_PLL_M1_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
& DISPLAY_PLL_M2_DIVISOR_MASK));
write32(INTEL_DISPLAY_B_PLL, dpll & ~DISPLAY_PLL_ENABLED); write32(INTEL_DISPLAY_B_PLL, dpll & ~DISPLAY_PLL_ENABLED);
read32(INTEL_DISPLAY_B_PLL); read32(INTEL_DISPLAY_B_PLL);
spin(150); spin(150);
@@ -657,9 +660,12 @@ if (first) {
read32(INTEL_DISPLAY_LVDS_PORT); read32(INTEL_DISPLAY_LVDS_PORT);
write32(INTEL_DISPLAY_B_PLL_DIVISOR_0, write32(INTEL_DISPLAY_B_PLL_DIVISOR_0,
(((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT) & DISPLAY_PLL_N_DIVISOR_MASK) (((divisors.n - 2) << DISPLAY_PLL_N_DIVISOR_SHIFT)
| (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT) & DISPLAY_PLL_M1_DIVISOR_MASK) & DISPLAY_PLL_N_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK)); | (((divisors.m1 - 2) << DISPLAY_PLL_M1_DIVISOR_SHIFT)
& DISPLAY_PLL_M1_DIVISOR_MASK)
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT)
& DISPLAY_PLL_M2_DIVISOR_MASK));
write32(INTEL_DISPLAY_B_PLL, dpll); write32(INTEL_DISPLAY_B_PLL, dpll);
read32(INTEL_DISPLAY_B_PLL); read32(INTEL_DISPLAY_B_PLL);
@@ -667,7 +673,7 @@ if (first) {
// Wait for the clocks to stabilize // Wait for the clocks to stabilize
spin(150); spin(150);
if (gInfo->shared_info->device_type == INTEL_TYPE_965) { if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x)) {
float adjusted = ((referenceClock * divisors.m) / divisors.n) float adjusted = ((referenceClock * divisors.m) / divisors.n)
/ divisors.post; / divisors.post;
uint32 pixelMultiply = uint32(adjusted uint32 pixelMultiply = uint32(adjusted
@@ -718,8 +724,9 @@ if (first) {
| (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK)); | (((divisors.m2 - 2) << DISPLAY_PLL_M2_DIVISOR_SHIFT) & DISPLAY_PLL_M2_DIVISOR_MASK));
uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL; uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL;
if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
pll |= ((1 << (divisors.post1 - 1)) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) pll |= ((1 << (divisors.post1 - 1))
<< DISPLAY_PLL_POST1_DIVISOR_SHIFT)
& DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
// pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) // pll |= ((divisors.post1 - 1) << DISPLAY_PLL_POST1_DIVISOR_SHIFT)
// & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK; // & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK;
@@ -728,7 +735,7 @@ if (first) {
pll |= DISPLAY_PLL_MODE_ANALOG; pll |= DISPLAY_PLL_MODE_ANALOG;
if (gInfo->shared_info->device_type == INTEL_TYPE_965) if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_96x))
pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT; pll |= 6 << DISPLAY_PLL_PULSE_PHASE_SHIFT;
} else { } else {
if (!divisors.post2_high) if (!divisors.post2_high)
@@ -834,7 +841,7 @@ intel_get_display_mode(display_mode *_currentMode)
pll_limits limits; pll_limits limits;
get_pll_limits(limits); get_pll_limits(limits);
if ((gInfo->shared_info->device_type & INTEL_TYPE_9xx) != 0) { if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_9xx)) {
divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK) divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK)
>> DISPLAY_PLL_POST1_DIVISOR_SHIFT; >> DISPLAY_PLL_POST1_DIVISOR_SHIFT;
@@ -856,8 +863,10 @@ intel_get_display_mode(display_mode *_currentMode)
divisors.m = 5 * divisors.m1 + divisors.m2; divisors.m = 5 * divisors.m1 + divisors.m2;
divisors.post = divisors.post1 * divisors.post2; divisors.post = divisors.post1 * divisors.post2;
float referenceClock = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; float referenceClock
float pixelClock = ((referenceClock * divisors.m) / divisors.n) / divisors.post; = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
float pixelClock
= ((referenceClock * divisors.m) / divisors.n) / divisors.post;
// timing // timing
src/add-ons/accelerants/intel_extreme/overlay.cpp
+50 -35
View File
@@ -227,7 +227,7 @@ static void
update_overlay(bool updateCoefficients) update_overlay(bool updateCoefficients)
{ {
if (!gInfo->shared_info->overlay_active if (!gInfo->shared_info->overlay_active
|| gInfo->shared_info->device_type == INTEL_TYPE_965) || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
return; return;
QueueCommands queue(gInfo->shared_info->primary_ring_buffer); QueueCommands queue(gInfo->shared_info->primary_ring_buffer);
@@ -249,7 +249,7 @@ static void
show_overlay(void) show_overlay(void)
{ {
if (gInfo->shared_info->overlay_active if (gInfo->shared_info->overlay_active
|| gInfo->shared_info->device_type == INTEL_TYPE_965) || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
return; return;
gInfo->shared_info->overlay_active = true; gInfo->shared_info->overlay_active = true;
@@ -269,7 +269,7 @@ static void
hide_overlay(void) hide_overlay(void)
{ {
if (!gInfo->shared_info->overlay_active if (!gInfo->shared_info->overlay_active
|| gInfo->shared_info->device_type == INTEL_TYPE_965) || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
return; return;
overlay_registers *registers = gInfo->overlay_registers; overlay_registers *registers = gInfo->overlay_registers;
@@ -315,7 +315,7 @@ intel_overlay_supported_spaces(const display_mode *mode)
static const uint32 kSupportedi965Spaces[] = {B_YCbCr422, 0}; static const uint32 kSupportedi965Spaces[] = {B_YCbCr422, 0};
intel_shared_info &sharedInfo = *gInfo->shared_info; intel_shared_info &sharedInfo = *gInfo->shared_info;
if (sharedInfo.device_type == INTEL_TYPE_965) if (sharedInfo.device_type.InGroup(INTEL_TYPE_96x))
return kSupportedi965Spaces; return kSupportedi965Spaces;
return kSupportedSpaces; return kSupportedSpaces;
@@ -368,7 +368,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
// alloc graphics mem // alloc graphics mem
int32 alignment = 0x3f; int32 alignment = 0x3f;
if (sharedInfo.device_type == INTEL_TYPE_965) if (sharedInfo.device_type.InGroup(INTEL_TYPE_965))
alignment = 0xff; alignment = 0xff;
overlay_buffer *buffer = &overlay->buffer; overlay_buffer *buffer = &overlay->buffer;
@@ -384,7 +384,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width,
return NULL; return NULL;
} }
if (sharedInfo.device_type == INTEL_TYPE_965) { if (sharedInfo.device_type.InGroup(INTEL_TYPE_965)) {
status = intel_allocate_memory(INTEL_i965_OVERLAY_STATE_SIZE, status = intel_allocate_memory(INTEL_i965_OVERLAY_STATE_SIZE,
B_APERTURE_NON_RESERVED, overlay->state_base); B_APERTURE_NON_RESERVED, overlay->state_base);
if (status < B_OK) { if (status < B_OK) {
@@ -425,7 +425,7 @@ intel_release_overlay_buffer(const overlay_buffer *buffer)
hide_overlay(); hide_overlay();
intel_free_memory(overlay->buffer_base); intel_free_memory(overlay->buffer_base);
if (gInfo->shared_info->device_type == INTEL_TYPE_965) if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965))
intel_free_memory(overlay->state_base); intel_free_memory(overlay->state_base);
free(overlay); free(overlay);
@@ -600,33 +600,42 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
// we need to offset the overlay view to adapt it to the clipping // we need to offset the overlay view to adapt it to the clipping
// (in addition to whatever offset is desired already) // (in addition to whatever offset is desired already)
left = view->h_start - (int32)((window->h_start - left) * (horizontalScale / 4096.0) + 0.5); left = view->h_start - (int32)((window->h_start - left)
top = view->v_start - (int32)((window->v_start - top) * (verticalScale / 4096.0) + 0.5); * (horizontalScale / 4096.0) + 0.5);
top = view->v_start - (int32)((window->v_start - top)
* (verticalScale / 4096.0) + 0.5);
right = view->h_start + view->width; right = view->h_start + view->width;
bottom = view->v_start + view->height; bottom = view->v_start + view->height;
gInfo->overlay_position_buffer_offset = buffer->bytes_per_row * top gInfo->overlay_position_buffer_offset = buffer->bytes_per_row * top
+ left * bytesPerPixel; + left * bytesPerPixel;
// Note: in non-planar mode, you *must* not program the source width/height // Note: in non-planar mode, you *must* not program the source
// UV registers - they must stay cleared, or the chip is doing strange stuff. // width/height UV registers - they must stay cleared, or the chip is
// On the other hand, you have to program the UV scaling registers, or the // doing strange stuff.
// result will be wrong, too. // On the other hand, you have to program the UV scaling registers, or
// the result will be wrong, too.
registers->source_width_rgb = right - left; registers->source_width_rgb = right - left;
registers->source_height_rgb = bottom - top; registers->source_height_rgb = bottom - top;
if ((gInfo->shared_info->device_type & INTEL_TYPE_8xx) != 0) { if (gInfo->shared_info->device_type.InFamily(INTEL_TYPE_8xx)) {
registers->source_bytes_per_row_rgb = (((overlay->buffer_offset + (view->width << 1) registers->source_bytes_per_row_rgb = (((overlay->buffer_offset
+ 0x1f) >> 5) - (overlay->buffer_offset >> 5) - 1) << 2; + (view->width << 1) + 0x1f) >> 5)
- (overlay->buffer_offset >> 5) - 1) << 2;
} else { } else {
registers->source_bytes_per_row_rgb = ((((overlay->buffer_offset + (view->width << 1) registers->source_bytes_per_row_rgb = ((((overlay->buffer_offset
+ 0x3f) >> 6) - (overlay->buffer_offset >> 6) << 1) - 1) << 2; + (view->width << 1) + 0x3f) >> 6)
- (overlay->buffer_offset >> 6) << 1) - 1) << 2;
} }
// horizontal scaling // horizontal scaling
registers->scale_rgb.horizontal_downscale_factor = horizontalScale >> 12; registers->scale_rgb.horizontal_downscale_factor
registers->scale_rgb.horizontal_scale_fraction = horizontalScale & 0xfff; = horizontalScale >> 12;
registers->scale_uv.horizontal_downscale_factor = horizontalScaleUV >> 12; registers->scale_rgb.horizontal_scale_fraction
registers->scale_uv.horizontal_scale_fraction = horizontalScaleUV & 0xfff; = horizontalScale & 0xfff;
registers->scale_uv.horizontal_downscale_factor
= horizontalScaleUV >> 12;
registers->scale_uv.horizontal_scale_fraction
= horizontalScaleUV & 0xfff;
// vertical scaling // vertical scaling
registers->scale_rgb.vertical_scale_fraction = verticalScale & 0xfff; registers->scale_rgb.vertical_scale_fraction = verticalScale & 0xfff;
@@ -635,7 +644,8 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
registers->vertical_scale_uv = verticalScaleUV >> 12; registers->vertical_scale_uv = verticalScaleUV >> 12;
TRACE(("scale: h = %ld.%ld, v = %ld.%ld\n", horizontalScale >> 12, TRACE(("scale: h = %ld.%ld, v = %ld.%ld\n", horizontalScale >> 12,
horizontalScale & 0xfff, verticalScale >> 12, verticalScale & 0xfff)); horizontalScale & 0xfff, verticalScale >> 12,
verticalScale & 0xfff));
if (verticalScale != gInfo->last_vertical_overlay_scale if (verticalScale != gInfo->last_vertical_overlay_scale
|| horizontalScale != gInfo->last_horizontal_overlay_scale) { || horizontalScale != gInfo->last_horizontal_overlay_scale) {
@@ -646,16 +656,18 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
update_coefficients(NUM_HORIZONTAL_TAPS, horizontalScale / 4096.0, update_coefficients(NUM_HORIZONTAL_TAPS, horizontalScale / 4096.0,
true, true, coefficients); true, true, coefficients);
phase_coefficient coefficientsUV[NUM_HORIZONTAL_UV_TAPS * NUM_PHASES]; phase_coefficient coefficientsUV[
update_coefficients(NUM_HORIZONTAL_UV_TAPS, horizontalScaleUV / 4096.0, NUM_HORIZONTAL_UV_TAPS * NUM_PHASES];
true, false, coefficientsUV); update_coefficients(NUM_HORIZONTAL_UV_TAPS,
horizontalScaleUV / 4096.0, true, false, coefficientsUV);
int32 pos = 0; int32 pos = 0;
for (int32 i = 0; i < NUM_PHASES; i++) { for (int32 i = 0; i < NUM_PHASES; i++) {
for (int32 j = 0; j < NUM_HORIZONTAL_TAPS; j++) { for (int32 j = 0; j < NUM_HORIZONTAL_TAPS; j++) {
registers->horizontal_coefficients_rgb[pos] = coefficients[pos].sign << 15 registers->horizontal_coefficients_rgb[pos]
| coefficients[pos].exponent << 12 = coefficients[pos].sign << 15
| coefficients[pos].mantissa; | coefficients[pos].exponent << 12
| coefficients[pos].mantissa;
pos++; pos++;
} }
} }
@@ -663,9 +675,10 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
pos = 0; pos = 0;
for (int32 i = 0; i < NUM_PHASES; i++) { for (int32 i = 0; i < NUM_PHASES; i++) {
for (int32 j = 0; j < NUM_HORIZONTAL_UV_TAPS; j++) { for (int32 j = 0; j < NUM_HORIZONTAL_UV_TAPS; j++) {
registers->horizontal_coefficients_uv[pos] = coefficientsUV[pos].sign << 15 registers->horizontal_coefficients_uv[pos]
| coefficientsUV[pos].exponent << 12 = coefficientsUV[pos].sign << 15
| coefficientsUV[pos].mantissa; | coefficientsUV[pos].exponent << 12
| coefficientsUV[pos].mantissa;
pos++; pos++;
} }
} }
@@ -683,11 +696,13 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer
// program buffer // program buffer
registers->buffer_rgb0 = overlay->buffer_offset + gInfo->overlay_position_buffer_offset; registers->buffer_rgb0
= overlay->buffer_offset + gInfo->overlay_position_buffer_offset;
registers->stride_rgb = buffer->bytes_per_row; registers->stride_rgb = buffer->bytes_per_row;
registers->mirroring_mode = (window->flags & B_OVERLAY_HORIZONTAL_MIRRORING) != 0 registers->mirroring_mode
? OVERLAY_MIRROR_HORIZONTAL : OVERLAY_MIRROR_NORMAL; = (window->flags & B_OVERLAY_HORIZONTAL_MIRRORING) != 0
? OVERLAY_MIRROR_HORIZONTAL : OVERLAY_MIRROR_NORMAL;
registers->ycbcr422_order = 0; registers->ycbcr422_order = 0;
if (!gInfo->shared_info->overlay_active) { if (!gInfo->shared_info->overlay_active) {
src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
+2 -2
View File
@@ -48,9 +48,9 @@ const struct supported_device {
{0x2592, INTEL_TYPE_91x, "i915GM"}, {0x2592, INTEL_TYPE_91x, "i915GM"},
{0x2772, INTEL_TYPE_945, "i945G"}, {0x2772, INTEL_TYPE_945, "i945G"},
{0x27a2, INTEL_TYPE_945, "i945GM"}, {0x27a2, INTEL_TYPE_945, "i945GM"},
{0x27ae, INTEL_TYPE_945, "i945GME"}, {0x27ae, INTEL_TYPE_945M, "i945GME"},
{0x29a2, INTEL_TYPE_965, "i965G"}, {0x29a2, INTEL_TYPE_965, "i965G"},
{0x2a02, INTEL_TYPE_965, "i965GM"}, {0x2a02, INTEL_TYPE_965M, "i965GM"},
{0x29b2, INTEL_TYPE_G33, "G33G"}, {0x29b2, INTEL_TYPE_G33, "G33G"},
{0x29c2, INTEL_TYPE_G33, "Q35G"}, {0x29c2, INTEL_TYPE_G33, "Q35G"},
{0x29d2, INTEL_TYPE_G33, "Q33G"}, {0x29d2, INTEL_TYPE_G33, "Q33G"},
src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+9 -7
View File
@@ -1,5 +1,5 @@
/* /*
* Copyright 2006-2008, Haiku, Inc. All Rights Reserved. * Copyright 2006-2009, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License. * Distributed under the terms of the MIT License.
* *
* Authors: * Authors:
@@ -193,9 +193,9 @@ intel_extreme_init(intel_info &info)
int fbIndex = 0; int fbIndex = 0;
int mmioIndex = 1; int mmioIndex = 1;
if ((info.device_type & INTEL_TYPE_9xx) != 0) { if (info.device_type.InFamily(INTEL_TYPE_9xx)) {
// for some reason Intel saw the need to change the order of the mappings // For some reason Intel saw the need to change the order of the
// with the introduction of the i9xx family // mappings with the introduction of the i9xx family
mmioIndex = 0; mmioIndex = 0;
fbIndex = 2; fbIndex = 2;
} }
@@ -263,13 +263,15 @@ intel_extreme_init(intel_info &info)
info.shared_info->frame_buffer = 0; info.shared_info->frame_buffer = 0;
info.shared_info->dpms_mode = B_DPMS_ON; info.shared_info->dpms_mode = B_DPMS_ON;
if ((info.device_type & INTEL_TYPE_9xx) != 0) { if (info.device_type.InFamily(INTEL_TYPE_9xx)) {
info.shared_info->pll_info.reference_frequency = 96000; // 96 kHz info.shared_info->pll_info.reference_frequency = 96000; // 96 kHz
info.shared_info->pll_info.max_frequency = 400000; // 400 MHz RAM DAC speed info.shared_info->pll_info.max_frequency = 400000;
// 400 MHz RAM DAC speed
info.shared_info->pll_info.min_frequency = 20000; // 20 MHz info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
} else { } else {
info.shared_info->pll_info.reference_frequency = 48000; // 48 kHz info.shared_info->pll_info.reference_frequency = 48000; // 48 kHz
info.shared_info->pll_info.max_frequency = 350000; // 350 MHz RAM DAC speed info.shared_info->pll_info.max_frequency = 350000;
// 350 MHz RAM DAC speed
info.shared_info->pll_info.min_frequency = 25000; // 25 MHz info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
} }
src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme_private.h
+12 -12
View File
@@ -21,27 +21,27 @@ struct intel_info {
int32 open_count; int32 open_count;
status_t init_status; status_t init_status;
int32 id; int32 id;
pci_info *pci; pci_info* pci;
addr_t aperture_base; addr_t aperture_base;
aperture_id aperture; aperture_id aperture;
uint8 *registers; uint8* registers;
area_id registers_area; area_id registers_area;
struct intel_shared_info *shared_info; struct intel_shared_info* shared_info;
area_id shared_area; area_id shared_area;
struct overlay_registers *overlay_registers; struct overlay_registers* overlay_registers;
bool fake_interrupts; bool fake_interrupts;
const char *device_identifier; const char* device_identifier;
uint32 device_type; DeviceType device_type;
}; };
extern status_t intel_free_memory(intel_info &info, addr_t offset); extern status_t intel_free_memory(intel_info& info, addr_t offset);
extern status_t intel_allocate_memory(intel_info &info, size_t size, extern status_t intel_allocate_memory(intel_info& info, size_t size,
size_t alignment, uint32 flags, addr_t *_offset, size_t alignment, uint32 flags, addr_t* _offset,
addr_t *_physicalBase = NULL); addr_t* _physicalBase = NULL);
extern status_t intel_extreme_init(intel_info &info); extern status_t intel_extreme_init(intel_info& info);
extern void intel_extreme_uninit(intel_info &info); extern void intel_extreme_uninit(intel_info& info);
#endif /* INTEL_EXTREME_PRIVATE_H */ #endif /* INTEL_EXTREME_PRIVATE_H */