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ARM MMU: Use MRC vs MCR for TTBR

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* Verified to use MRC vs MCR multiple locations
* Small bit of style cleanup as well
* Better comment function usage
This commit is contained in:
Alexander von Gluck IV
2012-05-18 08:57:00 -05:00
parent 7a81151b1b
commit 249e5492c1
2 changed files with 39 additions and 18 deletions
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src/system/boot/platform/raspberrypi_arm/mmu.cpp
+19 -9
View File
@@ -204,33 +204,43 @@ get_next_physical_page(size_t pagesize)
} }
/*
* Set translation table base
*/
void void
mmu_set_TTBR(uint32 ttb) mmu_set_TTBR(uint32 ttb)
{ {
ttb &= 0xffffc000; ttb &= 0xffffc000;
asm volatile("MCR p15, 0, %[adr], c2, c0, 0"::[adr] "r" (ttb)); asm volatile("MRC p15, 0, %[adr], c2, c0, 0"::[adr] "r" (ttb));
// set translation table base
} }
/*
* Flush the TLB
*/
void void
mmu_flush_TLB() mmu_flush_TLB()
{ {
uint32 bla = 0; uint32 value = 0;
asm volatile("MCR p15, 0, %[c8format], c8, c7, 0"::[c8format] "r" (bla)); asm volatile("MCR p15, 0, %[c8format], c8, c7, 0"::[c8format] "r" (value));
// flush TLB
} }
/*
* Read MMU Control Register
*/
uint32 uint32
mmu_read_C1() mmu_read_C1()
{ {
uint32 bla = 0; uint32 controlReg = 0;
asm volatile("MRC p15, 0, %[c1out], c1, c0, 0":[c1out] "=r" (bla)); asm volatile("MRC p15, 0, %[c1out], c1, c0, 0":[c1out] "=r" (controlReg));
return bla; return controlReg;
} }
/*
* Write MMU Control Register
*/
void void
mmu_write_C1(uint32 value) mmu_write_C1(uint32 value)
{ {
src/system/boot/platform/u-boot/mmu.cpp
+20 -9
View File
@@ -173,6 +173,7 @@ get_next_physical_address(size_t size)
return address; return address;
} }
static addr_t static addr_t
get_next_physical_address_alligned(size_t size, uint32 mask) get_next_physical_address_alligned(size_t size, uint32 mask)
{ {
@@ -197,33 +198,43 @@ get_next_physical_page(size_t pagesize)
} }
/*
* Set translation table base
*/
void void
mmu_set_TTBR(uint32 ttb) mmu_set_TTBR(uint32 ttb)
{ {
ttb &= 0xffffc000; ttb &= 0xffffc000;
asm volatile("MCR p15, 0, %[adr], c2, c0, 0"::[adr] "r" (ttb)); asm volatile("MRC p15, 0, %[adr], c2, c0, 0"::[adr] "r" (ttb));
// set translation table base
} }
/*
* Flush the TLB
*/
void void
mmu_flush_TLB() mmu_flush_TLB()
{ {
uint32 bla = 0; uint32 value = 0;
asm volatile("MCR p15, 0, %[c8format], c8, c7, 0"::[c8format] "r" (bla)); asm volatile("MCR p15, 0, %[c8format], c8, c7, 0"::[c8format] "r" (value));
// flush TLB
} }
/*
* Read MMU Control Register
*/
uint32 uint32
mmu_read_C1() mmu_read_C1()
{ {
uint32 bla = 0; uint32 controlReg = 0;
asm volatile("MRC p15, 0, %[c1out], c1, c0, 0":[c1out] "=r" (bla)); asm volatile("MRC p15, 0, %[c1out], c1, c0, 0":[c1out] "=r" (controlReg));
return bla; return controlReg;
} }
/*
* Write MMU Control Register
*/
void void
mmu_write_C1(uint32 value) mmu_write_C1(uint32 value)
{ {