diff --git a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
index 0ba111bc84..c05117a404 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
@@ -108,13 +108,8 @@ status_t nv_crtc_set_timing(display_mode target)
 	/* setup fixed modeline for flatpanel if connected and active */
 	if (si->ps.tmds1_active)
 	{
-		display_mode p1, p2;
-		bool pan1, pan2;
-
 		LOG(2,("CRTC: DFP active: tuning modeline\n"));
 
-		get_panel_modelines(&p1, &p2, &pan1, &pan2);
-
 		/* horizontal timing */
 		//testing (640x480): total = 135% is too much, 120% to small...
 		//total = display + 160 equals panel modeline: but must be smaller...?
@@ -123,15 +118,15 @@ status_t nv_crtc_set_timing(display_mode target)
 //		target.timing.h_sync_end = target.timing.h_total - 40;//48;//16
 		//adaptive to panel: fixme: test on 4:3 and 16:10 panels!
 		target.timing.h_sync_start =
-			((uint16)((p1.timing.h_sync_start / ((float)p1.timing.h_display)) *
+			((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) *
 			target.timing.h_display)) & 0xfff8;
 
 		target.timing.h_sync_end =
-			((uint16)((p1.timing.h_sync_end / ((float)p1.timing.h_display)) *
+			((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) *
 			target.timing.h_display)) & 0xfff8;
 
 		target.timing.h_total =
-			(((uint16)((p1.timing.h_total / ((float)p1.timing.h_display)) *
+			(((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) *
 			target.timing.h_display)) & 0xfff8) - 8;
 
 		if (target.timing.h_sync_start == target.timing.h_display)
@@ -144,15 +139,15 @@ status_t nv_crtc_set_timing(display_mode target)
 //		target.timing.v_sync_start = target.timing.v_total - 3;
 //		target.timing.v_sync_end = target.timing.v_total - 2;
 		target.timing.v_sync_start =
-			((uint16)((p1.timing.v_sync_start / ((float)p1.timing.v_display)) *
+			((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) *
 			target.timing.v_display));
 
 		target.timing.v_sync_end =
-			((uint16)((p1.timing.v_sync_end / ((float)p1.timing.v_display)) *
+			((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) *
 			target.timing.v_display));
 
 		target.timing.v_total =
-			((uint16)((p1.timing.v_total / ((float)p1.timing.v_display)) *
+			((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) *
 			target.timing.v_display));
 
 		if (target.timing.v_sync_start == target.timing.v_display)
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c b/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
index 1a91f9b399..6dfceb3528 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
@@ -94,13 +94,8 @@ status_t nv_crtc2_set_timing(display_mode target)
 	/* setup fixed modeline for flatpanel if connected and active */
 	if (si->ps.tmds2_active)
 	{
-		display_mode p1, p2;
-		bool pan1, pan2;
-
 		LOG(2,("CRTC2: DFP active: tuning modeline\n"));
 
-		get_panel_modelines(&p1, &p2, &pan1, &pan2);
-
 		/* horizontal timing */
 		//testing (640x480): total = 135% is too much, 120% to small...
 		//total = display + 160 equals panel modeline: but must be smaller...?
@@ -109,15 +104,15 @@ status_t nv_crtc2_set_timing(display_mode target)
 //		target.timing.h_sync_end = target.timing.h_total - 40;//48;//16
 		//adaptive to panel: fixme: test on 4:3 and 16:10 panels!
 		target.timing.h_sync_start =
-			((uint16)((p2.timing.h_sync_start / ((float)p2.timing.h_display)) *
+			((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) *
 			target.timing.h_display)) & 0xfff8;
 
 		target.timing.h_sync_end =
-			((uint16)((p2.timing.h_sync_end / ((float)p2.timing.h_display)) *
+			((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) *
 			target.timing.h_display)) & 0xfff8;
 
 		target.timing.h_total =
-			(((uint16)((p2.timing.h_total / ((float)p2.timing.h_display)) *
+			(((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) *
 			target.timing.h_display)) & 0xfff8) - 8;
 
 		if (target.timing.h_sync_start == target.timing.h_display)
@@ -130,15 +125,15 @@ status_t nv_crtc2_set_timing(display_mode target)
 //		target.timing.v_sync_start = target.timing.v_total - 3;
 //		target.timing.v_sync_end = target.timing.v_total - 2;
 		target.timing.v_sync_start =
-			((uint16)((p2.timing.v_sync_start / ((float)p2.timing.v_display)) *
+			((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) *
 			target.timing.v_display));
 
 		target.timing.v_sync_end =
-			((uint16)((p2.timing.v_sync_end / ((float)p2.timing.v_display)) *
+			((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) *
 			target.timing.v_display));
 
 		target.timing.v_total =
-			((uint16)((p2.timing.v_total / ((float)p2.timing.v_display)) *
+			((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) *
 			target.timing.v_display));
 
 		if (target.timing.v_sync_start == target.timing.v_display)