diff --git a/src/add-ons/accelerants/radeon_hd/dac.cpp b/src/add-ons/accelerants/radeon_hd/dac.cpp
index 2690b60d43..21b0b9d929 100644
--- a/src/add-ons/accelerants/radeon_hd/dac.cpp
+++ b/src/add-ons/accelerants/radeon_hd/dac.cpp
@@ -93,15 +93,15 @@ DACGetElectrical(uint8 type, uint8 dac,
 void
 DACSetModern(uint8 dacIndex, uint32 crtid)
 {
-	uint8 bandGap;
-	uint8 whiteFine;
+	bool istv = false;
 
 	// BIG TODO : NTSC, PAL, ETC.  We assume VGA for now
 	uint8 standard = FORMAT_VGA; /* VGA */
 	uint32 mode = 2;
-	bool istv = false;
 	uint32 source = istv ? 0x2 : crtid;
 
+	uint8 bandGap;
+	uint8 whiteFine;
 	DACGetElectrical(standard, dacIndex, &bandGap, &whiteFine);
 
 	uint32 mask = 0;
@@ -147,12 +147,12 @@ void
 DACSetLegacy(uint8 dacIndex, uint32 crtid)
 {
 	bool istv = false;
-	uint8 bandGap;
-	uint8 whiteFine;
 
 	// BIG TODO : NTSC, PAL, ETC.  We assume VGA for now
 	uint8 standard = FORMAT_VGA; /* VGA */
 
+	uint8 bandGap;
+	uint8 whiteFine;
 	DACGetElectrical(standard, dacIndex, &bandGap, &whiteFine);
 
 	uint32 mask = 0;
diff --git a/src/add-ons/accelerants/radeon_hd/dac.h b/src/add-ons/accelerants/radeon_hd/dac.h
index daccd93713..e69d06d69f 100644
--- a/src/add-ons/accelerants/radeon_hd/dac.h
+++ b/src/add-ons/accelerants/radeon_hd/dac.h
@@ -21,6 +21,7 @@
 #define FORMAT_VGA 0x2
 #define FORMAT_TvCV 0x3
 
+
 void DACGetElectrical(uint8 type, uint8 dac, uint8 *bandgap, uint8 *whitefine);
 void DACSet(uint8 dacIndex, uint32 crtid);
 void DACPower(uint8 dacIndex, int mode);
diff --git a/src/add-ons/accelerants/radeon_hd/pll.cpp b/src/add-ons/accelerants/radeon_hd/pll.cpp
index 0ca072424f..71a9f4d85d 100644
--- a/src/add-ons/accelerants/radeon_hd/pll.cpp
+++ b/src/add-ons/accelerants/radeon_hd/pll.cpp
@@ -262,11 +262,10 @@ PLLSetLowLegacy(uint8 pllIndex, uint32 pixelClock, uint16 reference,
 	uint32 control;
 	if (info.device_chipset == RADEON_R600)
 		control = 0x01130704;
-	else
+	else {
 		PLLControlTable(RV610PLLControl, feedback);
-
-	if (!control)
 		control = Read32(PLL, EXT1_PPLL_CNTL);
+	}
 
 	Write32Mask(PLL, P1PLL_INT_SS_CNTL, 0, 0x00000001);
 		// Disable Spread Spectrum