From 2ae3d5121c1f691cf1db3527847ac15ff33e40d1 Mon Sep 17 00:00:00 2001 From: Michael Lotz Date: Mon, 23 May 2011 14:51:42 +0000 Subject: [PATCH] Switch to using the PIT in mode 0 (interrupt on 0) instead of mode 2 (rate generator). There are chipsets (namely ATI/AMD SBx00) where mode 2 doesn't seem to work (the counter isn't reloaded after the countdown has completed). Mode 0 has the same resolution as mode 2 and, as interrupts are disabled at this point in booting, is otherwise equivalent as well. I've tested this on 5 machines available to me and it doesn't seem to have any negative effect. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41683 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/system/boot/platform/bios_ia32/cpu.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/system/boot/platform/bios_ia32/cpu.cpp b/src/system/boot/platform/bios_ia32/cpu.cpp index afbe2eee38..e9d405b883 100644 --- a/src/system/boot/platform/bios_ia32/cpu.cpp +++ b/src/system/boot/platform/bios_ia32/cpu.cpp @@ -185,7 +185,7 @@ calibration_loop(uint8 desiredHighByte, uint8 channel, uint64& tscDelta, double& conversionFactor, uint16& expired) { uint8 select = channel << PIT_SELECT_CHANNEL_SHIFT; - out8(select | PIT_ACCESS_LOW_THEN_HIGH_BYTE | PIT_MODE_RATE_GENERATOR + out8(select | PIT_ACCESS_LOW_THEN_HIGH_BYTE | PIT_MODE_INTERRUPT_ON_0 | PIT_BINARY_MODE, PIT_CONTROL); // Fill in count of 0xffff, low then high byte