From 2b83f3b47d3f5b86321d26788ed67ff42b8d5999 Mon Sep 17 00:00:00 2001 From: shatty Date: Sun, 23 Nov 2003 04:23:03 +0000 Subject: [PATCH] openBeOS_Nvidia_V0.02_src git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5447 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../private/graphics/nvidia/DriverInterface.h | 308 ++++++ headers/private/graphics/nvidia/nv_macros.h | 494 ++++++++++ .../kernel/drivers/graphics/nvidia/Jamfile | 17 + .../kernel/drivers/graphics/nvidia/driver.c | 889 ++++++++++++++++++ 4 files changed, 1708 insertions(+) create mode 100644 headers/private/graphics/nvidia/DriverInterface.h create mode 100644 headers/private/graphics/nvidia/nv_macros.h create mode 100644 src/add-ons/kernel/drivers/graphics/nvidia/Jamfile create mode 100644 src/add-ons/kernel/drivers/graphics/nvidia/driver.c diff --git a/headers/private/graphics/nvidia/DriverInterface.h b/headers/private/graphics/nvidia/DriverInterface.h new file mode 100644 index 0000000000..2afe854c34 --- /dev/null +++ b/headers/private/graphics/nvidia/DriverInterface.h @@ -0,0 +1,308 @@ +/* + Copyright 1999, Be Incorporated. All Rights Reserved. + This file may be used under the terms of the Be Sample Code License. + + Other authors: + Mark Watson; + Apsed; + Rudolf Cornelissen 10/2002-4/2003. +*/ + +#ifndef DRIVERINTERFACE_H +#define DRIVERINTERFACE_H + +#include +#include "video_overlay.h" +#include +#include +#include + +#define DRIVER_PREFIX "nv" // apsed + +/* + Internal driver state (also for sharing info between driver and accelerant) +*/ +#if defined(__cplusplus) +extern "C" { +#endif + +typedef struct { + sem_id sem; + int32 ben; +} benaphore; + +#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; +#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); +#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); +#define DELETE_BEN(x) delete_sem(x.sem); + + +#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ + +/*dualhead extensions to flags*/ +#define DUALHEAD_OFF (0<<6) +#define DUALHEAD_CLONE (1<<6) +#define DUALHEAD_ON (2<<6) +#define DUALHEAD_SWITCH (3<<6) +#define DUALHEAD_BITS (3<<6) +#define DUALHEAD_CAPABLE (1<<8) +#define TV_BITS (3<<9) +#define TV_MON (0<<9 +#define TV_PAL (1<<9) +#define TV_NTSC (2<<9) +#define TV_CAPABLE (1<<11) + +#define SKD_MOVE_CURSOR 0x00000001 +#define SKD_PROGRAM_CLUT 0x00000002 +#define SKD_SET_START_ADDR 0x00000004 +#define SKD_SET_CURSOR 0x00000008 +#define SKD_HANDLER_INSTALLED 0x80000000 + +enum { + NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, + NV_GET_PCI, + NV_SET_PCI, + NV_DEVICE_NAME, + NV_RUN_INTERRUPTS +}; + +/* max. number of overlay buffers */ +#define MAXBUFFERS 3 +/* max. pixelclock speed the BES supports */ +#define BESMAXSPEED 135000 + +/* internal used info on overlay buffers */ +typedef struct +{ + uint16 slopspace; + uint32 size; +} int_buf_info; + +typedef struct settings { // apsed, see comments in nv.settings + // for driver + char accelerant[B_FILE_NAME_LENGTH]; + bool dumprom; + // for accelerant + uint32 logmask; + uint32 memory; + bool usebios; + bool hardcursor; + bool greensync; +} settings; + +/*shared info*/ +typedef struct { + /*a few ID things*/ + uint16 vendor_id; /* PCI vendor ID, from pci_info */ + uint16 device_id; /* PCI device ID, from pci_info */ + uint8 revision; /* PCI device revsion, from pci_info */ + + /* bug workaround for 4.5.0 */ + uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ + uint32 * clone_bugfix_regs; + + /*memory mappings*/ + area_id regs_area; /* Kernel's area_id for the memory mapped registers. + It will be cloned into the accelerant's address + space. */ + + area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ + area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ + area_id dma_buffer_area; /* Area assigned for dma*/ + + void *framebuffer; /* As viewed from virtual memory */ + void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ + + void *pseudo_dma; /* As viewed from virtual memory */ + + void *dma_buffer; /* buffer for dma*/ + void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ + + /*screenmode list*/ + area_id mode_area; /* Contains the list of display modes the driver supports */ + uint32 mode_count; /* Number of display modes in the list */ + + /*flags - used by driver*/ + uint32 flags; + + /*vblank semaphore*/ + sem_id vblank; /* The vertical blank semaphore. Ownership will be + transfered to the team opening the device first */ + /*cursor information*/ + struct { + uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ + uint16 hot_y; /* is 0,0 */ + uint16 x; /* The location of the cursor hot spot on the */ + uint16 y; /* desktop */ + uint16 width; /* Width and height of the cursor shape (always 16!) */ + uint16 height; + bool is_visible; /* Is the cursor currently displayed? */ + } cursor; + + /*colour lookup table*/ + uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ + + /*more display mode stuff*/ + display_mode dm; /* current display mode configuration: head1 */ + display_mode dm2; /* current display mode configuration: head2 */ + bool switched_crtcs; /* dualhead stretch and switch mode info */ + bool acc_mode; /* signals (non)accelerated mode */ + bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */ + + /*frame buffer config - for BDirectScreen*/ + frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ + frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */ + + /*acceleration engine*/ + struct { + uint32 count; /* last dwgsync slot used */ + uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ + benaphore lock; /* for serializing access to the acceleration engine */ + } engine; + + /* card info - information gathered from PINS (and other sources) */ + enum + { // card_type in order of date of NV chip design + NV04 = 0, + NV05, + NV05M64, + NV06, + NV10, + NV11, + NV11M, + NV15, + NV17, + NV17M, + NV18, + NV18M, + NV20, + NV25, + NV28, + NV30, + NV31, + NV34, + NV35, + G550//remove later on + }; + enum + { // card_arch in order of date of NV chip design + NV04A = 0, + NV10A, + NV20A, + NV30A + }; + enum + { // tvout_chip_type in order of capability (more or less) + NONE = 0, + CH7003, + CH7004, + CH7005, + CH7006, + CH7007, + SAA7102, + SAA7108, + BT868, + BT869, + CX25870, + CX25871, + NVIDIA + }; + + struct + { + /* specialised registers for card initialisation read from NV BIOS (pins) */ + + /* general card information */ + uint32 card_type; /* see card_type enum above */ + uint32 card_arch; /* see card_arch enum above */ + bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ + uint32 tvout_chip_type; /* see tvchip_type enum above */ + status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ + bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ + + /* PINS */ + float f_ref; /* PLL reference-oscillator frequency (Mhz) */ + uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ + uint32 min_system_vco; + uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ + uint32 min_pixel_vco; + uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */ + uint32 min_video_vco; + uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ + uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ + uint32 max_dac1_clock; /* dac1 limits (Mhz) */ + uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ + uint32 max_dac1_clock_16; + uint32 max_dac1_clock_24; + uint32 max_dac1_clock_32; + uint32 max_dac1_clock_32dh; + uint32 max_dac2_clock; /* dac2 limits (Mhz) */ + uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ + uint32 max_dac2_clock_16; + uint32 max_dac2_clock_24; + uint32 max_dac2_clock_32; + uint32 max_dac2_clock_32dh; + bool secondary_head; /* presence of functions */ + bool tvout; + bool primary_dvi; + bool secondary_dvi; + uint32 memory_size; /* memory (Mb) */ + } ps; + + /*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/ + uint8 rom_mirror[32768]; + + /*CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it*/ + uint8 crtc_delay; + + /* apsed: some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ + settings settings; + + struct + { + overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ + int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ + overlay_token myToken; /* scaler is free/in use */ + benaphore lock; /* for creating buffers and aquiring overlay unit routines */ + } overlay; + +} shared_info; + +/* Read or write a value in PCI configuration space */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + uint32 offset; /* Offset to read/write */ + uint32 size; /* Number of bytes to transfer */ + uint32 value; /* The value read or written */ +} nv_get_set_pci; + +/* Set some boolean condition (like enabling or disabling interrupts) */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + bool do_it; /* state to set */ +} nv_set_bool_state; + +/* Retrieve the area_id of the kernel/accelerant shared info */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + area_id shared_info_area; /* area_id containing the shared information */ +} nv_get_private_data; + +/* Retrieve the device name. Usefull for when we have a file handle, but want +to know the device name (like when we are cloning the accelerant) */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + char *name; /* The name of the device, less the /dev root */ +} nv_device_name; + +enum { + + _WAIT_FOR_VBLANK = (1 << 0) +}; + +#if defined(__cplusplus) +} +#endif + + +#endif diff --git a/headers/private/graphics/nvidia/nv_macros.h b/headers/private/graphics/nvidia/nv_macros.h new file mode 100644 index 0000000000..51eaa61810 --- /dev/null +++ b/headers/private/graphics/nvidia/nv_macros.h @@ -0,0 +1,494 @@ +/* NV registers definitions and macros for access to */ + +//new: +/* PCI_config_space */ +#define NVCFG_DEVID 0x00 +#define NVCFG_DEVCTRL 0x04 +#define NVCFG_CLASS 0x08 +#define NVCFG_HEADER 0x0c +#define NVCFG_BASE1REGS 0x10 +#define NVCFG_BASE2FB 0x14 +#define NVCFG_BASE3 0x18 +#define NVCFG_BASE4 0x1c //unknown if used +#define NVCFG_BASE5 0x20 //unknown if used +#define NVCFG_BASE6 0x24 //unknown if used +#define NVCFG_BASE7 0x28 //unknown if used +#define NVCFG_SUBSYSID1 0x2c +#define NVCFG_ROMBASE 0x30 +#define NVCFG_CFG_0 0x34 +#define NVCFG_CFG_1 0x38 //unknown if used +#define NVCFG_INTERRUPT 0x3c +#define NVCFG_SUBSYSID2 0x40 +#define NVCFG_AGPREF 0x44 +#define NVCFG_AGPSTAT 0x48 +#define NVCFG_AGPCMD 0x4c +#define NVCFG_ROMSHADOW 0x50 +#define NVCFG_VGA 0x54 +#define NVCFG_SCHRATCH 0x58 +#define NVCFG_CFG_10 0x5c +#define NVCFG_CFG_11 0x60 +#define NVCFG_CFG_12 0x64 +#define NVCFG_CFG_13 0x68 //unknown if used +#define NVCFG_CFG_14 0x6c //unknown if used +#define NVCFG_CFG_15 0x70 //unknown if used +#define NVCFG_CFG_16 0x74 //unknown if used +#define NVCFG_CFG_17 0x78 //unknown if used +#define NVCFG_GF2IGPU 0x7c +#define NVCFG_CFG_19 0x80 //unknown if used +#define NVCFG_GF4MXIGPU 0x84 +#define NVCFG_CFG_21 0x88 //unknown if used +#define NVCFG_CFG_22 0x8c //unknown if used +#define NVCFG_CFG_23 0x90 //unknown if used +#define NVCFG_CFG_24 0x94 //unknown if used +#define NVCFG_CFG_25 0x98 //unknown if used +#define NVCFG_CFG_26 0x9c //unknown if used +#define NVCFG_CFG_27 0xa0 //unknown if used +#define NVCFG_CFG_28 0xa4 //unknown if used +#define NVCFG_CFG_29 0xa8 //unknown if used +#define NVCFG_CFG_30 0xac //unknown if used +#define NVCFG_CFG_31 0xb0 //unknown if used +#define NVCFG_CFG_32 0xb4 //unknown if used +#define NVCFG_CFG_33 0xb8 //unknown if used +#define NVCFG_CFG_34 0xbc //unknown if used +#define NVCFG_CFG_35 0xc0 //unknown if used +#define NVCFG_CFG_36 0xc4 //unknown if used +#define NVCFG_CFG_37 0xc8 //unknown if used +#define NVCFG_CFG_38 0xcc //unknown if used +#define NVCFG_CFG_39 0xd0 //unknown if used +#define NVCFG_CFG_40 0xd4 //unknown if used +#define NVCFG_CFG_41 0xd8 //unknown if used +#define NVCFG_CFG_42 0xdc //unknown if used +#define NVCFG_CFG_43 0xe0 //unknown if used +#define NVCFG_CFG_44 0xe4 //unknown if used +#define NVCFG_CFG_45 0xe8 //unknown if used +#define NVCFG_CFG_46 0xec //unknown if used +#define NVCFG_CFG_47 0xf0 //unknown if used +#define NVCFG_CFG_48 0xf4 //unknown if used +#define NVCFG_CFG_49 0xf8 //unknown if used +#define NVCFG_CFG_50 0xfc //unknown if used + +/* if(pNv->SecondCRTC) { + pNv->riva.PCIO = pNv->riva.PCIO0 + 0x2000; + pNv->riva.PCRTC = pNv->riva.PCRTC0 + 0x800; + pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0 + 0x800; + pNv->riva.PDIO = pNv->riva.PDIO0 + 0x2000; + } else { + pNv->riva.PCIO = pNv->riva.PCIO0; + pNv->riva.PCRTC = pNv->riva.PCRTC0; + pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0; + pNv->riva.PDIO = pNv->riva.PDIO0; + } +*/ + /* + * These registers are read/write as 8 bit values. Probably have to map + * sparse on alpha. + */ +/* pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, + pNv->PciTag, regBase+0x00601000, + 0x00003000); + pNv->riva.PDIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, + pNv->PciTag, regBase+0x00681000, + 0x00003000); + pNv->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, + pNv->PciTag, regBase+0x000C0000, + 0x00001000); + pNv->riva.PRAMDAC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00680000, 0x00003000); + pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00600000, 0x00003000); +*/ + +/* Nvidia PCI direct registers */ +#define NV8_MISCW 0x000c03c2 +#define NV8_MISCR 0x000c03cc +#define NV8_SEQIND 0x000c03c4 +#define NV16_SEQIND 0x000c03c4 +#define NV8_SEQDAT 0x000c03c5 +#define NV8_GRPHIND 0x000c03ce +#define NV16_GRPHIND 0x000c03ce +#define NV8_GRPHDAT 0x000c03cf + +/* bootstrap info registers */ +#define NV32_NV4STRAPINFO 0x00100000 +#define NV32_NV10STRAPINFO 0x0010020c +#define NV32_NVSTRAPINFO2 0x00101000 + +/* primary head */ +#define NV8_ATTRINDW 0x006013c0 +#define NV8_ATTRDATW 0x006013c0 +#define NV8_ATTRDATR 0x006013c1 +#define NV8_CRTCIND 0x006013d4 +#define NV16_CRTCIND 0x006013d4 +#define NV8_CRTCDAT 0x006013d5 +#define NV8_INSTAT1 0x006013da +#define NV32_NV10FBSTADD32 0x00600800 +#define NV32_CONFIG 0x00600804//not yet used (coldstart)... +#define NV32_NV10CURADD32 0x0060080c +#define NV32_CURCONF 0x00600810 + +/* secondary head */ +#define NV8_ATTR2INDW 0x006033c0 +#define NV8_ATTR2DATW 0x006033c0 +#define NV8_ATTR2DATR 0x006033c1 +#define NV8_CRTC2IND 0x006033d4 +#define NV16_CRTC2IND 0x006033d4 +#define NV8_CRTC2DAT 0x006033d5 +#define NV8_2INSTAT1 0x006033da//verify!!! +#define NV32_NV10FB2STADD32 0x00602800//verify!!! +#define NV32_NV10CUR2ADD32 0x0060280c//verify!!! +#define NV32_2CURCONF 0x00602810//verify!!! + +/* Nvidia DAC direct registers (standard VGA palette RAM registers) */ +/* primary head */ +#define NV8_PALMASK 0x006813c6 +#define NV8_PALINDR 0x006813c7 +#define NV8_PALINDW 0x006813c8 +#define NV8_PALDATA 0x006813c9 +/* secondary head */ +#define NV8_PAL2MASK 0x006833c6//verify!!! +#define NV8_PAL2INDR 0x006833c7//verify!!! +#define NV8_PAL2INDW 0x006833c8//verify!!! +#define NV8_PAL2DATA 0x006833c9//verify!!! + +/* Nvidia PCI direct DAC registers (32bit) */ +/* primary head */ +#define NVDAC_CURPOS 0x00680300 +#define NVDAC_PIXPLLC 0x00680508 +#define NVDAC_PLLSEL 0x0068050c +#define NVDAC_GENCTRL 0x00680600 +/* secondary head */ +#define NVDAC2_CURPOS 0x00680b00 +#define NVDAC2_PIXPLLC 0x00680d20//verify!!! +#define NVDAC2_PLLSEL 0x00680d0c//verify!!! +#define NVDAC2_GENCTRL 0x00680e00//verify!!! + +/* Nvidia CRTC indexed registers */ +/* VGA standard registers: */ +#define NVCRTCX_HTOTAL 0x00 +#define NVCRTCX_HDISPE 0x01 +#define NVCRTCX_HBLANKS 0x02 +#define NVCRTCX_HBLANKE 0x03 +#define NVCRTCX_HSYNCS 0x04 +#define NVCRTCX_HSYNCE 0x05 +#define NVCRTCX_VTOTAL 0x06 +#define NVCRTCX_OVERFLOW 0x07 +#define NVCRTCX_PRROWSCN 0x08 +#define NVCRTCX_MAXSCLIN 0x09 +#define NVCRTCX_VGACURCTRL 0x0a +#define NVCRTCX_FBSTADDH 0x0c //confirmed +#define NVCRTCX_FBSTADDL 0x0d //confirmed +#define NVCRTCX_VSYNCS 0x10 +#define NVCRTCX_VSYNCE 0x11 +#define NVCRTCX_VDISPE 0x12 +#define NVCRTCX_PITCHL 0x13 //confirmed +#define NVCRTCX_VBLANKS 0x15 +#define NVCRTCX_VBLANKE 0x16 +#define NVCRTCX_MODECTL 0x17 +#define NVCRTCX_LINECOMP 0x18 +/* Nvidia specific registers: */ +#define NVCRTCX_REPAINT0 0x19 +#define NVCRTCX_REPAINT1 0x1a +#define NVCRTCX_LOCK 0x1f +#define NVCRTCX_LSR 0x25 +#define NVCRTCX_PIXEL 0x28 +#define NVCRTCX_HEB 0x2d +#define NVCRTCX_CURCTL2 0x2f +#define NVCRTCX_CURCTL1 0x30 +#define NVCRTCX_CURCTL0 0x31 + +/* Nvidia ATTRIBUTE indexed registers */ +/* VGA standard registers: */ +#define NVATBX_MODECTL 0x10 +#define NVATBX_OSCANCOLOR 0x11 +#define NVATBX_COLPLANE_EN 0x12 +#define NVATBX_HORPIXPAN 0x13 //confirmed +#define NVATBX_COLSEL 0x14 + +/* Nvidia SEQUENCER indexed registers */ +/* VGA standard registers: */ +#define NVSEQX_RESET 0x00 +#define NVSEQX_CLKMODE 0x01 +#define NVSEQX_MEMMODE 0x04 + +/* Nvidia GRAPHICS indexed registers */ +/* VGA standard registers: */ +#define NVGRPHX_ENSETRESET 0x01 +#define NVGRPHX_DATAROTATE 0x03 +#define NVGRPHX_READMAPSEL 0x04 +#define NVGRPHX_MODE 0x05 +#define NVGRPHX_MISC 0x06 +#define NVGRPHX_BITMASK 0x08 +//end new. + +/* (D)AC (X) (I)ndexed registers (>= G100) */ +#define NVDXI_VREFCTRL 0x18 +#define NVDXI_MULCTRL 0x19 +#define NVDXI_PIXCLKCTRL 0x1A +#define NVDXI_GENCTRL 0x1D +#define NVDXI_MISCCTRL 0x1E +#define NVDXI_PANELMODE 0x1F +#define NVDXI_MAFCDEL 0x20 +#define NVDXI_GENIOCTRL 0x2A +#define NVDXI_GENIODATA 0x2B +#define NVDXI_SYSPLLM 0x2C +#define NVDXI_SYSPLLN 0x2D +#define NVDXI_SYSPLLP 0x2E +#define NVDXI_SYSPLLSTAT 0x2F +#define NVDXI_ZOOMCTRL 0x38 +#define NVDXI_SENSETEST 0x3A +#define NVDXI_CRCREML 0x3C +#define NVDXI_CRCREMH 0x3D +#define NVDXI_CRCBITSEL 0x3E +#define NVDXI_COLMSK 0x40 +#define NVDXI_COLKEY 0x42 +#define NVDXI_PIXPLLAM 0x44 +#define NVDXI_PIXPLLAN 0x45 +#define NVDXI_PIXPLLAP 0x46 +#define NVDXI_PIXPLLBM 0x48 +#define NVDXI_PIXPLLBN 0x49 +#define NVDXI_PIXPLLBP 0x4A +#define NVDXI_PIXPLLCM 0x4C +#define NVDXI_PIXPLLCN 0x4D +#define NVDXI_PIXPLLCP 0x4E +#define NVDXI_PIXPLLSTAT 0x4F +#define NVDXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/ + +/* (D)AC (X) (I)ndexed registers (>= G200) */ +#define NVDXI_KEYOPMODE 0x51 +#define NVDXI_COLMSK0RED 0x52 +#define NVDXI_COLMSK0GREEN 0x53 +#define NVDXI_COLMSK0BLUE 0x54 +#define NVDXI_COLKEY0RED 0x55 +#define NVDXI_COLKEY0GREEN 0x56 +#define NVDXI_COLKEY0BLUE 0x57 + +/* (D)AC (X) (I)ndexed registers (>= G450) */ +#define NVDXI_TVO_IDX 0x87 +#define NVDXI_TVO_DATA 0x88 +#define NVDXI_OUTPUTCONN 0x8A +#define NVDXI_SYNCCTRL 0x8B +#define NVDXI_VIDPLLSTAT 0x8C +#define NVDXI_VIDPLLP 0x8D +#define NVDXI_VIDPLLM 0x8E +#define NVDXI_VIDPLLN 0x8F +#define NVDXI_PWRCTRL 0xA0 +#define NVDXI_PANMODE 0xA2 + +/* NV 1st CRTC registers */ +#define NVCR1_VCOUNT 0x1E20 + +/* NV 2nd CRTC registers (>= G400) */ +#define NVCR2_CTL 0x3C10 +#define NVCR2_HPARAM 0x3C14 +#define NVCR2_HSYNC 0x3C18 +#define NVCR2_VPARAM 0x3C1C +#define NVCR2_VSYNC 0x3C20 +#define NVCR2_PRELOAD 0x3C24 +#define NVCR2_STARTADD0 0x3C28 +#define NVCR2_STARTADD1 0x3C2C +#define NVCR2_OFFSET 0x3C40 +#define NVCR2_MISC 0x3C44 +#define NVCR2_VCOUNT 0x3C48 +#define NVCR2_DATACTL 0x3C4C + +/* NV ACCeleration registers */ +#define NVACC_DWGCTL 0x1C00 +#define NVACC_MACCESS 0x1C04 +#define NVACC_MCTLWTST 0x1C08 +#define NVACC_ZORG 0x1C0C +#define NVACC_PLNWT 0x1C1C +#define NVACC_BCOL 0x1C20 +#define NVACC_FCOL 0x1C24 +#define NVACC_XYSTRT 0x1C40 +#define NVACC_XYEND 0x1C44 +#define NVACC_SGN 0x1C58 +#define NVACC_LEN 0x1C5C +#define NVACC_AR0 0x1C60 +#define NVACC_AR3 0x1C6C +#define NVACC_AR5 0x1C74 +#define NVACC_CXBNDRY 0x1C80 +#define NVACC_FXBNDRY 0x1C84 +#define NVACC_YDSTLEN 0x1C88 +#define NVACC_PITCH 0x1C8C +#define NVACC_YDST 0x1C90 +#define NVACC_YDSTORG 0x1C94 +#define NVACC_YTOP 0x1C98 +#define NVACC_YBOT 0x1C9C +#define NVACC_CXLEFT 0x1CA0 +#define NVACC_CXRIGHT 0x1CA4 +#define NVACC_FXLEFT 0x1CA8 +#define NVACC_FXRIGHT 0x1CAC +#define NVACC_STATUS 0x1E14 +#define NVACC_ICLEAR 0x1E18 /* required for interrupt stuff */ +#define NVACC_IEN 0x1E1C /* required for interrupt stuff */ +#define NVACC_RST 0x1E40 +#define NVACC_MEMRDBK 0x1E44 +#define NVACC_OPMODE 0x1E54 +#define NVACC_PRIMADDRESS 0x1E58 +#define NVACC_PRIMEND 0x1E5C +#define NVACC_TEXORG 0x2C24 // >= G100 +#define NVACC_DWGSYNC 0x2C4C // >= G200 +#define NVACC_TEXORG1 0x2CA4 // >= G200 +#define NVACC_TEXORG2 0x2CA8 // >= G200 +#define NVACC_TEXORG3 0x2CAC // >= G200 +#define NVACC_TEXORG4 0x2CB0 // >= G200 +#define NVACC_SRCORG 0x2CB4 // >= G200 +#define NVACC_DSTORG 0x2CB8 // >= G200 + +/*NV BES (Back End Scaler) registers (>= G200) */ +#define NVBES_A1ORG 0x3D00 +#define NVBES_A2ORG 0x3D04 +#define NVBES_B1ORG 0x3D08 +#define NVBES_B2ORG 0x3D0C +#define NVBES_A1CORG 0x3D10 +#define NVBES_A2CORG 0x3D14 +#define NVBES_B1CORG 0x3D18 +#define NVBES_B2CORG 0x3D1C +#define NVBES_CTL 0x3D20 +#define NVBES_PITCH 0x3D24 +#define NVBES_HCOORD 0x3D28 +#define NVBES_VCOORD 0x3D2C +#define NVBES_HISCAL 0x3D30 +#define NVBES_VISCAL 0x3D34 +#define NVBES_HSRCST 0x3D38 +#define NVBES_HSRCEND 0x3D3C +#define NVBES_LUMACTL 0x3D40 +#define NVBES_V1WGHT 0x3D48 +#define NVBES_V2WGHT 0x3D4C +#define NVBES_HSRCLST 0x3D50 +#define NVBES_V1SRCLST 0x3D54 +#define NVBES_V2SRCLST 0x3D58 +#define NVBES_A1C3ORG 0x3D60 +#define NVBES_A2C3ORG 0x3D64 +#define NVBES_B1C3ORG 0x3D68 +#define NVBES_B2C3ORG 0x3D6C +#define NVBES_GLOBCTL 0x3DC0 +#define NVBES_STATUS 0x3DC4 + +/*MAVEN registers (<= G400) */ +#define NVMAV_PGM 0x3E +#define NVMAV_PIXPLLM 0x80 +#define NVMAV_PIXPLLN 0x81 +#define NVMAV_PIXPLLP 0x82 +#define NVMAV_GAMMA1 0x83 +#define NVMAV_GAMMA2 0x84 +#define NVMAV_GAMMA3 0x85 +#define NVMAV_GAMMA4 0x86 +#define NVMAV_GAMMA5 0x87 +#define NVMAV_GAMMA6 0x88 +#define NVMAV_GAMMA7 0x89 +#define NVMAV_GAMMA8 0x8A +#define NVMAV_GAMMA9 0x8B +#define NVMAV_MONSET 0x8C +#define NVMAV_TEST 0x8D +#define NVMAV_WREG_0X8E_L 0x8E +#define NVMAV_WREG_0X8E_H 0x8F +#define NVMAV_HSCALETV 0x90 +#define NVMAV_TSCALETVL 0x91 +#define NVMAV_TSCALETVH 0x92 +#define NVMAV_FFILTER 0x93 +#define NVMAV_MONEN 0x94 +#define NVMAV_RESYNC 0x95 +#define NVMAV_LASTLINEL 0x96 +#define NVMAV_LASTLINEH 0x97 +#define NVMAV_WREG_0X98_L 0x98 +#define NVMAV_WREG_0X98_H 0x99 +#define NVMAV_HSYNCLENL 0x9A +#define NVMAV_HSYNCLENH 0x9B +#define NVMAV_HSYNCSTRL 0x9C +#define NVMAV_HSYNCSTRH 0x9D +#define NVMAV_HDISPLAYL 0x9E +#define NVMAV_HDISPLAYH 0x9F +#define NVMAV_HTOTALL 0xA0 +#define NVMAV_HTOTALH 0xA1 +#define NVMAV_VSYNCLENL 0xA2 +#define NVMAV_VSYNCLENH 0xA3 +#define NVMAV_VSYNCSTRL 0xA4 +#define NVMAV_VSYNCSTRH 0xA5 +#define NVMAV_VDISPLAYL 0xA6 +#define NVMAV_VDISPLAYH 0xA7 +#define NVMAV_VTOTALL 0xA8 +#define NVMAV_VTOTALH 0xA9 +#define NVMAV_HVIDRSTL 0xAA +#define NVMAV_HVIDRSTH 0xAB +#define NVMAV_VVIDRSTL 0xAC +#define NVMAV_VVIDRSTH 0xAD +#define NVMAV_VSOMETHINGL 0xAE +#define NVMAV_VSOMETHINGH 0xAF +#define NVMAV_OUTMODE 0xB0 +#define NVMAV_LOCK 0xB3 +#define NVMAV_LUMA 0xB9 +#define NVMAV_VDISPLAYTV 0xBE +#define NVMAV_STABLE 0xBF +#define NVMAV_HDISPLAYTV 0xC2 +#define NVMAV_BREG_0XC6 0xC6 + +//new: +/* Macros for convenient accesses to the NV chips */ +#define NV_REG8(r_) ((vuint8 *)regs)[(r_)] +#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] +#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] + +/* read and write to PCI config space */ +#define CFGR(A) (nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), nv_pci_access.value) +#define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access))) + +/* read and write from the dac registers */ +#define DACR(A) (NV_REG32(NVDAC_##A)) +#define DACW(A,B) (NV_REG32(NVDAC_##A)=B) +#define DAC2R(A) (NV_REG32(NVDAC2_##A)) +#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) +//end new. + +/* read and write from the dac index register */ +#define DXIR(A) (DACW(PALWTADD,NVDXI_##A),DACR(X_DATAREG)) +#define DXIW(A,B) (DACW(PALWTADD,NVDXI_##A),DACW(X_DATAREG,B)) + +/* read and write from the vga registers */ +#define VGAR(A) (NV_REG8(NVVGA_##A)) +#define VGAW(A,B) (NV_REG8(NVVGA_##A)=B) + +/* read and write from the indexed vga registers */ +#define VGAR_I(A,B) (VGAW(A##_I,B),VGAR(A##_D)) +#define VGAW_I(A,B,C) (VGAW(A##_I,B),VGAW(A##_D,C)) + +/* read and write from the powergraphics registers */ +#define ACCR(A) (NV_REG32(NVACC_##A)) +#define ACCW(A,B) (NV_REG32(NVACC_##A)=B) +#define ACCGO(A,B) (NV_REG32(NVACC_##A + 0x0100)=B) + +/* read and write from the backend scaler registers */ +#define BESR(A) (NV_REG32(NVBES_##A)) +#define BESW(A,B) (NV_REG32(NVBES_##A)=B) + +/* read and write from first CRTC */ +#define CR1R(A) (NV_REG32(NVCR1_##A)) +#define CR1W(A,B) (NV_REG32(NVCR1_##A)=B) + +/* read and write from second CRTC */ +#define CR2R(A) (NV_REG32(NVCR2_##A)) +#define CR2W(A,B) (NV_REG32(NVCR2_##A)=B) + +//new: +/* read and write from CRTC indexed registers */ +#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8))) +#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT)) + +/* read and write from ATTRIBUTE indexed registers */ +#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B)) +#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR)) + +/* read and write from SEQUENCER indexed registers */ +#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8))) +#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT)) + +/* read and write from PCI GRAPHICS indexed registers (>= NM2097) */ +#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8))) +#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT)) +//end new. + +/* read and write from maven (<= G400) */ +#define MAVR(A) (i2c_maven_read (NVMAV_##A )) +#define MAVW(A,B) (i2c_maven_write(NVMAV_##A ,B)) +#define MAVRW(A) (i2c_maven_read (NVMAV_##A )|(i2c_maven_read(NVMAV_##A +1)<<8)) +#define MAVWW(A,B) (i2c_maven_write(NVMAV_##A ,B &0xFF),i2c_maven_write(NVMAV_##A +1,B >>8)) diff --git a/src/add-ons/kernel/drivers/graphics/nvidia/Jamfile b/src/add-ons/kernel/drivers/graphics/nvidia/Jamfile new file mode 100644 index 0000000000..bd03a4ffea --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/nvidia/Jamfile @@ -0,0 +1,17 @@ +SubDir OBOS_TOP src add-ons kernel drivers graphics nvidia ; + +UsePrivateHeaders graphics ; +UsePrivateHeaders graphics nvidia ; + +R5KernelAddon nv.driver : kernel drivers bin : + driver.c +; + +# Link to kernel/drivers/dev/graphics +{ + local dir = [ FDirName $(OBOS_ADDON_DIR) kernel drivers dev graphics ] ; + local instDriver = nv.driver ; + MakeLocate $(instDriver) : $(dir) ; + RelSymLink $(instDriver) : nv.driver ; +} + diff --git a/src/add-ons/kernel/drivers/graphics/nvidia/driver.c b/src/add-ons/kernel/drivers/graphics/nvidia/driver.c new file mode 100644 index 0000000000..5d5c77c218 --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/nvidia/driver.c @@ -0,0 +1,889 @@ +/* + Copyright 1999, Be Incorporated. All Rights Reserved. + This file may be used under the terms of the Be Sample Code License. + + Other authors: + Mark Watson; + Rudolf Cornelissen 3/2002-7/2003. +*/ + +/* standard kernel driver stuff */ +#include +#include +#include +#include +#include +#include // for strtoXX + +/* this is for the standardized portion of the driver API */ +/* currently only one operation is defined: B_GET_ACCELERANT_SIGNATURE */ +#include + +/* this is for sprintf() */ +#include + +/* this is for string compares */ +#include + +/* The private interface between the accelerant and the kernel driver. */ +#include "DriverInterface.h" +#include "nv_macros.h" + +#define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) +#define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) + +#define MAX_DEVICES 8 + +#define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" // apsed + +/* Tell the kernel what revision of the driver API we support */ +int32 api_version = B_CUR_DRIVER_API_VERSION; // apsed, was 2, is 2 in R5 + +/* these structures are private to the kernel driver */ +typedef struct device_info device_info; + +typedef struct { + timer te; /* timer entry for add_timer() */ + device_info *di; /* pointer to the owning device */ + bigtime_t when_target; /* when we're supposed to wake up */ +} timer_info; + +struct device_info { + uint32 is_open; /* a count of how many times the devices has been opened */ + area_id shared_area; /* the area shared between the driver and all of the accelerants */ + shared_info *si; /* a pointer to the shared area, for convenience */ + vuint32 *regs; /* kernel's pointer to memory mapped registers */ + pci_info pcii; /* a convenience copy of the pci info for this device */ + char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ +}; + +typedef struct { + uint32 count; /* number of devices actually found */ + benaphore kernel; /* for serializing opens/closes */ + char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ + device_info di[MAX_DEVICES]; /* device specific stuff */ +} DeviceData; + +/* prototypes for our private functions */ +static status_t open_hook (const char* name, uint32 flags, void** cookie); +static status_t close_hook (void* dev); +static status_t free_hook (void* dev); +static status_t read_hook (void* dev, off_t pos, void* buf, size_t* len); +static status_t write_hook (void* dev, off_t pos, const void* buf, size_t* len); +static status_t control_hook (void* dev, uint32 msg, void *buf, size_t len); +static status_t map_device(device_info *di); +static void unmap_device(device_info *di); +static void probe_devices(void); +static int32 nv_interrupt(void *data); + +static DeviceData *pd; +static pci_module_info *pci_bus; +static device_hooks graphics_device_hooks = { + open_hook, + close_hook, + free_hook, + control_hook, + read_hook, + write_hook, + NULL, + NULL, + NULL, + NULL +}; + +#define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ +#define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ +#define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ +#define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ + +static uint16 nvidia_device_list[] = { + 0x0020, /* Nvidia TNT1 */ + 0x0028, /* Nvidia TNT2 (pro) */ + 0x0029, /* Nvidia TNT2 Ultra */ + 0x002a, /* Nvidia TNT2 */ + 0x002b, /* Nvidia TNT2 */ + 0x002c, /* Nvidia Vanta (Lt) */ + 0x002d, /* Nvidia TNT2-M64 (Pro) */ + 0x002e, /* Nvidia NV06 Vanta */ + 0x002f, /* Nvidia NV06 Vanta */ + 0x00a0, /* Nvidia Aladdin TNT2 */ + 0x0100, /* Nvidia GeForce256 SDR */ + 0x0101, /* Nvidia GeForce256 DDR */ + 0x0102, /* Nvidia GeForce256 Ultra */ + 0x0103, /* Nvidia Quadro */ + 0x0110, /* Nvidia GeForce2 MX/MX400 */ + 0x0111, /* Nvidia GeForce2 MX100/MX200 DDR */ + 0x0112, /* Nvidia GeForce2 Go */ + 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ + 0x0150, /* Nvidia GeForce2 GTS/Pro */ + 0x0151, /* Nvidia GeForce2 Ti DDR */ + 0x0152, /* Nvidia GeForce2 Ultra */ + 0x0153, /* Nvidia Quadro2 Pro */ + 0x0170, /* Nvidia GeForce4 MX 460 */ + 0x0171, /* Nvidia GeForce4 MX 440 */ + 0x0172, /* Nvidia GeForce4 MX 420 */ + 0x0173, /* Nvidia GeForce4 MX 440SE */ + 0x0174, /* Nvidia GeForce4 440 Go */ + 0x0175, /* Nvidia GeForce4 420 Go */ + 0x0176, /* Nvidia GeForce4 420 Go 32M */ + 0x0177, /* Nvidia GeForce4 460 Go */ + 0x0179, /* Nvidia GeForce4 440 Go 64M */ + 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ + 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ + 0x017c, /* Nvidia Quadro4 500 GoGL */ + //fixme: three IDs below correct?? + 0x0180, /* Nvidia GeForce4 MX 440 AGP8X */ + 0x0181, /* Nvidia GeForce4 MX 440SE AGP8X */ + 0x0182, /* Nvidia GeForce4 MX 420 AGP8X */ + 0x0188, /* Nvidia Quadro4 580 XGL */ + 0x018a, /* Nvidia Quadro4 280 NVS */ + 0x018b, /* Nvidia Quadro4 380 XGL */ + 0x01a0, /* Nvidia GeForce2 Integrated GPU */ + 0x01f0, /* Nvidia GeForce4 MX Integrated GPU */ + 0x0200, /* Nvidia GeForce3 */ + 0x0201, /* Nvidia GeForce3 Ti 200 */ + 0x0202, /* Nvidia GeForce3 Ti 500 */ + 0x0203, /* Nvidia Quadro DCC */ + 0x0250, /* Nvidia GeForce4 Ti 4600 */ + 0x0251, /* Nvidia GeForce4 Ti 4400 */ + 0x0253, /* Nvidia GeForce4 Ti 4200 */ + 0x0258, /* Nvidia Quadro4 900 XGL */ + 0x0259, /* Nvidia Quadro4 750 XGL */ + 0x025b, /* Nvidia Quadro4 700 XGL */ + 0x0280, /* Nvidia GeForce4 Ti 4600 AGP8X */ + 0x0281, /* Nvidia GeForce4 Ti 4200 AGP8X */ + 0x0282, /* Nvidia GeForce4 Ti 4800SE */ + 0x0286, /* Nvidia GeForce4 4200 Go */ + 0x0288, /* Nvidia Quadro4 980 XGL */ + 0x0289, /* Nvidia Quadro4 780 XGL */ + 0x02a0, /* Nvidia GeForce3 Integrated GPU */ + 0x0301, /* Nvidia GeForce FX 5800 Ultra */ + 0x0302, /* Nvidia GeForce FX 5800 */ + 0x0308, /* Nvidia Quadro FX 2000 */ + 0x0309, /* Nvidia Quadro FX 1000 */ + 0x0311, /* Nvidia GeForce FX 5600 Ultra */ + 0x0312, /* Nvidia GeForce FX 5600 */ + 0x031a, /* Nvidia GeForce FX 5600 Go */ + 0x0321, /* Nvidia GeForce FX 5200 Ultra */ + 0x0322, /* Nvidia GeForce FX 5200 */ + 0x032b, /* Nvidia Quadro FX 500 */ + 0x0330, /* Nvidia GeForce FX 5900 Ultra */ + 0x0331, /* Nvidia GeForce FX 5900 */ + 0x0338, /* Nvidia Quadro FX 3000 */ + 0 +}; + +static uint16 elsa_device_list[] = { + 0x0c60, /* Elsa Gladiac Geforce2 MX */ + 0 +}; + +static uint16 nvstbsgs_device_list[] = { + 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ + 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ + 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ + 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ + 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ + 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ + 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ + 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ + 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ + 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ + 0 +}; + +static uint16 varisys_device_list[] = { + 0x3503, /* Varisys GeForce4 MX440 */ + 0x3505, /* Varisys GeForce4 Ti 4200 */ + 0 +}; + +static struct { + uint16 vendor; + uint16 *devices; +} SupportedDevices[] = { + {VENDOR_ID_NVIDIA, nvidia_device_list}, + {VENDOR_ID_ELSA, elsa_device_list}, + {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, + {VENDOR_ID_VARISYS, varisys_device_list}, + {0x0000, NULL} +}; + +static settings current_settings = { // see comments in nv.settings + // for driver + DRIVER_PREFIX ".accelerant", + false, // dumprom + // for accelerant + 0x00000000, // logmask + 0, // memory + false, // usebios + false, // hardcursor + false, // greensync +}; + +static void dumprom (void *rom, size_t size) +{ + int fd = open ("/boot/home/" DRIVER_PREFIX ".rom", O_WRONLY | O_CREAT, 0666); + if (fd < 0) return; + write (fd, rom, size); + close (fd); +} + +/*return 1, is interrupt has occured*/ +int caused_vbi(vuint32 * regs) +{ +// return (ACCR(STATUS)&0x20); +//temp: +return 0; +} + +/*clear the interrupt*/ +void clear_vbi(vuint32 * regs) +{ +// ACCW(ICLEAR,0x20); +} + +void enable_vbi(vuint32 * regs) +{ +// ACCW(IEN,ACCR(IEN)|0x20); +} + +void disable_vbi(vuint32 * regs) +{ +// ACCW(IEN,(ACCR(IEN)&~0x20)); +// ACCW(ICLEAR,0x20); +} + + +/* + init_hardware() - Returns B_OK if one is + found, otherwise returns B_ERROR so the driver will be unloaded. +*/ +status_t +init_hardware(void) { + long pci_index = 0; + pci_info pcii; + bool found_one = FALSE; + + /* choke if we can't find the PCI bus */ + if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) + return B_ERROR; + + /* while there are more pci devices */ + while ((*pci_bus->get_nth_pci_info)(pci_index, &pcii) == B_NO_ERROR) { + int vendor = 0; + + /* if we match a supported vendor */ + while (SupportedDevices[vendor].vendor) { + if (SupportedDevices[vendor].vendor == pcii.vendor_id) { + uint16 *devices = SupportedDevices[vendor].devices; + /* while there are more supported devices */ + while (*devices) { + /* if we match a supported device */ + if (*devices == pcii.device_id ) { + + found_one = TRUE; + goto done; + } + /* next supported device */ + devices++; + } + } + vendor++; + } + /* next pci_info struct, please */ + pci_index++; + } + +done: + /* put away the module manager */ + put_module(B_PCI_MODULE_NAME); + return (found_one ? B_OK : B_ERROR); +} + +status_t +init_driver(void) { + void *settings_handle; + + // get driver/accelerant settings, apsed + settings_handle = load_driver_settings (DRIVER_PREFIX ".settings"); + if (settings_handle != NULL) { + const char *item; + char *end; + uint32 value; + + // for driver + item = get_driver_parameter (settings_handle, "accelerant", "", ""); + if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.accelerant) - 1)) { + strcpy (current_settings.accelerant, item); + } + current_settings.dumprom = get_driver_boolean_parameter (settings_handle, "dumprom", false, false); + + // for accelerant + item = get_driver_parameter (settings_handle, "logmask", "0x00000000", "0x00000000"); + value = strtoul (item, &end, 0); + if (*end == '\0') current_settings.logmask = value; + + item = get_driver_parameter (settings_handle, "memory", "0", "0"); + value = strtoul (item, &end, 0); + if (*end == '\0') current_settings.memory = value; + + current_settings.hardcursor = get_driver_boolean_parameter (settings_handle, "hardcursor", false, false); + current_settings.usebios = get_driver_boolean_parameter (settings_handle, "usebios", false, false); + current_settings.greensync = get_driver_boolean_parameter (settings_handle, "greensync", false, false); + + unload_driver_settings (settings_handle); + } + + /* get a handle for the pci bus */ + if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) + return B_ERROR; + + /* driver private data */ + pd = (DeviceData *)calloc(1, sizeof(DeviceData)); + if (!pd) { + put_module(B_PCI_MODULE_NAME); + return B_ERROR; + } + /* initialize the benaphore */ + INIT_BEN(pd->kernel); + /* find all of our supported devices */ + probe_devices(); + return B_OK; +} + +const char ** +publish_devices(void) { + /* return the list of supported devices */ + return (const char **)pd->device_names; +} + +device_hooks * +find_device(const char *name) { + int index = 0; + while (pd->device_names[index]) { + if (strcmp(name, pd->device_names[index]) == 0) + return &graphics_device_hooks; + index++; + } + return NULL; + +} + +void uninit_driver(void) { + + /* free the driver data */ + DELETE_BEN(pd->kernel); + free(pd); + pd = NULL; + + /* put the pci module away */ + put_module(B_PCI_MODULE_NAME); +} + +static status_t map_device(device_info *di) +{ + char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ + shared_info *si = di->si; + uint32 tmpUlong; + pci_info *pcii = &(di->pcii); + system_info sysinfo; + + /*storage for the physical to virtual table (used for dma buffer)*/ +// physical_entry physical_memory[2]; +// #define G400_DMA_BUFFER_SIZE 1024*1024 + + /*variables for making copy of ROM*/ + char * rom_temp; + area_id rom_area; + + /* Nvidia cards have registers in [0] and framebuffer in [1] */ + int registers = 0; + int frame_buffer = 1; +// int pseudo_dma = 2; + + /* enable memory mapped IO, disable VGA I/O - this is standard*/ + tmpUlong = get_pci(PCI_command, 4); + /* enable PCI access */ + tmpUlong |= PCI_command_memory; + /* enable busmastering */ + tmpUlong |= PCI_command_master; + /* disable ISA I/O access */ + tmpUlong &= ~PCI_command_io; + set_pci(PCI_command, 4, tmpUlong); + + /*work out which version of BeOS is running*/ + get_system_info(&sysinfo); + if (sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ + { + si->use_clone_bugfix = 1; + } + else + { + si->use_clone_bugfix = 0; + } + + /* work out a name for the register mapping */ + sprintf(buffer, DEVICE_FORMAT " regs", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* get a virtual memory address for the registers*/ + si->regs_area = map_physical_memory( + buffer, + /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ + (void *) di->pcii.u.h0.base_registers_pci[registers], + di->pcii.u.h0.base_register_sizes[registers], + B_ANY_KERNEL_ADDRESS, + (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), + (void **)&(di->regs)); + si->clone_bugfix_regs = (uint32 *) di->regs; + + /* if mapping registers to vmem failed then pass on error */ + if (si->regs_area < 0) return si->regs_area; + + /* work out a name for the ROM mapping*/ + sprintf(buffer, DEVICE_FORMAT " rom", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /*place ROM over the fbspace (this is definately safe)*/ + tmpUlong = di->pcii.u.h0.base_registers[frame_buffer]; + tmpUlong |= 0x00000001; + set_pci(PCI_rom_base, 4, tmpUlong); + + rom_area = map_physical_memory( + buffer, + (void *)di->pcii.u.h0.base_registers[frame_buffer], + 32768, + B_ANY_KERNEL_ADDRESS, + B_READ_AREA, + (void **)&(rom_temp) + ); + + /* if mapping ROM to vmem failed then clean up and pass on error */ + if (rom_area < 0) { + delete_area(si->regs_area); + si->regs_area = -1; + return rom_area; + } + + /* make a copy of ROM for future reference*/ + memcpy (si->rom_mirror, rom_temp, 32768); + if (current_settings.dumprom) dumprom (rom_temp, 32768); + + /*disable ROM and delete the area*/ + set_pci(PCI_rom_base,4,0); + delete_area(rom_area); + + /* work out a name for the framebuffer mapping*/ + sprintf(buffer, DEVICE_FORMAT " framebuffer", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* map the framebuffer into vmem, using Write Combining*/ + si->fb_area = map_physical_memory( + buffer, + /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ + (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], + di->pcii.u.h0.base_register_sizes[frame_buffer], + B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, + B_READ_AREA + B_WRITE_AREA, + &(si->framebuffer)); + + /*if failed with write combining try again without*/ + if (si->fb_area < 0) { + si->fb_area = map_physical_memory( + buffer, + /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ + (void *) di->pcii.u.h0.base_registers_pci[frame_buffer], + di->pcii.u.h0.base_register_sizes[frame_buffer], + B_ANY_KERNEL_BLOCK_ADDRESS, + B_READ_AREA + B_WRITE_AREA, + &(si->framebuffer)); + } + + /* if there was an error, delete our other areas and pass on error*/ + if (si->fb_area < 0) + { + delete_area(si->regs_area); + si->regs_area = -1; + return si->fb_area; + } +//fixme: retest for card coldstart and PCI/virt_mem mapping!! + /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ + si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; + + // remember settings for use here and in accelerant + si->settings = current_settings; + + /* in any case, return the result */ + return si->fb_area; +} + +static void unmap_device(device_info *di) { + shared_info *si = di->si; + uint32 tmpUlong; + pci_info *pcii = &(di->pcii); + + /* disable memory mapped IO */ + tmpUlong = get_pci(PCI_command, 4); + tmpUlong &= 0xfffffffc; + set_pci(PCI_command, 4, tmpUlong); + /* delete the areas */ + if (si->regs_area >= 0) delete_area(si->regs_area); + if (si->fb_area >= 0) delete_area(si->fb_area); + si->regs_area = si->fb_area = -1; + si->framebuffer = NULL; + di->regs = NULL; +} + +static void probe_devices(void) { + uint32 pci_index = 0; + uint32 count = 0; + device_info *di = pd->di; + + /* while there are more pci devices */ + while ((count < MAX_DEVICES) && ((*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_NO_ERROR)) { + int vendor = 0; + + /* if we match a supported vendor */ + while (SupportedDevices[vendor].vendor) { + if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { + uint16 *devices = SupportedDevices[vendor].devices; + /* while there are more supported devices */ + while (*devices) { + /* if we match a supported device */ + if (*devices == di->pcii.device_id ) { + /* publish the device name */ + sprintf(di->name, "graphics/" DEVICE_FORMAT, + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* remember the name */ + pd->device_names[count] = di->name; + /* mark the driver as available for R/W open */ + di->is_open = 0; + /* mark areas as not yet created */ + di->shared_area = -1; + /* mark pointer to shared data as invalid */ + di->si = NULL; + /* inc pointer to device info */ + di++; + /* inc count */ + count++; + /* break out of these while loops */ + goto next_device; + } + /* next supported device */ + devices++; + } + } + vendor++; + } +next_device: + /* next pci_info struct, please */ + pci_index++; + } + /* propagate count */ + pd->count = count; + /* terminate list of device names with a null pointer */ + pd->device_names[pd->count] = NULL; +} + +static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) { + uint32 handled = B_HANDLED_INTERRUPT; + /* release the vblank semaphore */ + if (si->vblank >= 0) { + int32 blocked; + if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { + release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); + handled = B_INVOKE_SCHEDULER; + } + } + return handled; +} + +static int32 +nv_interrupt(void *data) +{ + int32 handled = B_UNHANDLED_INTERRUPT; + device_info *di = (device_info *)data; + shared_info *si = di->si; + int32 *flags = &(si->flags); + vuint32 *regs; + + /* is someone already handling an interrupt for this device? */ + if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) { + goto exit0; + } + /* get regs */ + regs = di->regs; + + /* was it a VBI? */ + if (caused_vbi(regs)) { + /*clear the interrupt*/ + clear_vbi(regs); + /*release the semaphore*/ + handled = thread_interrupt_work(flags, regs, si); + } + + /* note that we're not in the handler any more */ + atomic_and(flags, ~SKD_HANDLER_INSTALLED); + +exit0: + return handled; +} + +static status_t open_hook (const char* name, uint32 flags, void** cookie) { + int32 index = 0; + device_info *di; + shared_info *si; + thread_id thid; + thread_info thinfo; + status_t result = B_OK; + vuint32 *regs; + char shared_name[B_OS_NAME_LENGTH]; + + /* find the device name in the list of devices */ + /* we're never passed a name we didn't publish */ + while (pd->device_names[index] && (strcmp(name, pd->device_names[index]) != 0)) index++; + + /* for convienience */ + di = &(pd->di[index]); + + /* make sure no one else has write access to the common data */ + AQUIRE_BEN(pd->kernel); + + /* if it's already open for writing */ + if (di->is_open) { + /* mark it open another time */ + goto mark_as_open; + } + /* create the shared area */ + sprintf(shared_name, DEVICE_FORMAT " shared", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + /* create this area with NO user-space read or write permissions, to prevent accidental dammage */ + di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 0); + if (di->shared_area < 0) { + /* return the error */ + result = di->shared_area; + goto done; + } + + /* save a few dereferences */ + si = di->si; + + /* save the vendor and device IDs */ + si->vendor_id = di->pcii.vendor_id; + si->device_id = di->pcii.device_id; + si->revision = di->pcii.revision; + + /* map the device */ + result = map_device(di); + if (result < 0) goto free_shared; + result = B_OK; + + /* create a semaphore for vertical blank management */ + si->vblank = create_sem(0, di->name); + if (si->vblank < 0) { + result = si->vblank; + goto unmap; + } + + /* change the owner of the semaphores to the opener's team */ + /* this is required because apps can't aquire kernel semaphores */ + thid = find_thread(NULL); + get_thread_info(thid, &thinfo); + set_sem_owner(si->vblank, thinfo.team); + + /* assign local regs pointer for SAMPLExx() macros */ + regs = di->regs; + + /* disable and clear any pending interrupts */ + disable_vbi(regs); + + /* If there is a valid interrupt line assigned then set up interrupts */ + if ((di->pcii.u.h0.interrupt_pin == 0x00) || + (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ + (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ + { + /* interrupt does not exist so exit without installing our handler */ + goto delete_the_sem; + } + else + { + /* otherwise install our interrupt handler */ + result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); + /* bail if we couldn't install the handler */ + if (result != B_OK) goto delete_the_sem; + } + +mark_as_open: + /* mark the device open */ + di->is_open++; + + /* send the cookie to the opener */ + *cookie = di; + + goto done; + + +delete_the_sem: + delete_sem(si->vblank); + +unmap: + unmap_device(di); + +free_shared: + /* clean up our shared area */ + delete_area(di->shared_area); + di->shared_area = -1; + di->si = NULL; + +done: + /* end of critical section */ + RELEASE_BEN(pd->kernel); + + /* all done, return the status */ + return result; +} + +/* ---------- + read_hook - does nothing, gracefully +----- */ +static status_t +read_hook (void* dev, off_t pos, void* buf, size_t* len) +{ + *len = 0; + return B_NOT_ALLOWED; +} + + +/* ---------- + write_hook - does nothing, gracefully +----- */ +static status_t +write_hook (void* dev, off_t pos, const void* buf, size_t* len) +{ + *len = 0; + return B_NOT_ALLOWED; +} + +/* ---------- + close_hook - does nothing, gracefully +----- */ +static status_t +close_hook (void* dev) +{ + /* we don't do anything on close: there might be dup'd fd */ + return B_NO_ERROR; +} + +/* ----------- + free_hook - close down the device +----------- */ +static status_t +free_hook (void* dev) { + device_info *di = (device_info *)dev; + shared_info *si = di->si; + vuint32 *regs = di->regs; + + /* lock the driver */ + AQUIRE_BEN(pd->kernel); + + /* if opened multiple times, decrement the open count and exit */ + if (di->is_open > 1) + goto unlock_and_exit; + + /* disable and clear any pending interrupts */ + disable_vbi(regs); + + /* remove interrupt handler */ + remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); + + /* delete the semaphores, ignoring any errors ('cause the owning team may have died on us) */ + delete_sem(si->vblank); + si->vblank = -1; + + /* free regs and framebuffer areas */ + unmap_device(di); + + /* clean up our shared area */ + delete_area(di->shared_area); + di->shared_area = -1; + di->si = NULL; + +unlock_and_exit: + /* mark the device available */ + di->is_open--; + /* unlock the driver */ + RELEASE_BEN(pd->kernel); + /* all done */ + return B_OK; +} + +/* ----------- + control_hook - where the real work is done +----------- */ +static status_t +control_hook (void* dev, uint32 msg, void *buf, size_t len) { + device_info *di = (device_info *)dev; + status_t result = B_DEV_INVALID_IOCTL; + + switch (msg) { + /* the only PUBLIC ioctl */ + case B_GET_ACCELERANT_SIGNATURE: { + char *sig = (char *)buf; + strcpy(sig, current_settings.accelerant); + result = B_OK; + } break; + + /* PRIVATE ioctl from here on */ + case NV_GET_PRIVATE_DATA: { + nv_get_private_data *gpd = (nv_get_private_data *)buf; + if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { + gpd->shared_info_area = di->shared_area; + result = B_OK; + } + } break; + case NV_GET_PCI: { + nv_get_set_pci *gsp = (nv_get_set_pci *)buf; + if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { + pci_info *pcii = &(di->pcii); + gsp->value = get_pci(gsp->offset, gsp->size); + result = B_OK; + } + } break; + case NV_SET_PCI: { + nv_get_set_pci *gsp = (nv_get_set_pci *)buf; + if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { + pci_info *pcii = &(di->pcii); + set_pci(gsp->offset, gsp->size, gsp->value); + result = B_OK; + } + } break; + case NV_DEVICE_NAME: { // apsed + nv_device_name *dn = (nv_device_name *)buf; + if (dn->magic == NV_PRIVATE_DATA_MAGIC) { + strcpy(dn->name, di->name); + result = B_OK; + } + } break; + case NV_RUN_INTERRUPTS: { + nv_set_bool_state *ri = (nv_set_bool_state *)buf; + if (ri->magic == NV_PRIVATE_DATA_MAGIC) { + vuint32 *regs = di->regs; + if (ri->do_it) { + enable_vbi(regs); + } else { + disable_vbi(regs); + } + result = B_OK; + } + } break; + } + return result; +} +