diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index 4a1d9ef59b..1982d9b390 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -549,8 +549,8 @@ struct intel_free_graphics_memory { #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_NORTH_PIPE_AND_PORT) #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_NORTH_PIPE_AND_PORT) -#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) -#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_DISPLAY_A_PIPE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_DISPLAY_B_PIPE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) // Cougar Point transcoder pipe selection #define PORT_TRANS_A_SEL_CPT 0 @@ -668,7 +668,7 @@ struct intel_free_graphics_memory { #define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL) // reserved on A -#define INTEL_DISPLAY_A_PIPE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) +#define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL) // i965 and up only @@ -676,7 +676,7 @@ struct intel_free_graphics_memory { #define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL) -#define INTEL_DISPLAY_B_PIPE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) +#define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL) // i965 and up only diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp b/src/add-ons/accelerants/intel_extreme/Pipes.cpp index 92c5ee9963..200d435ecb 100644 --- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp +++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp @@ -209,26 +209,22 @@ Pipe::ConfigureTimings(display_mode* target, bool hardware) | ((uint32)target->timing.v_sync_start - 1)); } - // XXX: Is it ok to do these on non-digital? - - write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0); - - // Set the image size for both pipes, just in case. - write32(INTEL_DISPLAY_A_IMAGE_SIZE, - ((uint32)(target->virtual_width - 1) << 16) - | ((uint32)target->virtual_height - 1)); - write32(INTEL_DISPLAY_B_IMAGE_SIZE, - ((uint32)(target->virtual_width - 1) << 16) - | ((uint32)target->virtual_height - 1)); - write32(INTEL_DISPLAY_A_PIPE_SIZE + fPipeOffset, - ((uint32)(target->timing.v_display - 1) << 16) - | ((uint32)target->timing.h_display - 1)); + ((uint32)(target->timing.h_display - 1) << 16) + | ((uint32)target->timing.v_display - 1)); - // This is useful for debugging: it sets the border to red, so you - // can see what is border and what is porch (black area around the - // sync) - //write32(INTEL_DISPLAY_A_RED + fPipeOffset, 0x00FF0000); + // Set the plane size as well while we're at it (this is independant, we + // could have a larger plane and scroll through it). + if (gInfo->shared_info->device_type.Generation() > 4) { + // This is "reserved" on G45 and below. + write32(INTEL_DISPLAY_A_IMAGE_SIZE + fPipeOffset, + ((uint32)(target->virtual_width - 1) << 16) + | ((uint32)target->virtual_height - 1)); + } + + // Since we set the plane to be the same size as the display, we can just + // show it starting at top-left. + write32(INTEL_DISPLAY_A_POS + fPipeOffset, 0); if (fHasTranscoder) _ConfigureTranscoder(target); diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp index 1e7072102b..24bce5c5a7 100644 --- a/src/add-ons/accelerants/intel_extreme/mode.cpp +++ b/src/add-ons/accelerants/intel_extreme/mode.cpp @@ -40,165 +40,6 @@ #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) -#if 0 -// This hack needs to die. Leaving in for a little while -// incase we *really* need it. -static void -retrieve_current_mode(display_mode& mode, uint32 pllRegister) -{ - uint32 pll = read32(pllRegister); - uint32 pllDivisor; - uint32 hTotalRegister; - uint32 vTotalRegister; - uint32 hSyncRegister; - uint32 vSyncRegister; - uint32 imageSizeRegister; - uint32 controlRegister; - - if (pllRegister == INTEL_DISPLAY_A_PLL) { - pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0 - ? INTEL_DISPLAY_A_PLL_DIVISOR_1 : INTEL_DISPLAY_A_PLL_DIVISOR_0); - - hTotalRegister = INTEL_DISPLAY_A_HTOTAL; - vTotalRegister = INTEL_DISPLAY_A_VTOTAL; - hSyncRegister = INTEL_DISPLAY_A_HSYNC; - vSyncRegister = INTEL_DISPLAY_A_VSYNC; - imageSizeRegister = INTEL_DISPLAY_A_IMAGE_SIZE; - controlRegister = INTEL_DISPLAY_A_CONTROL; - } else if (pllRegister == INTEL_DISPLAY_B_PLL) { - pllDivisor = read32((pll & DISPLAY_PLL_DIVISOR_1) != 0 - ? INTEL_DISPLAY_B_PLL_DIVISOR_1 : INTEL_DISPLAY_B_PLL_DIVISOR_0); - - hTotalRegister = INTEL_DISPLAY_B_HTOTAL; - vTotalRegister = INTEL_DISPLAY_B_VTOTAL; - hSyncRegister = INTEL_DISPLAY_B_HSYNC; - vSyncRegister = INTEL_DISPLAY_B_VSYNC; - imageSizeRegister = INTEL_DISPLAY_B_IMAGE_SIZE; - controlRegister = INTEL_DISPLAY_B_CONTROL; - } else { - ERROR("%s: PLL not supported\n", __func__); - return; - } - - pll_divisors divisors; - if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { - divisors.m1 = 0; - divisors.m2 = (pllDivisor & DISPLAY_PLL_IGD_M2_DIVISOR_MASK) - >> DISPLAY_PLL_M2_DIVISOR_SHIFT; - divisors.n = ((pllDivisor & DISPLAY_PLL_IGD_N_DIVISOR_MASK) - >> DISPLAY_PLL_N_DIVISOR_SHIFT) - 1; - } else { - divisors.m1 = (pllDivisor & DISPLAY_PLL_M1_DIVISOR_MASK) - >> DISPLAY_PLL_M1_DIVISOR_SHIFT; - divisors.m2 = (pllDivisor & DISPLAY_PLL_M2_DIVISOR_MASK) - >> DISPLAY_PLL_M2_DIVISOR_SHIFT; - divisors.n = (pllDivisor & DISPLAY_PLL_N_DIVISOR_MASK) - >> DISPLAY_PLL_N_DIVISOR_SHIFT; - } - - pll_limits limits; - get_pll_limits(&limits, false); - // TODO: Detect LVDS connector vs assume no - - if (gInfo->shared_info->device_type.Generation() >= 3) { - - if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { - divisors.post1 = (pll & DISPLAY_PLL_IGD_POST1_DIVISOR_MASK) - >> DISPLAY_PLL_IGD_POST1_DIVISOR_SHIFT; - } else { - divisors.post1 = (pll & DISPLAY_PLL_9xx_POST1_DIVISOR_MASK) - >> DISPLAY_PLL_POST1_DIVISOR_SHIFT; - } - - if (pllRegister == INTEL_DISPLAY_B_PLL - && !gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) { - // TODO: Fix this? Need to support dual channel LVDS. - divisors.post2 = LVDS_POST2_RATE_SLOW; - } else { - if ((pll & DISPLAY_PLL_DIVIDE_HIGH) != 0) - divisors.post2 = limits.max.post2; - else - divisors.post2 = limits.min.post2; - } - } else { - // 8xx - divisors.post1 = (pll & DISPLAY_PLL_POST1_DIVISOR_MASK) - >> DISPLAY_PLL_POST1_DIVISOR_SHIFT; - - if ((pll & DISPLAY_PLL_DIVIDE_4X) != 0) - divisors.post2 = limits.max.post2; - else - divisors.post2 = limits.min.post2; - } - - divisors.m = 5 * divisors.m1 + divisors.m2; - divisors.post = divisors.post1 * divisors.post2; - - float referenceClock - = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; - float pixelClock - = ((referenceClock * divisors.m) / divisors.n) / divisors.post; - - // timing - - mode.timing.pixel_clock = uint32(pixelClock * 1000); - mode.timing.flags = 0; - - uint32 value = read32(hTotalRegister); - mode.timing.h_total = (value >> 16) + 1; - mode.timing.h_display = (value & 0xffff) + 1; - - value = read32(hSyncRegister); - mode.timing.h_sync_end = (value >> 16) + 1; - mode.timing.h_sync_start = (value & 0xffff) + 1; - - value = read32(vTotalRegister); - mode.timing.v_total = (value >> 16) + 1; - mode.timing.v_display = (value & 0xffff) + 1; - - value = read32(vSyncRegister); - mode.timing.v_sync_end = (value >> 16) + 1; - mode.timing.v_sync_start = (value & 0xffff) + 1; - - // image size and color space - - value = read32(imageSizeRegister); - mode.virtual_width = (value >> 16) + 1; - mode.virtual_height = (value & 0xffff) + 1; - - // using virtual size based on image size is the 'proper' way to do it, - // however the bios appears to be suggesting scaling or somesuch, so ignore - // the proper virtual dimension for now if they'd suggest a smaller size. - if (mode.virtual_width < mode.timing.h_display) - mode.virtual_width = mode.timing.h_display; - if (mode.virtual_height < mode.timing.v_display) - mode.virtual_height = mode.timing.v_display; - - value = read32(controlRegister); - switch (value & DISPLAY_CONTROL_COLOR_MASK) { - case DISPLAY_CONTROL_RGB32: - default: - mode.space = B_RGB32; - break; - case DISPLAY_CONTROL_RGB16: - mode.space = B_RGB16; - break; - case DISPLAY_CONTROL_RGB15: - mode.space = B_RGB15; - break; - case DISPLAY_CONTROL_CMAP8: - mode.space = B_CMAP8; - break; - } - - mode.h_display_start = 0; - mode.v_display_start = 0; - mode.flags = B_8_BIT_DAC | B_HARDWARE_CURSOR | B_PARALLEL_ACCESS - | B_DPMS | B_SUPPORTS_OVERLAYS; -} -#endif - - static void get_color_space_format(const display_mode &mode, uint32 &colorMode, uint32 &bytesPerRow, uint32 &bitsPerPixel)