From 2bf16c66b59699a2d162be5154aab68cbd12fe38 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Sun, 3 Jan 2016 15:21:20 -0600 Subject: [PATCH] intel_extreme: Fix pll divisors on gen 3 cards * Likely a regression from my card generation rework --- src/add-ons/accelerants/intel_extreme/Pipes.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp b/src/add-ons/accelerants/intel_extreme/Pipes.cpp index 8a010fbfc7..18fea97423 100644 --- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp +++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp @@ -241,9 +241,7 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock, uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags; - if (gInfo->shared_info->device_type.Generation() >= 4 - || gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { - + if (gInfo->shared_info->device_type.Generation() >= 3) { // post1 divisor << 1 , 1-8 if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_PIN)) { pll |= ((1 << (divisors.post1 - 1)) @@ -269,6 +267,7 @@ Pipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock, pll |= DISPLAY_PLL_2X_CLOCK; + // TODO: Is this supposed to be DISPLAY_PLL_IGD_POST1_DIVISOR_MASK?? if (divisors.post1 > 2) { pll |= ((divisors.post1 - 2) << DISPLAY_PLL_POST1_DIVISOR_SHIFT) & DISPLAY_PLL_POST1_DIVISOR_MASK;