From 2d004e3e89b98b25cdd710f0f92a33f5cee7a10d Mon Sep 17 00:00:00 2001 From: Michael Lotz Date: Sun, 16 Oct 2011 14:38:44 +0000 Subject: [PATCH] Fix register definition for image size registers. They are in the north pipe control block. Doesn't matter on (G)MCH (they are the same register block tehre) but fixes mode setting on PCH again. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42862 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- headers/private/graphics/intel_extreme/intel_extreme.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index 2d90d88f18..a5e8f86bf0 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -396,14 +396,15 @@ struct intel_free_graphics_memory { #define INTEL_DISPLAY_A_VTOTAL (0x000c | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_A_VBLANK (0x0010 | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_A_VSYNC (0x0014 | REGS_SOUTH_TRANSCODER_PORT) -#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_B_HTOTAL (0x1000 | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_B_HBLANK (0x1004 | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_B_HSYNC (0x1008 | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_B_VTOTAL (0x100c | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_DISPLAY_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) -#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) + +#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c | REGS_NORTH_PIPE_AND_PORT) #define INTEL_DISPLAY_B_DIGITAL_PORT (0x1140 | REGS_SOUTH_TRANSCODER_PORT)