Work in progress while trying to fix ticket #2227:
- Added skeleton code for setting device mode. - Next, figure out which bits to set! git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@26862 a95241bf-73f2-0310-859d-f6bbb57e9c96
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@@ -40,7 +40,6 @@ jmicron_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device,
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if (!(val & (1 << 30))) {
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if (!(val & (1 << 30))) {
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// IDE controller at function 1 is configured in IDE mode (as opposed
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// IDE controller at function 1 is configured in IDE mode (as opposed
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// to AHCI or RAID). So we want to handle it.
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// to AHCI or RAID). So we want to handle it.
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dprintf("jmicron_fixup_ahci: PATA controller in IDE mode.\n");
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dprintf("jmicron_fixup_ahci: PATA controller in IDE mode.\n");
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// TODO(bga): It seems that with recent BIOS revisions no special code
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// TODO(bga): It seems that with recent BIOS revisions no special code
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@@ -60,6 +59,18 @@ jmicron_fixup_ahci(PCI *pci, int domain, uint8 bus, uint8 device,
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// Maybe fixing this would be as simple as changing the device class to
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// Maybe fixing this would be as simple as changing the device class to
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// Serial ATA Controller instead of IDE Controller (even in AHCI mode
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// Serial ATA Controller instead of IDE Controller (even in AHCI mode
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// it reports being a standard IDE controller)?
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// it reports being a standard IDE controller)?
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dprintf("jmicron_fixup_ahci: PATA controller in AHCI or RAID mode.\n");
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// Read controller control register (0x40). This should contain all the
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// bits we need to change.
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val = pci->ReadConfig(domain, bus, device, function, 0x40, 4);
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dprintf("jmicron_fixup_ahci: Register 0x40 : %0x%08lx\n", val);
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// TODO(bga): Do some bit shuffling here to set the controller to split
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// mode. Right now, the write operation bellow is a no-op.
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// Write controller control register (0x40).
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pci->WriteConfig(domain, bus, device, 1, 0x40, 4, val);
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}
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}
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}
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}
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