diff --git a/src/add-ons/accelerants/via/SetDisplayMode.c b/src/add-ons/accelerants/via/SetDisplayMode.c
index d68f40ea16..4de00a8236 100644
--- a/src/add-ons/accelerants/via/SetDisplayMode.c
+++ b/src/add-ons/accelerants/via/SetDisplayMode.c
@@ -204,7 +204,7 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
 			si->interlaced_tv_mode = true;
 */
 		/*set the display(s) pitches*/
-//		head1_set_display_pitch ();
+		head1_set_display_pitch ();
 		//fixme: seperate for real dualhead modes:
 		//we need a secondary si->fbc!
 //		head2_set_display_pitch ();
@@ -217,11 +217,11 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
 		{
 		case DUALHEAD_ON:
 		case DUALHEAD_SWITCH:
-//			head1_set_display_start(startadd,colour_depth1);
+			head1_set_display_start(startadd,colour_depth1);
 //			head2_set_display_start(startadd_right,colour_depth2);
 			break;
 		case DUALHEAD_CLONE:
-//			head1_set_display_start(startadd,colour_depth1);
+			head1_set_display_start(startadd,colour_depth1);
 //			head2_set_display_start(startadd,colour_depth2);
 			break;
 		}
@@ -291,7 +291,7 @@ status = B_OK;
 //		head1_mode(colour_mode,1.0);
 
 		/* set the display pitch */
-//		head1_set_display_pitch();
+		head1_set_display_pitch();
 
 		/* tell the card what memory to display */
 		head1_set_display_start(startadd,colour_depth1);
diff --git a/src/add-ons/accelerants/via/engine/crtc.c b/src/add-ons/accelerants/via/engine/crtc.c
index 9a2c0b446b..82a3d6f56a 100644
--- a/src/add-ons/accelerants/via/engine/crtc.c
+++ b/src/add-ons/accelerants/via/engine/crtc.c
@@ -578,21 +578,19 @@ status_t eng_crtc_dpms_fetch(bool *display, bool *h, bool *v)
 
 status_t eng_crtc_set_display_pitch() 
 {
-	uint32 offset;
+	uint16 offset;
 
 	LOG(4,("CRTC: setting card pitch (offset between lines)\n"));
 
 	/* figure out offset value hardware needs */
-	offset = si->fbc.bytes_per_row / 8;
+	offset = si->fbc.bytes_per_row >> 3;
 
 	LOG(2,("CRTC: offset register set to: $%04x\n", offset));
 
-	/* enable access to primary head */
-	set_crtc_owner(0);
-
 	/* program the card */
+	// fixme: lowbyte register may not be programmed with value 0xff. Prevent that...
 	CRTCW(PITCHL, (offset & 0x00ff));
-	CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3)));
+	//fixme: there is a high-byte register somewhere that needs to be pgm'd!!!
 
 	return B_OK;
 }