From 32807945aae9698c87f0a56f95f73b16b01a9827 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Tue, 17 Nov 2015 20:12:41 -0600 Subject: [PATCH] intel_extreme: Some basic pipe cleanup --- .../accelerants/intel_extreme/DisplayPipe.cpp | 28 +++++++++---------- .../accelerants/intel_extreme/mode.cpp | 8 +++--- 2 files changed, 17 insertions(+), 19 deletions(-) diff --git a/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp b/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp index 2876c7aa7f..568dce06ad 100644 --- a/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp +++ b/src/add-ons/accelerants/intel_extreme/DisplayPipe.cpp @@ -94,9 +94,6 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress) return; } - // Wait for the clocks to stabilize - spin(150); - // update timing (fPipeBase bumps the DISPLAY_A to B when needed) write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_HTOTAL), ((uint32)(target->timing.h_total - 1) << 16) @@ -118,24 +115,24 @@ DisplayPipe::Enable(display_mode* target, addr_t portAddress) ((uint32)(target->timing.v_sync_end - 1) << 16) | ((uint32)target->timing.v_sync_start - 1)); + // XXX: Is it ok to do these on non-digital? write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_POS), 0); + write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE), + ((uint32)(target->virtual_width - 1) << 16) + | ((uint32)target->virtual_height - 1)); + + write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_PIPE_SIZE), + ((uint32)(target->timing.v_display - 1) << 16) + | ((uint32)target->timing.h_display - 1)); // This is useful for debugging: it sets the border to red, so you // can see what is border and what is porch (black area around the // sync) //write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_RED), 0x00FF0000); - // TODO: Review these - write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_IMAGE_SIZE), - ((uint32)(target->virtual_width - 1) << 16) - | ((uint32)target->virtual_height - 1)); - write32(fPipeBase + REGISTER_REGISTER(INTEL_DISPLAY_A_PIPE_SIZE), - ((uint32)(target->timing.v_display - 1) << 16) - | ((uint32)target->timing.h_display - 1)); - - write32(portAddress, (read32(portAddress) - & ~(DISPLAY_MONITOR_POLARITY_MASK - | DISPLAY_MONITOR_VGA_POLARITY)) + // XXX: Is it ok to do this on non-analog? + write32(portAddress, (read32(portAddress) & ~(DISPLAY_MONITOR_POLARITY_MASK + | DISPLAY_MONITOR_VGA_POLARITY)) | ((target->timing.flags & B_POSITIVE_HSYNC) != 0 ? DISPLAY_MONITOR_POSITIVE_HSYNC : 0) | ((target->timing.flags & B_POSITIVE_VSYNC) != 0 @@ -235,7 +232,8 @@ DisplayPipe::ConfigureTimings(const pll_divisors& divisors, uint32 pixelClock, pll |= DISPLAY_PLL_POST1_DIVIDE_2; } - write32(pllControl, pll); + // Allow the PLL to warm up by masking its bit. + write32(pllControl, pll & ~DISPLAY_PLL_NO_VGA_CONTROL); read32(pllControl); spin(150); write32(pllControl, pll); diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp index a32795d02a..b7ce22b149 100644 --- a/src/add-ons/accelerants/intel_extreme/mode.cpp +++ b/src/add-ons/accelerants/intel_extreme/mode.cpp @@ -622,9 +622,6 @@ if (first) { TRACE("%s: Port configuration completed successfully!\n", __func__); - // RIP DIGITAL / LVDS (strange..) - // RIP ANALOG - // We set the same color mode across all pipes program_pipe_color_modes(colorMode); @@ -656,7 +653,10 @@ intel_get_display_mode(display_mode* _currentMode) { CALLED(); - retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL); + *_currentMode = gInfo->shared_info->current_mode; + + // This seems unreliable. We should always know the current_mode + //retrieve_current_mode(*_currentMode, INTEL_DISPLAY_A_PLL); return B_OK; }