x86: Implement PAT support for memory type configuration.

Using the page attribute table to set the memory type on a per page
mapping basis is the more modern and flexible approach to physical
memory type handling compared to using MTRRs.

Most of the needed infrastructure was already in place, as setting the
page table entry attributes was already done for uncachable and
write-back memory types. Using the PAT now also allows to set the last
remaining memory type of write-combining through the PTE flags. The PAT
is configured to have entry 4 mean write-combining and the PAT bit in
the PTE is set to point to that.

When PAT is supported and not disabled, MTRRs are completely ignored
and left as set up by the system firmware, where the basic uncachable
and RAM ranges are supposed to be set up. These configurations are then
overridden by the PTE flags as needed.

Change-Id: I0a74b3fc7d3ba9fa384251290ce41621b69d3a02
Reviewed-on: https://review.haiku-os.org/c/haiku/+/8340
Reviewed-by: waddlesplash <[email protected]>

headers/private/kernel/arch/x86/arch_cpu.h

@@ -57,6 +57,7 @@
 #define IA32_MSR_MTRR_DEFAULT_TYPE		0x2ff
 #define IA32_MSR_MTRR_PHYSICAL_BASE_0	0x200
 #define IA32_MSR_MTRR_PHYSICAL_MASK_0	0x201
+#define IA32_MSR_PAT					0x277
 
 // MSR SPEC CTRL bits
 #define IA32_MSR_SPEC_CTRL_IBRS			(1 << 0)
@@ -177,6 +178,16 @@
 #define	IA32_HWP_REQUEST_MAXIMUM_VALID					(1ULL << 62)
 #define	IA32_HWP_REQUEST_MINIMUM_VALID					(1ULL << 63)
 
+// IA32_MSR_PAT bits
+#define IA32_MSR_PAT_ENTRY_MASK							0x7ULL
+#define IA32_MSR_PAT_ENTRY_SHIFT(x)						(x * 8)
+#define IA32_MSR_PAT_TYPE_UNCACHEABLE					0x0ULL
+#define IA32_MSR_PAT_TYPE_WRITE_COMBINING				0x1ULL
+#define IA32_MSR_PAT_TYPE_WRITE_THROUGH					0x4ULL
+#define IA32_MSR_PAT_TYPE_WRITE_PROTECTED				0x5ULL
+#define IA32_MSR_PAT_TYPE_WRITE_BACK					0x6ULL
+#define IA32_MSR_PAT_TYPE_UNCACHED						0x7ULL
+
 // x86 features from cpuid eax 1, edx register
 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-5)
 #define IA32_FEATURE_FPU	(1 << 0) // x87 fpu
@@ -668,6 +679,7 @@ void x86_set_mtrrs(uint8 defaultType, const x86_mtrr_info* infos,
 	uint32 count);
 void x86_init_fpu();
 bool x86_check_feature(uint32 feature, enum x86_feature_type type);
+bool x86_use_pat();
 void* x86_get_double_fault_stack(int32 cpu, size_t* _size);
 int32 x86_double_fault_get_cpu(void);