diff --git a/headers/private/graphics/matrox/DriverInterface.h b/headers/private/graphics/matrox/DriverInterface.h new file mode 100644 index 0000000000..eefb2d8605 --- /dev/null +++ b/headers/private/graphics/matrox/DriverInterface.h @@ -0,0 +1,281 @@ +/* + Copyright 1999, Be Incorporated. All Rights Reserved. + This file may be used under the terms of the Be Sample Code License. + + Other authors: + Mark Watson; + Apsed; + Rudolf Cornelissen 10/2002. +*/ + +#ifndef DRIVERINTERFACE_H +#define DRIVERINTERFACE_H + +#include +#include "video_overlay.h" +#include +#include +#include + +#define DRIVER_PREFIX "mga" // apsed + +/* + Internal driver state (also for sharing info between driver and accelerant) +*/ +#if defined(__cplusplus) +extern "C" { +#endif + +typedef struct { + sem_id sem; + int32 ben; +} benaphore; + +#define INIT_BEN(x) x.sem = create_sem(0, "G400 "#x" benaphore"); x.ben = 0; +#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); +#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); +#define DELETE_BEN(x) delete_sem(x.sem); + + +#define GX00_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ + +/*dualhead extensions to flags*/ +#define DUALHEAD_OFF (0<<6) +#define DUALHEAD_CLONE (1<<6) +#define DUALHEAD_ON (2<<6) +#define DUALHEAD_SWITCH (3<<6) +#define DUALHEAD_BITS (3<<6) +#define DUALHEAD_CAPABLE (1<<8) +#define TV_BITS (3<<9) +#define TV_MON (0<<9 +#define TV_PAL (1<<9) +#define TV_NTSC (2<<9) +#define TV_CAPABLE (1<<11) + +#define SKD_MOVE_CURSOR 0x00000001 +#define SKD_PROGRAM_CLUT 0x00000002 +#define SKD_SET_START_ADDR 0x00000004 +#define SKD_SET_CURSOR 0x00000008 +#define SKD_HANDLER_INSTALLED 0x80000000 + +enum { + GX00_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, + GX00_GET_PCI, + GX00_SET_PCI, + GX00_DEVICE_NAME, + GX00_RUN_INTERRUPTS +}; + +/* max. number of overlay buffers */ +#define MAXBUFFERS 3 +/* max. pixelclock speed the BES supports */ +#define BESMAXSPEED 135000 + +/* internal used info on overlay buffers */ +typedef struct +{ + uint16 slopspace; + uint32 size; +} int_buf_info; + +typedef struct settings { // apsed, see comments in mga.settings + // for driver + char accelerant[B_FILE_NAME_LENGTH]; + bool dumprom; + // for accelerant + uint32 logmask; + uint32 memory; + bool usebios; + bool hardcursor; +} settings; + +/*shared info*/ +typedef struct { + /*a few ID things*/ + uint16 vendor_id; /* PCI vendor ID, from pci_info */ + uint16 device_id; /* PCI device ID, from pci_info */ + uint8 revision; /* PCI device revsion, from pci_info */ + + /* bug workaround for 4.5.0 */ + uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ + uint32 * clone_bugfix_regs; + + /*memory mappings*/ + area_id regs_area; /* Kernel's area_id for the memory mapped registers. + It will be cloned into the accelerant's address + space. */ + + area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ + area_id pseudo_dma_area; /* Pseudo dma area_id. Shared by all teams. */ + area_id dma_buffer_area; /* Area assigned for dma*/ + + void *framebuffer; /* As viewed from virtual memory */ + void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ + + void *pseudo_dma; /* As viewed from virtual memory */ + + void *dma_buffer; /* buffer for dma*/ + void *dma_buffer_pci; /* buffer for dma - from PCI bus*/ + + /*screenmode list*/ + area_id mode_area; /* Contains the list of display modes the driver supports */ + uint32 mode_count; /* Number of display modes in the list */ + + /*flags - used by driver*/ + uint32 flags; + + /*vblank semaphore*/ + sem_id vblank; /* The vertical blank semaphore. Ownership will be + transfered to the team opening the device first */ + /*cursor information*/ + struct { + uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ + uint16 hot_y; /* is 0,0 */ + uint16 x; /* The location of the cursor hot spot on the */ + uint16 y; /* desktop */ + uint16 width; /* Width and height of the cursor shape (always 16!) */ + uint16 height; + bool is_visible; /* Is the cursor currently displayed? */ + }cursor; + + /*colour lookup table*/ + uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ + + /*more display mode stuff*/ + display_mode dm; /* current display mode configuration */ + + /*frame buffer config - for BDirectScreen*/ + frame_buffer_config fbc; /* bytes_per_row and start of frame buffer */ + + /*acceleration engine*/ + struct { + uint32 count; /* last dwgsync slot used */ + uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ + benaphore lock; /* for serializing access to the acceleration engine */ + } engine; + + /* card info - information gathered from PINS (and other sources) */ + enum + { // card_type in order of date of MGA chip design + MILL=0, + MYST, + MIL2, + G100, + G200, + G400, + G400MAX, + G450, + G550 + }; + struct + { + /*specialised registers for initialisation*/ + //will be deleted, will be replaced by new Pins implementation: + //these are nolonger used by G100. + uint32 mem_ctl; + uint32 mem_type; + uint8 membuf; /*memory buffer type*/ + uint32 mem_rd; + uint32 mem_rfhcnt; + + /*temporary extra info for G450*/ + //will be deleted, will be replaced by new Pins implementation: + uint32 option; + uint32 option2; + uint32 option4; + uint32 maccess; + + /* general card information */ + uint32 card_type; /* see card_type enum above */ + status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ + bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ + + /* newly implemented PINS: will replace most of the above.. */ + float f_ref; /* PLL reference-oscillator frequency (Mhz) */ + uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ + uint32 min_system_vco; + uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ + uint32 min_pixel_vco; + uint32 max_video_vco; /* dac2, maven PLL VCO limits (Mhz) */ + uint32 min_video_vco; + uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ + uint32 std_engine_clock_dh; + uint32 max_dac1_clock; /* dac1 limits (Mhz) */ + uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ + uint32 max_dac1_clock_16; + uint32 max_dac1_clock_24; + uint32 max_dac1_clock_32; + uint32 max_dac1_clock_32dh; + uint32 max_dac2_clock; /* dac2 limits (Mhz) */ + uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ + uint32 max_dac2_clock_16; + uint32 max_dac2_clock_24; + uint32 max_dac2_clock_32; + uint32 max_dac2_clock_32dh; + bool secondary_head; /* presence of functions */ + bool secondary_tvout; + bool primary_dvi; + bool secondary_dvi; + uint32 memory_size; /* memory (Mb) */ + uint32 mctlwtst_reg; /* memory control waitstate register */ + uint32 option_reg; /* option register */ + uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ + uint8 v3_mem_type; /* pins v3 memory type info */ + } ps; + + /*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/ + uint8 rom_mirror[32768]; + + /*CRTC delay -> used in timing for MAVEN, depending on which CRTC is driving it*/ + uint8 crtc_delay; + + /* apsed: some configuration settings from ~/config/settings/kernel/drivers/mga.settings if exists */ + settings settings; + + struct + { + overlay_buffer myBuffer[MAXBUFFERS];/* scaler input buffers */ + int_buf_info myBufInfo[MAXBUFFERS]; /* extra info on scaler input buffers */ + overlay_token myToken; /* scaler is free/in use */ + benaphore lock; /* for creating buffers and aquiring overlay unit routines */ + } overlay; + +} shared_info; + +/* Read or write a value in PCI configuration space */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + uint32 offset; /* Offset to read/write */ + uint32 size; /* Number of bytes to transfer */ + uint32 value; /* The value read or written */ +} gx00_get_set_pci; + +/* Set some boolean condition (like enabling or disabling interrupts) */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + bool do_it; /* state to set */ +} gx00_set_bool_state; + +/* Retrieve the area_id of the kernel/accelerant shared info */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + area_id shared_info_area; /* area_id containing the shared information */ +} gx00_get_private_data; + +/* Retrieve the device name. Usefull for when we have a file handle, but want +to know the device name (like when we are cloning the accelerant) */ +typedef struct { + uint32 magic; /* magic number to make sure the caller groks us */ + char *name; /* The name of the device, less the /dev root */ +} gx00_device_name; + +enum { + GX00_WAIT_FOR_VBLANK = (1 << 0) +}; + +#if defined(__cplusplus) +} +#endif + + +#endif diff --git a/headers/private/graphics/matrox/mga_macros.h b/headers/private/graphics/matrox/mga_macros.h new file mode 100644 index 0000000000..f460574a36 --- /dev/null +++ b/headers/private/graphics/matrox/mga_macros.h @@ -0,0 +1,286 @@ +/* MGA registers definitions and macros for access to */ + +/* apsed : merged mga_macro.h and mga_regs.c with #define for speed */ + +/* PCI_config_space */ +#define MGACFG_DEVID 0x00 +#define MGACFG_DEVCTRL 0x04 +#define MGACFG_CLASS 0x08 +#define MGACFG_HEADER 0x0c +#define MGACFG_MGABASE2 0x10 +#define MGACFG_MGABASE1 0x14 +#define MGACFG_MGABASE3 0x18 // >= MYST +#define MGACFG_SUBSYSIDR 0x2c // >= MYST +#define MGACFG_ROMBASE 0x30 +#define MGACFG_CAP_PTR 0x34 // >= MIL2 +#define MGACFG_INTCTRL 0x3c +#define MGACFG_OPTION 0x40 +#define MGACFG_MGA_INDEX 0x44 +#define MGACFG_MGA_DATA 0x48 +#define MGACFG_SUBSYSIDW 0x4c // >= MYST +#define MGACFG_OPTION2 0x50 // >= G100 +#define MGACFG_OPTION3 0x54 // >= G400 +#define MGACFG_OPTION4 0x58 // >= G400 +#define MGACFG_PM_IDENT 0xdc // >= G100 +#define MGACFG_PM_CSR 0xe0 // >= G100 +#define MGACFG_AGP_IDENT 0xf0 // >= MIL2 +#define MGACFG_AGP_STS 0xf4 // >= MIL2 +#define MGACFG_AGP_CMD 0xf8 // >= MIL2 + +/*VGA registers - these are byte wide*/ +#define MGAVGA_ATTR_I 0x1FC0 // apsed as SEQ +#define MGAVGA_ATTR_D 0x1FC1 // apsed as SEQ +#define MGAVGA_MISCW 0x1FC2 +#define MGAVGA_SEQ_I 0x1FC4 +#define MGAVGA_SEQ_D 0x1FC5 +#define MGAVGA_DACSTAT 0x1FC7 +#define MGAVGA_FEATR 0x1FCA +#define MGAVGA_MISCR 0x1FCC +#define MGAVGA_GCTL_I 0x1FCE +#define MGAVGA_GCTL_D 0x1FCF +#define MGAVGA_CRTC_I 0x1FD4 +#define MGAVGA_CRTC_D 0x1FD5 +#define MGAVGA_INSTS1 0x1FDA +#define MGAVGA_FEATW 0x1FDA +#define MGAVGA_CRTCEXT_I 0x1FDE +#define MGAVGA_CRTCEXT_D 0x1FDF + +/*DAC registers (>= g100) */ +#define MGADAC_PALWTADD 0x3C00 +#define MGADAC_PALDATA 0x3C01 +#define MGADAC_PIXRDMSK 0x3C02 +#define MGADAC_PALRDADD 0x3C03 +#define MGADAC_X_DATAREG 0x3C0A +#define MGADAC_CURSPOSXL 0x3C0C +#define MGADAC_CURSPOSXH 0x3C0D +#define MGADAC_CURSPOSYL 0x3C0E +#define MGADAC_CURSPOSYH 0x3C0F + +/*(D)AC (X) (I)ndexed registers (>= g100) */ +#define MGADXI_CURADDL 0x04 +#define MGADXI_CURADDH 0x05 +#define MGADXI_CURCTRL 0x06 +#define MGADXI_CURCOL0RED 0x08 +#define MGADXI_CURCOL0GREEN 0x09 +#define MGADXI_CURCOL0BLUE 0x0A +#define MGADXI_CURCOL1RED 0x0C +#define MGADXI_CURCOL1GREEN 0x0D +#define MGADXI_CURCOL1BLUE 0x0E +#define MGADXI_CURCOL2RED 0x10 +#define MGADXI_CURCOL2GREEN 0x11 +#define MGADXI_CURCOL2BLUE 0x12 +#define MGADXI_VREFCTRL 0x18 +#define MGADXI_MULCTRL 0x19 +#define MGADXI_PIXCLKCTRL 0x1A +#define MGADXI_GENCTRL 0x1D +#define MGADXI_MISCCTRL 0x1E +#define MGADXI_PANELMODE 0x1F +#define MGADXI_MAFCDEL 0x20 +#define MGADXI_GENIOCTRL 0x2A +#define MGADXI_GENIODATA 0x2B +#define MGADXI_SYSPLLM 0x2C +#define MGADXI_SYSPLLN 0x2D +#define MGADXI_SYSPLLP 0x2E +#define MGADXI_SYSPLLSTAT 0x2F +#define MGADXI_ZOOMCTRL 0x38 +#define MGADXI_SENSETEST 0x3A +#define MGADXI_CRCREML 0x3C +#define MGADXI_CRCREMH 0x3D +#define MGADXI_CRCBITSEL 0x3E +#define MGADXI_COLMSK 0x40 +#define MGADXI_COLKEY 0x42 +#define MGADXI_PIXPLLAM 0x44 +#define MGADXI_PIXPLLAN 0x45 +#define MGADXI_PIXPLLAP 0x46 +#define MGADXI_PIXPLLBM 0x48 +#define MGADXI_PIXPLLBN 0x49 +#define MGADXI_PIXPLLBP 0x4A +#define MGADXI_PIXPLLCM 0x4C +#define MGADXI_PIXPLLCN 0x4D +#define MGADXI_PIXPLLCP 0x4E +#define MGADXI_PIXPLLSTAT 0x4F +#define MGADXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/ + +//rudolf: missing registers! +/*(D)AC (X) (I)ndexed registers (>= g200) */ +#define MGADXI_KEYOPMODE 0x51 +#define MGADXI_COLMSK0RED 0x52 +#define MGADXI_COLMSK0GREEN 0x53 +#define MGADXI_COLMSK0BLUE 0x54 +#define MGADXI_COLKEY0RED 0x55 +#define MGADXI_COLKEY0GREEN 0x56 +#define MGADXI_COLKEY0BLUE 0x57 + +/*MGA 1st CRTC registers */ +#define MGACR1_VCOUNT 0x1E20 +//end rudolf. + +/*MGA 2nd CRTC registers >= ?? TODO */ +#define MGACR2_CTL 0x3C10 +#define MGACR2_HPARAM 0x3C14 +#define MGACR2_HSYNC 0x3C18 +#define MGACR2_VPARAM 0x3C1C +#define MGACR2_VSYNC 0x3C20 +#define MGACR2_PRELOAD 0x3C24 +#define MGACR2_STARTADD0 0x3C28 +#define MGACR2_OFFSET 0x3C40 +#define MGACR2_MISC 0x3C44 +#define MGACR2_VCOUNT 0x3C48 +#define MGACR2_DATACTL 0x3C4C + +/*MGA ACCeleration registers*/ +#define MGAACC_DWGCTL 0x1C00 +#define MGAACC_MACCESS 0x1C04 +#define MGAACC_MCTLWTST 0x1C08 +#define MGAACC_ZORG 0x1C0C +#define MGAACC_PLNWT 0x1C1C +#define MGAACC_BCOL 0x1C20 +#define MGAACC_FCOL 0x1C24 +#define MGAACC_XYSTRT 0x1C40 +#define MGAACC_XYEND 0x1C44 +#define MGAACC_SGN 0x1C58 +#define MGAACC_LEN 0x1C5C +#define MGAACC_AR0 0x1C60 +#define MGAACC_AR3 0x1C6C +#define MGAACC_AR5 0x1C74 +#define MGAACC_CXBNDRY 0x1C80 +#define MGAACC_FXBNDRY 0x1C84 +#define MGAACC_YDSTLEN 0x1C88 +#define MGAACC_PITCH 0x1C8C +#define MGAACC_YDST 0x1C90 +#define MGAACC_YDSTORG 0x1C94 +#define MGAACC_YTOP 0x1C98 +#define MGAACC_YBOT 0x1C9C +#define MGAACC_CXLEFT 0x1CA0 +#define MGAACC_CXRIGHT 0x1CA4 +#define MGAACC_FXLEFT 0x1CA8 +#define MGAACC_FXRIGHT 0x1CAC +#define MGAACC_STATUS 0x1E14 +#define MGAACC_ICLEAR 0x1E18 /* required for interrupt stuff */ +#define MGAACC_IEN 0x1E1C /* required for interrupt stuff */ +#define MGAACC_RST 0x1E40 +#define MGAACC_MEMRDBK 0x1E44 +#define MGAACC_OPMODE 0x1E54 +#define MGAACC_PRIMADDRESS 0x1E58 +#define MGAACC_PRIMEND 0x1E5C +#define MGAACC_TEXORG 0x2C24 // >= G100 +#define MGAACC_DWGSYNC 0x2C4C // >= G200 +#define MGAACC_TEXORG1 0x2CA4 // >= G200 +#define MGAACC_TEXORG2 0x2CA8 // >= G200 +#define MGAACC_TEXORG3 0x2CAC // >= G200 +#define MGAACC_TEXORG4 0x2CB0 // >= G200 +#define MGAACC_SRCORG 0x2CB4 // >= G200 +#define MGAACC_DSTORG 0x2CB8 // >= G200 + +/*MGA BES (Back End Scaler) registers >= TODO */ +#define MGABES_A1ORG 0x3D00 +#define MGABES_A2ORG 0x3D04 +#define MGABES_B1ORG 0x3D08 +#define MGABES_B2ORG 0x3D0C +#define MGABES_A1CORG 0x3D10 +#define MGABES_A2CORG 0x3D14 +#define MGABES_B1CORG 0x3D18 +#define MGABES_B2CORG 0x3D1C +#define MGABES_CTL 0x3D20 +#define MGABES_PITCH 0x3D24 +#define MGABES_HCOORD 0x3D28 +#define MGABES_VCOORD 0x3D2C +#define MGABES_HISCAL 0x3D30 +#define MGABES_VISCAL 0x3D34 +#define MGABES_HSRCST 0x3D38 +#define MGABES_HSRCEND 0x3D3C +#define MGABES_LUMACTL 0x3D40 +#define MGABES_V1WGHT 0x3D48 +#define MGABES_V2WGHT 0x3D4C +#define MGABES_HSRCLST 0x3D50 +#define MGABES_V1SRCLST 0x3D54 +#define MGABES_V2SRCLST 0x3D58 +#define MGABES_A1C3ORG 0x3D60 +#define MGABES_A2C3ORG 0x3D64 +#define MGABES_B1C3ORG 0x3D68 +#define MGABES_B2C3ORG 0x3D6C +#define MGABES_GLOBCTL 0x3DC0 +#define MGABES_STATUS 0x3DC4 + +/*MAVEN registers >= TODO */ +#define MGAMAV_PIXPLLM 0x80 +#define MGAMAV_PIXPLLN 0x81 +#define MGAMAV_PIXPLLP 0x82 +#define MGAMAV_MONSET 0x8C +#define MGAMAV_TEST 0x8D +#define MGAMAV_MONEN 0x94 +#define MGAMAV_LASTLINEL 0x96 +#define MGAMAV_LASTLINEH 0x97 +#define MGAMAV_HSYNCLENL 0x9A +#define MGAMAV_HSYNCLENH 0x9B +#define MGAMAV_HSYNCSTRL 0x9C +#define MGAMAV_HSYNCSTRH 0x9D +#define MGAMAV_HDISPLAYL 0x9E +#define MGAMAV_HDISPLAYH 0x9F +#define MGAMAV_HTOTALL 0xA0 +#define MGAMAV_HTOTALH 0xA1 +#define MGAMAV_VSYNCLENL 0xA2 +#define MGAMAV_VSYNCLENH 0xA3 +#define MGAMAV_VSYNCSTRL 0xA4 +#define MGAMAV_VSYNCSTRH 0xA5 +#define MGAMAV_VDISPLAYL 0xA6 +#define MGAMAV_VDISPLAYH 0xA7 +#define MGAMAV_VTOTALL 0xA8 +#define MGAMAV_VTOTALH 0xA9 +#define MGAMAV_HVIDRSTL 0xAA +#define MGAMAV_HVIDRSTH 0xAB +#define MGAMAV_VVIDRSTL 0xAC +#define MGAMAV_VVIDRSTH 0xAD +#define MGAMAV_OUTMODE 0xB0 +#define MGAMAV_LOCK 0xB3 +#define MGAMAV_LUMA 0xB9 +#define MGAMAV_STABLE 0xBF + +/*Macros for convenient accesses to the G400*/ + +#define MGA_REG8(r_) ((vuint8 *)regs)[(r_)] +#define MGA_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] + +/*read and write to PCI config space*/ +#define CFGR(A) (gx00_pci_access.offset=MGACFG_##A, ioctl(fd,GX00_GET_PCI, &gx00_pci_access,sizeof(gx00_pci_access)), gx00_pci_access.value) +#define CFGW(A,B) (gx00_pci_access.offset=MGACFG_##A, gx00_pci_access.value = B, ioctl(fd,GX00_SET_PCI,&gx00_pci_access,sizeof(gx00_pci_access))) + +/*read and write from the dac registers*/ +#define DACR(A) (MGA_REG8(MGADAC_##A)) +#define DACW(A,B) (MGA_REG8(MGADAC_##A)=B) + +/*read and write from the dac index register*/ +#define DXIR(A) (DACW(PALWTADD,MGADXI_##A),DACR(X_DATAREG)) +#define DXIW(A,B) (DACW(PALWTADD,MGADXI_##A),DACW(X_DATAREG,B)) + +/*read and write from the vga registers*/ +#define VGAR(A) (MGA_REG8(MGAVGA_##A)) +#define VGAW(A,B) (MGA_REG8(MGAVGA_##A)=B) + +/*read and write from the indexed vga registers*/ +#define VGAR_I(A,B) (VGAW(A##_I,B),VGAR(A##_D)) +#define VGAW_I(A,B,C) (VGAW(A##_I,B),VGAW(A##_D,C)) + +/*read and write from the powergraphics registers*/ +#define ACCR(A) (MGA_REG32(MGAACC_##A)) +#define ACCW(A,B) (MGA_REG32(MGAACC_##A)=B) +#define ACCGO(A,B) (MGA_REG32(MGAACC_##A + 0x0100)=B) + +/*read and write from the backend scaler registers*/ +#define BESR(A) (MGA_REG32(MGABES_##A)) +#define BESW(A,B) (MGA_REG32(MGABES_##A)=B) + +/*read and write from first CRTC*/ +#define CR1R(A) (MGA_REG32(MGACR1_##A)) +#define CR1W(A,B) (MGA_REG32(MGACR1_##A)=B) + +/*read and write from second CRTC*/ +#define CR2R(A) (MGA_REG32(MGACR2_##A)) +#define CR2W(A,B) (MGA_REG32(MGACR2_##A)=B) + +/*read and write from maven*/ +#define MAVR(A) (i2c_maven_read (MGAMAV_##A )) +#define MAVW(A,B) (i2c_maven_write(MGAMAV_##A ,B)) +#define MAVRW(A) (i2c_maven_read (MGAMAV_##A )|(i2c_maven_read(MGAMAV_##A +1)<<8)) +#define MAVWW(A,B) (i2c_maven_write(MGAMAV_##A ,B &0xFF),i2c_maven_write(MGAMAV_##A +1,B >>8)) +#define MAVWWP(A,B) (i2c_maven_write(A ,B &0xFF),i2c_maven_write(A +1,B >>8)) diff --git a/src/add-ons/kernel/drivers/graphics/Jamfile b/src/add-ons/kernel/drivers/graphics/Jamfile index 05e48171ef..73cffdf7fc 100644 --- a/src/add-ons/kernel/drivers/graphics/Jamfile +++ b/src/add-ons/kernel/drivers/graphics/Jamfile @@ -1,3 +1,4 @@ SubDir OBOS_TOP src add-ons kernel drivers graphics ; +SubInclude OBOS_TOP src add-ons kernel drivers graphics matrox ; SubInclude OBOS_TOP src add-ons kernel drivers graphics nvidia ; diff --git a/src/add-ons/kernel/drivers/graphics/matrox/Jamfile b/src/add-ons/kernel/drivers/graphics/matrox/Jamfile new file mode 100644 index 0000000000..73483f6541 --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/matrox/Jamfile @@ -0,0 +1,17 @@ +SubDir OBOS_TOP src add-ons kernel drivers graphics matrox ; + +UsePrivateHeaders graphics ; +UsePrivateHeaders [ FDirName graphics matrox ] ; + +R5KernelAddon mga.driver : kernel drivers bin : + driver.c +; + +# Link to kernel/drivers/dev/graphics +{ + local dir = [ FDirName $(OBOS_ADDON_DIR) kernel drivers dev graphics ] ; + local instDriver = mga.driver ; + MakeLocate $(instDriver) : $(dir) ; + RelSymLink $(instDriver) : mga.driver ; +} + diff --git a/src/add-ons/kernel/drivers/graphics/matrox/driver.c b/src/add-ons/kernel/drivers/graphics/matrox/driver.c new file mode 100644 index 0000000000..c57d9fd9a9 --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/matrox/driver.c @@ -0,0 +1,827 @@ +/* + Copyright 1999, Be Incorporated. All Rights Reserved. + This file may be used under the terms of the Be Sample Code License. + + Modified to work with the Matrox G400 - Mark Watson +*/ + +/* standard kernel driver stuff */ +#include +#include +#include +#include +#include +#include // for strtoXX + +/* this is for the standardized portion of the driver API */ +/* currently only one operation is defined: B_GET_ACCELERANT_SIGNATURE */ +#include + +/* this is for sprintf() */ +#include + +/* this is for string compares */ +#include + +/* The private interface between the accelerant and the kernel driver. */ +#include "DriverInterface.h" +#include "mga_macros.h" + +#define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) +#define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) + +#define MAX_DEVICES 8 + +#define DEVICE_FORMAT "%04X_%04X_%02X%02X%02X" // apsed + +/* Tell the kernel what revision of the driver API we support */ +int32 api_version = B_CUR_DRIVER_API_VERSION; // apsed, was 2, is 2 in R5 + +/* these structures are private to the kernel driver */ +typedef struct device_info device_info; + +typedef struct { + timer te; /* timer entry for add_timer() */ + device_info *di; /* pointer to the owning device */ + bigtime_t when_target; /* when we're supposed to wake up */ +} timer_info; + +struct device_info { + uint32 is_open; /* a count of how many times the devices has been opened */ + area_id shared_area; /* the area shared between the driver and all of the accelerants */ + shared_info *si; /* a pointer to the shared area, for convenience */ + vuint32 *regs; /* kernel's pointer to memory mapped registers */ + pci_info pcii; /* a convenience copy of the pci info for this device */ + char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ +}; + +typedef struct { + uint32 count; /* number of devices actually found */ + benaphore kernel; /* for serializing opens/closes */ + char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ + device_info di[MAX_DEVICES]; /* device specific stuff */ +} DeviceData; + +/* prototypes for our private functions */ +static status_t open_hook (const char* name, uint32 flags, void** cookie); +static status_t close_hook (void* dev); +static status_t free_hook (void* dev); +static status_t read_hook (void* dev, off_t pos, void* buf, size_t* len); +static status_t write_hook (void* dev, off_t pos, const void* buf, size_t* len); +static status_t control_hook (void* dev, uint32 msg, void *buf, size_t len); +static status_t map_device(device_info *di); +static void unmap_device(device_info *di); +static void probe_devices(void); +static int32 gx00_interrupt(void *data); + +static DeviceData *pd; +static pci_module_info *pci_bus; +static device_hooks graphics_device_hooks = { + open_hook, + close_hook, + free_hook, + control_hook, + read_hook, + write_hook, + NULL, + NULL, + NULL, + NULL +}; + +#define VENDOR_ID 0x102b /* Matrox graphics inc. */ + +static uint16 gx00_device_list[] = { + 0x2527,/*G550AGP*/ + 0x0525,/*G400AGP*/ + 0x0520,/*G200PCI*/ + 0x0521,/*G200AGP*/ + 0x1000,/*G100PCI*/ + 0x1001,/*G100AGP*/ + 0x051F,/*MGA-2164 AGP Millennium 2*/ + 0x051B,/*MGA-2164 PCI Millennium 2*/ + 0x051A,/*MGA-1054 PCI Mystic*/ + 0x0519,/*MGA-2064 PCI Millennium*/ + 0 +}; + +static struct { + uint16 vendor; + uint16 *devices; +} SupportedDevices[] = { + {VENDOR_ID, gx00_device_list}, + {0x0000, NULL} +}; + +static settings current_settings = { // see comments in mga.settings + // for driver + DRIVER_PREFIX ".accelerant", + false, // dumprom + // for accelerant + 0x00000000, // logmask + 0, // memory + false, // usebios + false, // hardcursor +}; + +static void dumprom (void *rom, size_t size) +{ + int fd = open ("/boot/home/" DRIVER_PREFIX ".rom", O_WRONLY | O_CREAT, 0666); + if (fd < 0) return; + write (fd, rom, size); + close (fd); +} + +/*return 1, is interrupt has occured*/ +int caused_vbi(vuint32 * regs) +{ + return (ACCR(STATUS)&0x20); +} + +/*clear the interrupt*/ +void clear_vbi(vuint32 * regs) +{ + ACCW(ICLEAR,0x20); +} + +void enable_vbi(vuint32 * regs) +{ + ACCW(IEN,ACCR(IEN)|0x20); +} + +void disable_vbi(vuint32 * regs) +{ + ACCW(IEN,(ACCR(IEN)&~0x20)); + ACCW(ICLEAR,0x20); +} + + +/* + init_hardware() - Returns B_OK if one is + found, otherwise returns B_ERROR so the driver will be unloaded. +*/ +status_t +init_hardware(void) { + long pci_index = 0; + pci_info pcii; + bool found_one = FALSE; + + /* choke if we can't find the PCI bus */ + if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) + return B_ERROR; + + /* while there are more pci devices */ + while ((*pci_bus->get_nth_pci_info)(pci_index, &pcii) == B_NO_ERROR) { + int vendor = 0; + + /* if we match a supported vendor */ + while (SupportedDevices[vendor].vendor) { + if (SupportedDevices[vendor].vendor == pcii.vendor_id) { + uint16 *devices = SupportedDevices[vendor].devices; + /* while there are more supported devices */ + while (*devices) { + /* if we match a supported device */ + if (*devices == pcii.device_id ) { + + found_one = TRUE; + goto done; + } + /* next supported device */ + devices++; + } + } + vendor++; + } + /* next pci_info struct, please */ + pci_index++; + } + +done: + /* put away the module manager */ + put_module(B_PCI_MODULE_NAME); + return (found_one ? B_OK : B_ERROR); +} + +status_t +init_driver(void) { + void *settings_handle; + + // get driver/accelerant settings, apsed + settings_handle = load_driver_settings (DRIVER_PREFIX ".settings"); + if (settings_handle != NULL) { + const char *item; + char *end; + uint32 value; + + // for driver + item = get_driver_parameter (settings_handle, "accelerant", "", ""); + if ((strlen (item) > 0) && (strlen (item) < sizeof (current_settings.accelerant) - 1)) { + strcpy (current_settings.accelerant, item); + } + current_settings.dumprom = get_driver_boolean_parameter (settings_handle, "dumprom", false, false); + + // for accelerant + item = get_driver_parameter (settings_handle, "logmask", "0x00000000", "0x00000000"); + value = strtoul (item, &end, 0); + if (*end == '\0') current_settings.logmask = value; + + item = get_driver_parameter (settings_handle, "memory", "0", "0"); + value = strtoul (item, &end, 0); + if (*end == '\0') current_settings.memory = value; + + current_settings.hardcursor = get_driver_boolean_parameter (settings_handle, "hardcursor", false, false); + current_settings.usebios = get_driver_boolean_parameter (settings_handle, "usebios", false, false); + + unload_driver_settings (settings_handle); + } + + /* get a handle for the pci bus */ + if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) + return B_ERROR; + + /* driver private data */ + pd = (DeviceData *)calloc(1, sizeof(DeviceData)); + if (!pd) { + put_module(B_PCI_MODULE_NAME); + return B_ERROR; + } + /* initialize the benaphore */ + INIT_BEN(pd->kernel); + /* find all of our supported devices */ + probe_devices(); + return B_OK; +} + +const char ** +publish_devices(void) { + /* return the list of supported devices */ + return (const char **)pd->device_names; +} + +device_hooks * +find_device(const char *name) { + int index = 0; + while (pd->device_names[index]) { + if (strcmp(name, pd->device_names[index]) == 0) + return &graphics_device_hooks; + index++; + } + return NULL; + +} + +void uninit_driver(void) { + + /* free the driver data */ + DELETE_BEN(pd->kernel); + free(pd); + pd = NULL; + + /* put the pci module away */ + put_module(B_PCI_MODULE_NAME); +} + +static status_t map_device(device_info *di) { + /* frame buffer in [0], control regs in [1], pseudo_dma in [2] */ + int frame_buffer = 0; + int registers = 1; + int pseudo_dma = 2; + + char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ + shared_info *si = di->si; + uint32 tmpUlong; + pci_info *pcii = &(di->pcii); + system_info sysinfo; + + /*storage for the physical to virtual table (used for dma buffer)*/ +// physical_entry physical_memory[2]; +// #define G400_DMA_BUFFER_SIZE 1024*1024 + + /*variables for making copy of ROM*/ + int i; + char * rom_temp; + area_id rom_area; + + /* enable memory mapped IO, disable VGA I/O - this is standard*/ + tmpUlong = get_pci(PCI_command, 4); + tmpUlong |= 0x00000002; + tmpUlong &= 0xfffffffe; + set_pci(PCI_command, 4, tmpUlong); + + /*work out which version of BeOS is running*/ + get_system_info(&sysinfo); + if (sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ + { + si->use_clone_bugfix = 1; + } + else + { + si->use_clone_bugfix = 0; + } + + /* work out a name for the register mapping */ + sprintf(buffer, DEVICE_FORMAT " regs", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* get a virtual memory address for the registers*/ + si->regs_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[registers], + di->pcii.u.h0.base_register_sizes[registers], + B_ANY_KERNEL_ADDRESS, + (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), + (void **)&(di->regs)); + si->clone_bugfix_regs = (uint32 *) di->regs; + + /* if mapping registers to vmem failed then pass on error */ + if (si->regs_area < 0) return si->regs_area; + + /* work out a name for the ROM mapping*/ + sprintf(buffer, DEVICE_FORMAT " rom", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /*place ROM over the fbspace (this is definately safe)*/ + tmpUlong = di->pcii.u.h0.base_registers[frame_buffer]; + tmpUlong |= 0x00000001; + set_pci(PCI_rom_base, 4, tmpUlong); + + rom_area = map_physical_memory( + buffer, + (void *)di->pcii.u.h0.base_registers[frame_buffer], + 32768, + B_ANY_KERNEL_ADDRESS, + B_READ_AREA, + (void **)&(rom_temp) + ); + + /* if mapping ROM to vmem failed then clean up and pass on error */ + if (rom_area < 0) { + delete_area(si->regs_area); + si->regs_area = -1; + return rom_area; + } + + /* make a copy of ROM for future reference*/ + memcpy (si->rom_mirror, rom_temp, 32768); + if (current_settings.dumprom) dumprom (rom_temp, 32768); + + /*disable ROM and delete the area*/ + set_pci(PCI_rom_base,4,0); + delete_area(rom_area); + + /* work out a name for the pseudo dma mapping*/ + sprintf(buffer, DEVICE_FORMAT " pseudodma", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* map the pseudo dma into vmem (write-only)*/ + si->pseudo_dma_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[pseudo_dma], + di->pcii.u.h0.base_register_sizes[pseudo_dma], + B_ANY_KERNEL_ADDRESS, + B_WRITE_AREA, + &(si->pseudo_dma)); + + /* if there was an error, delete our other areas and pass on error*/ + if (si->pseudo_dma_area < 0) { + delete_area(si->regs_area); + si->regs_area = -1; + return si->pseudo_dma_area; + } + + /* work out a name for the a dma buffer*/ +// sprintf(buffer, DEVICE_FORMAT " dmabuffer", +// di->pcii.vendor_id, di->pcii.device_id, +// di->pcii.bus, di->pcii.device, di->pcii.function); + + /* create an area for the dma buffer*/ +// si->dma_buffer_area = create_area( +// buffer, +// &si->dma_buffer, +// B_ANY_ADDRESS, +// G400_DMA_BUFFER_SIZE, +// B_FULL_LOCK|B_CONTIGUOUS, +// B_READ_AREA|B_WRITE_AREA); + + /* if there was an error, delete our other areas and pass on error*/ +// if (si->dma_buffer_area < 0) { +// delete_area(si->pseudo_dma_area); +// si->pseudo_dma_area = -1; +// delete_area(si->regs_area); +// si->regs_area = -1; +// return si->dma_buffer_area; +// } + + /*find where it is in real memory*/ +// get_memory_map(si->dma_buffer,4,physical_memory,1); +// si->dma_buffer_pci = physical_memory[0].address; /*addr from PCI space*/ + + /* work out a name for the framebuffer mapping*/ + sprintf(buffer, DEVICE_FORMAT " framebuffer", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* map the framebuffer into vmem, using Write Combining*/ + si->fb_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[frame_buffer], + di->pcii.u.h0.base_register_sizes[frame_buffer], + B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, + B_READ_AREA + B_WRITE_AREA, + &(si->framebuffer)); + + /*if failed with write combining try again without*/ + if (si->fb_area < 0) { + si->fb_area = map_physical_memory( + buffer, + (void *) di->pcii.u.h0.base_registers[frame_buffer], + di->pcii.u.h0.base_register_sizes[frame_buffer], + B_ANY_KERNEL_BLOCK_ADDRESS, + B_READ_AREA + B_WRITE_AREA, + &(si->framebuffer)); + } + + /* if there was an error, delete our other areas and pass on error*/ + if (si->fb_area < 0) { + delete_area(si->dma_buffer_area); + si->dma_buffer_area = -1; + delete_area(si->pseudo_dma_area); + si->pseudo_dma_area = -1; + delete_area(si->regs_area); + si->regs_area = -1; + return si->fb_area; + } + /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ + si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; + + // remember settings for use here and in accelerant + si->settings = current_settings; + + /* in any case, return the result */ + return si->fb_area; +} + +static void unmap_device(device_info *di) { + shared_info *si = di->si; + uint32 tmpUlong; + pci_info *pcii = &(di->pcii); + + /* disable memory mapped IO */ + tmpUlong = get_pci(PCI_command, 4); + tmpUlong &= 0xfffffffc; + set_pci(PCI_command, 4, tmpUlong); + /* delete the areas */ + if (si->regs_area >= 0) delete_area(si->regs_area); + if (si->fb_area >= 0) delete_area(si->fb_area); + si->regs_area = si->fb_area = -1; + si->framebuffer = NULL; + di->regs = NULL; +} + +static void probe_devices(void) { + uint32 pci_index = 0; + uint32 count = 0; + device_info *di = pd->di; + + /* while there are more pci devices */ + while ((count < MAX_DEVICES) && ((*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_NO_ERROR)) { + int vendor = 0; + + /* if we match a supported vendor */ + while (SupportedDevices[vendor].vendor) { + if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { + uint16 *devices = SupportedDevices[vendor].devices; + /* while there are more supported devices */ + while (*devices) { + /* if we match a supported device */ + if (*devices == di->pcii.device_id ) { + /* publish the device name */ + sprintf(di->name, "graphics/" DEVICE_FORMAT, + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + + /* remember the name */ + pd->device_names[count] = di->name; + /* mark the driver as available for R/W open */ + di->is_open = 0; + /* mark areas as not yet created */ + di->shared_area = -1; + /* mark pointer to shared data as invalid */ + di->si = NULL; + /* inc pointer to device info */ + di++; + /* inc count */ + count++; + /* break out of these while loops */ + goto next_device; + } + /* next supported device */ + devices++; + } + } + vendor++; + } +next_device: + /* next pci_info struct, please */ + pci_index++; + } + /* propagate count */ + pd->count = count; + /* terminate list of device names with a null pointer */ + pd->device_names[pd->count] = NULL; +} + +static uint32 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) { + uint32 handled = B_HANDLED_INTERRUPT; + /* release the vblank semaphore */ + if (si->vblank >= 0) { + int32 blocked; + if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { + release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); + handled = B_INVOKE_SCHEDULER; + } + } + return handled; +} + +static int32 +gx00_interrupt(void *data) +{ + int32 handled = B_UNHANDLED_INTERRUPT; + device_info *di = (device_info *)data; + shared_info *si = di->si; + int32 *flags = &(si->flags); + vuint32 *regs; + + /* is someone already handling an interrupt for this device? */ + if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) { + goto exit0; + } + /* get regs */ + regs = di->regs; + + /* was it a VBI? */ + if (caused_vbi(regs)) { + /*clear the interrupt*/ + clear_vbi(regs); + /*release the semaphore*/ + handled = thread_interrupt_work(flags, regs, si); + } + + /* note that we're not in the handler any more */ + atomic_and(flags, ~SKD_HANDLER_INSTALLED); + +exit0: + return handled; +} + +static status_t open_hook (const char* name, uint32 flags, void** cookie) { + int32 index = 0; + device_info *di; + shared_info *si; + thread_id thid; + thread_info thinfo; + status_t result = B_OK; + vuint32 *regs; + char shared_name[B_OS_NAME_LENGTH]; + + /* find the device name in the list of devices */ + /* we're never passed a name we didn't publish */ + while (pd->device_names[index] && (strcmp(name, pd->device_names[index]) != 0)) index++; + + /* for convienience */ + di = &(pd->di[index]); + + /* make sure no one else has write access to the common data */ + AQUIRE_BEN(pd->kernel); + + /* if it's already open for writing */ + if (di->is_open) { + /* mark it open another time */ + goto mark_as_open; + } + /* create the shared area */ + sprintf(shared_name, DEVICE_FORMAT " shared", + di->pcii.vendor_id, di->pcii.device_id, + di->pcii.bus, di->pcii.device, di->pcii.function); + /* create this area with NO user-space read or write permissions, to prevent accidental dammage */ + di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 0); + if (di->shared_area < 0) { + /* return the error */ + result = di->shared_area; + goto done; + } + + /* save a few dereferences */ + si = di->si; + + /* save the vendor and device IDs */ + si->vendor_id = di->pcii.vendor_id; + si->device_id = di->pcii.device_id; + si->revision = di->pcii.revision; + + /* map the device */ + result = map_device(di); + if (result < 0) goto free_shared; + result = B_OK; + + /* create a semaphore for vertical blank management */ + si->vblank = create_sem(0, di->name); + if (si->vblank < 0) { + result = si->vblank; + goto unmap; + } + + /* change the owner of the semaphores to the opener's team */ + /* this is required because apps can't aquire kernel semaphores */ + thid = find_thread(NULL); + get_thread_info(thid, &thinfo); + set_sem_owner(si->vblank, thinfo.team); + + /* assign local regs pointer for SAMPLExx() macros */ + regs = di->regs; + + /* disable and clear any pending interrupts */ + disable_vbi(regs); + + /* If there is an interrupt line then set up interrupts*/ + if ((di->pcii.u.h0.interrupt_pin == 0x00) || (di->pcii.u.h0.interrupt_line == 0xff)){ + /*interrupt does not exist so DIE*/ + goto delete_the_sem; + } else { + /* otherwise install our interrupt handler */ + result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, gx00_interrupt, (void *)di, 0); + /* bail if we couldn't install the handler */ + if (result != B_OK) goto delete_the_sem; + } + +mark_as_open: + /* mark the device open */ + di->is_open++; + + /* send the cookie to the opener */ + *cookie = di; + + goto done; + + +delete_the_sem: + delete_sem(si->vblank); + +unmap: + unmap_device(di); + +free_shared: + /* clean up our shared area */ + delete_area(di->shared_area); + di->shared_area = -1; + di->si = NULL; + +done: + /* end of critical section */ + RELEASE_BEN(pd->kernel); + + /* all done, return the status */ + return result; +} + +/* ---------- + read_hook - does nothing, gracefully +----- */ +static status_t +read_hook (void* dev, off_t pos, void* buf, size_t* len) +{ + *len = 0; + return B_NOT_ALLOWED; +} + + +/* ---------- + write_hook - does nothing, gracefully +----- */ +static status_t +write_hook (void* dev, off_t pos, const void* buf, size_t* len) +{ + *len = 0; + return B_NOT_ALLOWED; +} + +/* ---------- + close_hook - does nothing, gracefully +----- */ +static status_t +close_hook (void* dev) +{ + /* we don't do anything on close: there might be dup'd fd */ + return B_NO_ERROR; +} + +/* ----------- + free_hook - close down the device +----------- */ +static status_t +free_hook (void* dev) { + device_info *di = (device_info *)dev; + shared_info *si = di->si; + vuint32 *regs = di->regs; + + /* lock the driver */ + AQUIRE_BEN(pd->kernel); + + /* if opened multiple times, decrement the open count and exit */ + if (di->is_open > 1) + goto unlock_and_exit; + + /* disable and clear any pending interrupts */ + disable_vbi(regs); + + /* remove interrupt handler */ + remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, gx00_interrupt, di); + + /* delete the semaphores, ignoring any errors ('cause the owning team may have died on us) */ + delete_sem(si->vblank); + si->vblank = -1; + + /* free regs and framebuffer areas */ + unmap_device(di); + + /* clean up our shared area */ + delete_area(di->shared_area); + di->shared_area = -1; + di->si = NULL; + +unlock_and_exit: + /* mark the device available */ + di->is_open--; + /* unlock the driver */ + RELEASE_BEN(pd->kernel); + /* all done */ + return B_OK; +} + +/* ----------- + control_hook - where the real work is done +----------- */ +static status_t +control_hook (void* dev, uint32 msg, void *buf, size_t len) { + device_info *di = (device_info *)dev; + status_t result = B_DEV_INVALID_IOCTL; + + switch (msg) { + /* the only PUBLIC ioctl */ + case B_GET_ACCELERANT_SIGNATURE: { + char *sig = (char *)buf; + strcpy(sig, current_settings.accelerant); + result = B_OK; + } break; + + /* PRIVATE ioctl from here on */ + case GX00_GET_PRIVATE_DATA: { + gx00_get_private_data *gpd = (gx00_get_private_data *)buf; + if (gpd->magic == GX00_PRIVATE_DATA_MAGIC) { + gpd->shared_info_area = di->shared_area; + result = B_OK; + } + } break; + case GX00_GET_PCI: { + gx00_get_set_pci *gsp = (gx00_get_set_pci *)buf; + if (gsp->magic == GX00_PRIVATE_DATA_MAGIC) { + pci_info *pcii = &(di->pcii); + gsp->value = get_pci(gsp->offset, gsp->size); + result = B_OK; + } + } break; + case GX00_SET_PCI: { + gx00_get_set_pci *gsp = (gx00_get_set_pci *)buf; + if (gsp->magic == GX00_PRIVATE_DATA_MAGIC) { + pci_info *pcii = &(di->pcii); + set_pci(gsp->offset, gsp->size, gsp->value); + result = B_OK; + } + } break; + case GX00_DEVICE_NAME: { // apsed + gx00_device_name *dn = (gx00_device_name *)buf; + if (dn->magic == GX00_PRIVATE_DATA_MAGIC) { + strcpy(dn->name, di->name); + result = B_OK; + } + } break; + case GX00_RUN_INTERRUPTS: { + gx00_set_bool_state *ri = (gx00_set_bool_state *)buf; + if (ri->magic == GX00_PRIVATE_DATA_MAGIC) { + vuint32 *regs = di->regs; + if (ri->do_it) { + enable_vbi(regs); + } else { + disable_vbi(regs); + } + result = B_OK; + } + } break; + } + return result; +} + diff --git a/src/add-ons/kernel/drivers/graphics/matrox/mga.settings b/src/add-ons/kernel/drivers/graphics/matrox/mga.settings new file mode 100644 index 0000000000..7a9077ff3a --- /dev/null +++ b/src/add-ons/kernel/drivers/graphics/matrox/mga.settings @@ -0,0 +1,26 @@ +# Settings file for the mga driver and accelerant +# +# This file should be moved to the directory +# ~/config/settings/kernel/drivers/ +# + +# mga.driver parameters +#accelerant "mga.accelerant" + +# mga.accelerant parameters +usebios true # if true rely on bios to coldstart the card instead of by the driver + # currently also: if false use BIOS PINS config info, otherwise just guess... +#memory 2 # in MB, override builtin memory size detection +hardcursor true # if true use on-chip cursor capabilities +#logmask 0x00000000 # nothing logged, except errors, is default +#logmask 0x80000000 # log card physical features +#logmask 0x80000000 # log following mask +#logmask 0x08000604 # log overlay use in full +#logmask 0xffffffff # log everything +dumprom false # dump bios rom in ~/mga.rom + +# not yet, ?never implemented +#gamma 1.0 +#dualhead true +#mode 31500,640,648,744,840,480,481,500,500,0 +#--------- that's all \ No newline at end of file