From 37223744b700aa9e3ebe09831f10422dfc130d7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Duval?= Date: Tue, 10 Jan 2023 19:54:17 +0100 Subject: [PATCH] kernel/x86: add a hybrid type per cpu, to be dumped when the feature exists. for AlderLake CPUs Change-Id: I4beba04e3ac95d7564684ee86de99c894b57a15c Reviewed-on: https://review.haiku-os.org/c/haiku/+/5988 Reviewed-by: waddlesplash Tested-by: Commit checker robot --- headers/private/kernel/arch/x86/arch_cpu.h | 2 + src/system/kernel/arch/x86/arch_cpu.cpp | 44 +++++++++++++++++++--- 2 files changed, 41 insertions(+), 5 deletions(-) diff --git a/headers/private/kernel/arch/x86/arch_cpu.h b/headers/private/kernel/arch/x86/arch_cpu.h index 16eb276672..4cf34ec4ee 100644 --- a/headers/private/kernel/arch/x86/arch_cpu.h +++ b/headers/private/kernel/arch/x86/arch_cpu.h @@ -356,6 +356,7 @@ // https://en.wikipedia.org/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features #define IA32_FEATURE_AVX512_4VNNIW (1 << 2) // AVX-512 4-register Neural Network Instructions #define IA32_FEATURE_AVX512_4FMAPS (1 << 3) // AVX-512 4-register Multiply Accumulation Single precision +#define IA32_FEATURE_HYBRID_CPU (1 << 15) // CPUs are of several types #define IA32_FEATURE_IBRS (1 << 26) // IBRS / IBPB Speculation Control #define IA32_FEATURE_STIBP (1 << 27) // STIBP Speculation Control #define IA32_FEATURE_L1D_FLUSH (1 << 28) // L1D_FLUSH supported @@ -542,6 +543,7 @@ typedef struct arch_cpu_info { int model; int extended_model; uint32 patch_level; + uint8 hybrid_type; uint32 logical_apic_id; diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp b/src/system/kernel/arch/x86/arch_cpu.cpp index 7b2598b394..3fd6353202 100644 --- a/src/system/kernel/arch/x86/arch_cpu.cpp +++ b/src/system/kernel/arch/x86/arch_cpu.cpp @@ -41,7 +41,7 @@ #define DUMP_FEATURE_STRING 1 #define DUMP_CPU_TOPOLOGY 1 -#define DUMP_CPU_PATCHLEVEL 1 +#define DUMP_CPU_PATCHLEVEL_TYPE 1 /* cpu vendor info */ @@ -347,7 +347,7 @@ x86_init_fpu(void) static void dump_feature_string(int currentCPU, cpu_ent* cpu) { - char features[512]; + char features[768]; features[0] = 0; if (cpu->arch.feature[FEATURE_COMMON] & IA32_FEATURE_FPU) @@ -612,6 +612,8 @@ dump_feature_string(int currentCPU, cpu_ent* cpu) strlcat(features, "rdpid ", sizeof(features)); if (cpu->arch.feature[FEATURE_7_ECX] & IA32_FEATURE_SGX_LC) strlcat(features, "sgx_lc ", sizeof(features)); + if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_HYBRID_CPU) + strlcat(features, "hybrid ", sizeof(features)); if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_IBRS) strlcat(features, "ibrs ", sizeof(features)); if (cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_STIBP) @@ -1253,6 +1255,34 @@ load_microcode(int currentCPU) } +static uint8 +get_hybrid_cpu_type() +{ + cpu_ent* cpu = get_cpu_struct(); + if ((cpu->arch.feature[FEATURE_7_EDX] & IA32_FEATURE_HYBRID_CPU) == 0) + return 0; + +#define X86_HYBRID_CPU_TYPE_ID_SHIFT 24 + cpuid_info cpuid; + get_current_cpuid(&cpuid, 0x1a, 0); + return cpuid.regs.eax >> X86_HYBRID_CPU_TYPE_ID_SHIFT; +} + + +static const char* +get_hybrid_cpu_type_string(uint8 type) +{ + switch (type) { + case 0x20: + return "Atom"; + case 0x40: + return "Core"; + default: + return ""; + } +} + + static void detect_cpu(int currentCPU, bool full = true) { @@ -1415,12 +1445,16 @@ detect_cpu(int currentCPU, bool full = true) else if (cpu->arch.vendor == VENDOR_AMD) detect_amd_patch_level(cpu); + cpu->arch.hybrid_type = get_hybrid_cpu_type(); + #if DUMP_FEATURE_STRING dump_feature_string(currentCPU, cpu); #endif -#if DUMP_CPU_PATCHLEVEL - dprintf("CPU %d: patch_level %" B_PRIx32 "\n", currentCPU, - cpu->arch.patch_level); +#if DUMP_CPU_PATCHLEVEL_TYPE + dprintf("CPU %d: patch_level %" B_PRIx32 "%s%s\n", currentCPU, + cpu->arch.patch_level, + cpu->arch.hybrid_type != 0 ? ", hybrid type ": "", + get_hybrid_cpu_type_string(cpu->arch.hybrid_type)); #endif }