From 381288838bbeafb53bda6e480d68d8a8b3ef7ed1 Mon Sep 17 00:00:00 2001
From: Rudolf Cornelissen <rudolf.cornelissen@gmail.com>
Date: Mon, 18 Jul 2005 11:39:11 +0000
Subject: [PATCH] added colordepth and CRTC FIFO limit programming. You can now
 switch colorspaces on the fly, but colors probably mess-up because of still
 lacking colorpalette programming.

git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@13745 a95241bf-73f2-0310-859d-f6bbb57e9c96
---
 src/add-ons/accelerants/via/SetDisplayMode.c | 10 ++--
 src/add-ons/accelerants/via/engine/crtc.c    | 60 +++++++++++++-------
 2 files changed, 43 insertions(+), 27 deletions(-)

diff --git a/src/add-ons/accelerants/via/SetDisplayMode.c b/src/add-ons/accelerants/via/SetDisplayMode.c
index 34a94ec04b..af68e6a022 100644
--- a/src/add-ons/accelerants/via/SetDisplayMode.c
+++ b/src/add-ons/accelerants/via/SetDisplayMode.c
@@ -155,22 +155,22 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set)
 		case B_CMAP8:
 			colour_depth1 =  8;
 //			head1_mode(BPP8, 1.0);
-//			head1_depth(BPP8);
+			head1_depth(BPP8);
 			break;
 		case B_RGB15_LITTLE:
 			colour_depth1 = 16;
 //			head1_mode(BPP15, 1.0);
-//			head1_depth(BPP15);
+			head1_depth(BPP15);
 			break;
 		case B_RGB16_LITTLE:
 			colour_depth1 = 16;
 //			head1_mode(BPP16, 1.0);
-//			head1_depth(BPP16);
+			head1_depth(BPP16);
 			break;
 		case B_RGB32_LITTLE:
 			colour_depth1 = 32;
 //			head1_mode(BPP32, 1.0);
-//			head1_depth(BPP32);
+			head1_depth(BPP32);
 			break;
 		}
 		/*set the colour depth for CRTC2 and DAC2 */
@@ -286,7 +286,7 @@ status = B_OK;
 
 		/* set the colour depth for CRTC1 and the DAC */
 		/* first set the colordepth */
-//		head1_depth(colour_mode);
+		head1_depth(colour_mode);
 		/* then(!) program the PAL (<8bit colordepth does not support 8bit PAL) */
 //		head1_mode(colour_mode,1.0);
 
diff --git a/src/add-ons/accelerants/via/engine/crtc.c b/src/add-ons/accelerants/via/engine/crtc.c
index a8c37a88da..1510b61925 100644
--- a/src/add-ons/accelerants/via/engine/crtc.c
+++ b/src/add-ons/accelerants/via/engine/crtc.c
@@ -80,6 +80,7 @@ status_t eng_crtc_validate_timing(
 /*set a mode line - inputs are in pixels*/
 status_t eng_crtc_set_timing(display_mode target)
 {
+	uint16 fifolimit = 0;
 	uint8 temp;
 
 	uint32 htotal;		/*total horizontal total VCLKs*/
@@ -269,6 +270,29 @@ status_t eng_crtc_set_timing(display_mode target)
 		ENG_REG8(RG8_MISCW) = temp;
 
 		LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR)));
+
+		/* setup CRTC FIFO depth, method 'extrapolated' from VBE BIOS behaviour */
+		switch (target.space)
+		{
+		case B_CMAP8:
+			fifolimit = 0x0001;
+			break;
+		case B_RGB15_LITTLE:
+		case B_RGB16_LITTLE:
+			fifolimit = 0x0002;
+			break;
+		case B_RGB24_LITTLE:
+			fifolimit = 0x0003;
+			break;
+		case B_RGB32_LITTLE:
+			fifolimit = 0x0004;
+			break;
+		}
+		fifolimit *= target.timing.h_display;
+		fifolimit >>= 4;
+		fifolimit += 4;
+		SEQW(FETCHCNTLO, (fifolimit & 0x00fe));
+		SEQW(FETCHCNTHI, (((SEQR(FETCHCNTHI)) & 0xfc) | ((fifolimit & 0x0300) >> 8)));
 	}
 
 	/* always disable interlaced operation */
@@ -396,43 +420,35 @@ status_t eng_crtc_set_timing(display_mode target)
 
 status_t eng_crtc_depth(int mode)
 {
-	uint8 viddelay = 0;
-	uint32 genctrl = 0;
+	uint8 genctrl = 0;
 
 	/* set VCLK scaling */
 	switch(mode)
 	{
 	case BPP8:
-		viddelay = 0x01;
-		/* genctrl b4 & b5 reset: 'direct mode' */
-		genctrl = 0x00101100;
+		/* bits unknown (yet): 'direct mode' */
+		genctrl = 0x22; //%0010 0010
 		break;
 	case BPP15:
-		viddelay = 0x02;
-		/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
-		genctrl = 0x00100130;
+		/* bits unknown (yet): 'indirect mode' (via colorpalette?) */
+		genctrl = 0xb6; //%1011 0110
 		break;
 	case BPP16:
-		viddelay = 0x02;
-		/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
-		genctrl = 0x00101130;
+		/* bits unknown (yet): 'indirect mode' (via colorpalette?) */
+		genctrl = 0xb6; //%1011 0110
 		break;
 	case BPP24:
-		viddelay = 0x03;
-		/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
-		genctrl = 0x00100130;
+		/* bits unknown (yet): 'indirect mode' (via colorpalette?) */
+		//fixme: unknown what to set yet..
+		genctrl = 0x00;
 		break;
 	case BPP32:
-		viddelay = 0x03;
-		/* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
-		genctrl = 0x00101130;
+		/* bits unknown (yet): 'indirect mode' (via colorpalette?) */
+		genctrl = 0xae; //%1010 1110
 		break;
 	}
-	/* enable access to primary head */
-	set_crtc_owner(0);
-
-	CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay));
-	DACW(GENCTRL, genctrl);
+	/* setup bytes per pixel, and direct/indirect mode */
+	SEQW(COLDEPTH, genctrl);
 
 	return B_OK;
 }