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Some more SandyBridge specifics to get V-blank interrupts going.

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git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42850 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
2011-10-14 19:11:29 +00:00
parent 2cc1b10386
commit 395d16a9bd
2 changed files with 35 additions and 13 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+7 -1
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@@ -225,7 +225,11 @@ struct intel_free_graphics_memory {
// to a PCH based one, that means anything that used to communicate via (G)MCH
// registers needs to use different ones on PCH based platforms (Ironlake and
// up, SandyBridge, etc.).
#define PCH_DE_INTERRUPT_ENABLE 0x4400c // INTEL_INTERRUPT_ENABLED
#define PCH_DE_POWER_MEASUREMENT 0x42400
#define PCH_DE_INTERRUPT_STATUS 0x44000 // INTEL_INTERRUPT_STATUS
#define PCH_DE_INTERRUPT_MASK 0x44004 // INTEL_INTERRUPT_MASK
#define PCH_DE_INTERRUPT_IDENTITY 0x44008 // INTEL_INTERRUPT_IDENTITY
#define PCH_DE_INTERRUPT_ENABLED 0x4400c // INTEL_INTERRUPT_ENABLED
#define PCH_DISPLAY_A_ANALOG_PORT 0xe1100 // INTEL_DISPLAY_A_ANALOG_PORT
#define PCH_DISPLAY_A_DIGITAL_PORT 0xe1120 // INTEL_DISPLAY_A_DIGITAL_PORT
#define PCH_DISPLAY_B_DIGITAL_PORT 0xe1140 // INTEL_DISPLAY_B_DIGITAL_PORT
@@ -252,6 +256,8 @@ struct intel_free_graphics_memory {
#define PCH_TRANSCODER_B_VSYNC 0xe1014 // INTEL_DISPLAY_B_VSYNC
#define PCH_LVDS_DETECTED (1 << 1)
#define PCH_INTERRUPT_VBLANK_PIPEA (1 << 7)
#define PCH_INTERRUPT_VBLANK_PIPEB (1 << 15)
// SandyBridge (SNB)