From 3a42882e0fcfa4cbe71b1bfbaee769e33b198e3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=A9r=C3=B4me=20Duval?= Date: Fri, 25 Nov 2022 19:02:44 +0100 Subject: [PATCH] intel_extreme: check another register when finding out hw_cdclk on Haswell/Broadwell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit doesn't help with #18084 Change-Id: I6f3cc8b50fc5742fab3021f01b90dfebe484b336 Reviewed-on: https://review.haiku-os.org/c/haiku/+/5830 Reviewed-by: Jérôme Duval Tested-by: Commit checker robot --- headers/private/graphics/intel_extreme/intel_extreme.h | 3 +++ .../kernel/drivers/graphics/intel_extreme/intel_extreme.cpp | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index cad0f7dc3a..a3c2c6c22d 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -927,6 +927,9 @@ struct intel_brightness_legacy { #define LCPLL_CLK_FREQ_337_5_BDW (2 << 26) #define LCPLL_CD_SOURCE_FCLK (1 << 21) +#define FUSE_STRAP 0x42014 +#define HSW_CDCLK_LIMIT (1 << 24) + // display #define INTEL_DISPLAY_OFFSET 0x1000 diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index 1e541a9b86..59646c639e 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp @@ -883,6 +883,8 @@ intel_extreme_init(intel_info &info) uint32 lcpll = read32(info, LCPLL_CTL); if ((lcpll & LCPLL_CD_SOURCE_FCLK) != 0) info.shared_info->hw_cdclk = 800000; + else if ((read32(info, FUSE_STRAP) & HSW_CDCLK_LIMIT) != 0) + info.shared_info->hw_cdclk = 450000; else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450) info.shared_info->hw_cdclk = 450000; else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_54O_BDW) @@ -895,6 +897,8 @@ intel_extreme_init(intel_info &info) uint32 lcpll = read32(info, LCPLL_CTL); if ((lcpll & LCPLL_CD_SOURCE_FCLK) != 0) info.shared_info->hw_cdclk = 800000; + else if ((read32(info, FUSE_STRAP) & HSW_CDCLK_LIMIT) != 0) + info.shared_info->hw_cdclk = 450000; else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450) info.shared_info->hw_cdclk = 450000; /* ULT type is missing