diff --git a/headers/private/graphics/radeon_hd/radeon_hd.h b/headers/private/graphics/radeon_hd/radeon_hd.h index 3375d7b94f..d511b8b229 100644 --- a/headers/private/graphics/radeon_hd/radeon_hd.h +++ b/headers/private/graphics/radeon_hd/radeon_hd.h @@ -73,14 +73,12 @@ struct radeon_shared_info { area_id registers_area; // area of memory mapped registers uint8* status_page; addr_t physical_status_page; - uint8* graphics_memory; uint32 graphics_memory_size; addr_t frame_buffer_phys; // card PCI BAR address of FB - uint32 frame_buffer_int; // card internal offset of FB + area_id frame_buffer_area; // area of memory mapped FB uint32 frame_buffer_size; // card internal FB aperture size - uint32 frame_buffer_offset; // current offset within FB - uint32 frame_buffer_free; // free space in framebuffer + uint8* frame_buffer; // virtual memory mapped FB bool has_edid; edid1_info edid_info; diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp b/src/add-ons/accelerants/radeon_hd/mode.cpp index f82158eeda..e946d4e74b 100644 --- a/src/add-ons/accelerants/radeon_hd/mode.cpp +++ b/src/add-ons/accelerants/radeon_hd/mode.cpp @@ -129,34 +129,6 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode, } -uint32 -AllocateFB(uint32 size, const char *description) -{ - uint32 chunk; - - // TODO : Kernel AreaMapper? - - // Is there any framebuffer left to allocate? - if (gInfo->shared_info->frame_buffer_free < size) { - TRACE("%s was unable to allocate a framebuffer - memory shortage\n", - __func__); - return 0; - } - - // assign requested "chunk" of framebuffer memory - chunk = gInfo->shared_info->frame_buffer_offset; - - // retally framebuffer memory status - gInfo->shared_info->frame_buffer_offset += size; - gInfo->shared_info->frame_buffer_free -= size; - - TRACE("%s allocated framebuffer %s at offset 0x%08X (size: 0x%08X)\n", - __func__, description, chunk, size); - - return chunk; -} - - // Blacks the screen out, useful for mode setting static void CardBlankSet(int crtNumber, bool blank) @@ -173,7 +145,7 @@ CardBlankSet(int crtNumber, bool blank) } write32(blackColorReg, 0); - write32AtMask(blankControlReg, blank ? 0x00000100 : 0, 0x00000100); + write32AtMask(blankControlReg, blank ? 1 << 8 : 0, 1 << 8); } @@ -219,14 +191,13 @@ CardFBSet(int crtNumber, display_mode *mode) // only for chipsets > r600 // R5xx - RS690 case is GRPH_CONTROL bit 16 - uint32 neededFrameBuffer = mode->timing.h_display - * bitsPerPixel * mode->virtual_height / 8; - uint32 fbIntAddress = gInfo->shared_info->frame_buffer_int; - uint32 fbOffset = AllocateFB(neededFrameBuffer, "DisplayFramebuffer"); + // framebuffersize = w * h * bpp = fb bits / 8 = bytes needed + + uint32 fbAddress = gInfo->shared_info->frame_buffer_phys; write32(regOffset + gRegister->grphPrimarySurfaceAddr, - fbIntAddress + fbOffset); + fbAddress); write32(regOffset + gRegister->grphPitch, bytesPerRow / 4); write32(regOffset + gRegister->grphSurfaceOffsetX, 0); @@ -275,9 +246,9 @@ CardModeSet(int crtNumber, display_mode *mode) write32(regOffset + D1CRTC_H_SYNC_A, (displayTiming.h_sync_end - displayTiming.h_sync_start) << 16); - // set flag for neg. H sync - if (!(displayTiming.flags & B_POSITIVE_HSYNC)) - write32(regOffset + D1CRTC_H_SYNC_A_CNTL, 0x01); + // set flag for neg. H sync. M76 Register Reference Guide 2-256 + write32AtMask(regOffset + D1CRTC_H_SYNC_A_CNTL, + displayTiming.flags & B_POSITIVE_HSYNC ? 0 : 1, 0x1); // *** Vertical write32(regOffset + D1CRTC_V_TOTAL, displayTiming.v_total - 1); @@ -300,9 +271,10 @@ CardModeSet(int crtNumber, display_mode *mode) write32(regOffset + D1CRTC_V_SYNC_A, (displayTiming.v_sync_end - displayTiming.v_sync_start) << 16); - // set flag for neg. V sync - if (!(displayTiming.flags & B_POSITIVE_VSYNC)) - write32(regOffset + D1CRTC_V_SYNC_A_CNTL, 0x01); + // set flag for neg. V sync. M76 Register Reference Guide 2-258 + // we don't need a mask here as this is the only param for Vertical + write32(regOffset + D1CRTC_V_SYNC_A_CNTL, + displayTiming.flags & B_POSITIVE_VSYNC ? 0 : 1); /* set D1CRTC_HORZ_COUNT_BY2_EN to 0; should only be set to 1 on 30bpp DVI modes @@ -356,6 +328,13 @@ radeon_set_display_mode(display_mode *mode) CardModeSet(crtNumber, mode); CardModeScale(crtNumber, mode); + uint16_t regOffset = (crtNumber == 0) + ? gRegister->regOffsetCRT0 : gRegister->regOffsetCRT1; + + int32 cardstatus = read32(regOffset + D1CRTC_STATUS); + + TRACE("Card Status: 0x%X\n", cardstatus); + return B_OK; } @@ -375,14 +354,8 @@ radeon_get_frame_buffer_config(frame_buffer_config *config) { TRACE("%s\n", __func__); - // TODO : This returns the location of the last allocated fb - - config->frame_buffer = gInfo->shared_info->graphics_memory - + gInfo->shared_info->frame_buffer_int - + gInfo->shared_info->frame_buffer_offset; - - config->frame_buffer_dma = (uint8 *)gInfo->shared_info->frame_buffer_phys - + gInfo->shared_info->frame_buffer_offset; + config->frame_buffer = gInfo->shared_info->frame_buffer; + config->frame_buffer_dma = (uint8 *)gInfo->shared_info->frame_buffer_phys; config->bytes_per_row = gInfo->shared_info->bytes_per_row; diff --git a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp index ca9a2c5b76..866883a5cb 100644 --- a/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp +++ b/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp @@ -46,7 +46,7 @@ radeon_hd_init(radeon_info &info) { TRACE("card(%ld): %s: called\n", info.id, __func__); - // memory mapped I/O + // *** Map shared info AreaKeeper sharedCreator; info.shared_area = sharedCreator.Create("radeon hd shared info", (void **)&info.shared_info, B_ANY_KERNEL_ADDRESS, @@ -57,6 +57,7 @@ radeon_hd_init(radeon_info &info) memset((void *)info.shared_info, 0, sizeof(radeon_shared_info)); + // *** Map Memory mapped IO // R6xx_R7xx_3D.pdf, 5.3.3.1 SET_CONFIG_REG AreaKeeper mmioMapper; info.registers_area = mmioMapper.Map("radeon hd mmio", @@ -70,12 +71,13 @@ radeon_hd_init(radeon_info &info) return info.registers_area; } + // *** Framebuffer mapping AreaKeeper frambufferMapper; info.framebuffer_area = frambufferMapper.Map("radeon hd framebuffer", (void *)info.pci->u.h0.base_registers[RHD_FB_BAR], info.pci->u.h0.base_register_sizes[RHD_FB_BAR], B_ANY_KERNEL_ADDRESS, B_READ_AREA | B_WRITE_AREA, - (void **)&info.shared_info->graphics_memory); + (void **)&info.shared_info->frame_buffer); if (frambufferMapper.InitCheck() < B_OK) { dprintf(DEVICE_NAME ": card(%ld): could not map framebuffer!\n", info.id); @@ -90,11 +92,12 @@ radeon_hd_init(radeon_info &info) mmioMapper.Detach(); frambufferMapper.Detach(); + // Pass common information to accelerant info.shared_info->device_chipset = info.device_chipset; info.shared_info->registers_area = info.registers_area; + info.shared_info->frame_buffer_area = info.framebuffer_area; info.shared_info->frame_buffer_phys = info.pci->u.h0.base_registers[RHD_FB_BAR]; - info.shared_info->frame_buffer_offset = 0; // Pull active monitor VESA EDID from boot loader edid1_info* edidInfo = (edid1_info*)get_boot_item(EDID_BOOT_INFO, @@ -110,9 +113,6 @@ radeon_hd_init(radeon_info &info) info.shared_info->has_edid = false; } - info.shared_info->frame_buffer_int - = read32(info.registers + R6XX_CONFIG_FB_BASE); - // Populate graphics_memory/aperture_size with KB if (info.shared_info->device_chipset >= RADEON_R800) { // R800+ has memory stored in MB @@ -143,9 +143,6 @@ radeon_hd_init(radeon_info &info) TRACE("card(%ld): Found %ld MB memory on card\n", info.id, memory_size); - TRACE("card(%ld): Frame buffer aperture internal location is %08x\n", - info.id, (unsigned int)info.shared_info->frame_buffer_int); - TRACE("card(%ld): Frame buffer aperture size is %ld MB\n", info.id, frame_buffer_size);