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ide: Remove last ide fragments.

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* Missed in previous commit.
This commit is contained in:
Alexander von Gluck IV
2017-06-28 08:51:24 -05:00
parent 7600fdd8e2
commit 402ec26eda
20 changed files with 0 additions and 4215 deletions
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headers/private/drivers/ide_adapter.h
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/*
* Copyright 2005-2007, Axel Dörfler, [email protected]. All rights reserved.
* Copyright 2002-04, Thomas Kurschel. All rights reserved.
*
* Distributed under the terms of the MIT License.
*/
#ifndef _IDE_PCI_H
#define _IDE_PCI_H
/*
IDE adapter library
Module to simplify writing an IDE adapter driver.
The interface is not very abstract, i.e. the actual driver is
free to access any controller or channel data of this library.
*/
#include <bus/PCI.h>
#include <bus/IDE.h>
#include <ide_types.h>
#include <device_manager.h>
// one Physical Region Descriptor (PRD)
// (one region must not cross 64K boundary;
// the PRD table must not cross a 64K boundary)
typedef struct prd_entry {
uint32 address; // physical address of block (must be even)
uint16 count; // size of block, 0 stands for 65536 (must be even)
uint8 res6;
LBITFIELD8_2(
res7_0 : 7,
EOT : 1 // 1 for last entry
);
} prd_entry;
// IDE bus master command register
#define IDE_BM_COMMAND_START_STOP 0x01
#define IDE_BM_COMMAND_READ_FROM_DEVICE 0x08
// IDE bus master status register
#define IDE_BM_STATUS_ACTIVE 0x01
#define IDE_BM_STATUS_ERROR 0x02
#define IDE_BM_STATUS_INTERRUPT 0x04
#define IDE_BM_STATUS_MASTER_DMA 0x20
#define IDE_BM_STATUS_SLAVE_DMA 0x40
#define IDE_BM_STATUS_SIMPLEX_DMA 0x80
// offset of bus master registers
enum {
IDE_BM_COMMAND_REG = 0,
IDE_BM_STATUS_REG = 2,
IDE_BM_PRDT_ADDRESS = 4
// offset of PRDT register; content must be dword-aligned
};
// (maximum) size of S/G table
// there are so many restrictions that we want to keep it inside one page
// to be sure that we fulfill them all
#define IDE_ADAPTER_MAX_SG_COUNT (B_PAGE_SIZE / sizeof( prd_entry ))
// channel node items
// io address of command block (uint16)
#define IDE_ADAPTER_COMMAND_BLOCK_BASE "ide_adapter/command_block_base"
// io address of control block (uint16)
#define IDE_ADAPTER_CONTROL_BLOCK_BASE "ide_adapter/control_block_base"
// interrupt number (uint8)
// can also be defined in controller node if both channels use same IRQ!
#define IDE_ADAPTER_INTNUM "ide_adapter/irq"
// 0 if primary channel, 1 if secondary channel, 2 if tertiary, ... (uint8)
#define IDE_ADAPTER_CHANNEL_INDEX "ide_adapter/channel_index"
// controller node items
// io address of bus master registers (uint16)
#define IDE_ADAPTER_BUS_MASTER_BASE "ide_adapter/bus_master_base"
// info about one channel
typedef struct ide_adapter_channel_info {
pci_device_module_info *pci;
pci_device *device;
uint16 command_block_base; // io address command block
uint16 control_block_base; // io address control block
uint16 bus_master_base;
int intnum; // interrupt number
uint32 lost; // != 0 if device got removed, i.e. if it must not
// be accessed anymore
ide_channel ideChannel;
device_node *node;
int32 (*inthand)( void *arg );
area_id prd_area;
prd_entry *prdt;
uint32 prdt_phys;
uint32 dmaing;
} ide_adapter_channel_info;
// info about controller
typedef struct ide_adapter_controller_info {
pci_device_module_info *pci;
pci_device *device;
uint16 bus_master_base;
uint32 lost; // != 0 if device got removed, i.e. if it must not
// be accessed anymore
device_node *node;
} ide_adapter_controller_info;
// interface of IDE adapter library
typedef struct {
module_info info;
void (*set_channel)(ide_adapter_channel_info *channel,
ide_channel ideChannel);
// function calls that can be forwarded from actual driver
status_t (*write_command_block_regs)(ide_adapter_channel_info *channel,
ide_task_file *tf, ide_reg_mask mask);
status_t (*read_command_block_regs)(ide_adapter_channel_info *channel,
ide_task_file *tf, ide_reg_mask mask);
uint8 (*get_altstatus) (ide_adapter_channel_info *channel);
status_t (*write_device_control) (ide_adapter_channel_info *channel, uint8 val);
status_t (*write_pio)(ide_adapter_channel_info *channel, uint16 *data, int count, bool force_16bit);
status_t (*read_pio)(ide_adapter_channel_info *channel, uint16 *data, int count, bool force_16bit);
status_t (*prepare_dma)(ide_adapter_channel_info *channel, const physical_entry *sg_list,
size_t sg_list_count, bool to_device);
status_t (*start_dma)(ide_adapter_channel_info *channel);
status_t (*finish_dma)(ide_adapter_channel_info *channel);
// default functions that should be replaced by a more specific version
// (copy them from source code of this library and modify them at will)
int32 (*inthand)(void *arg);
// functions that must be called by init/uninit etc. of channel driver
status_t (*init_channel)(device_node *node,
ide_adapter_channel_info **cookie, size_t total_data_size,
int32 (*inthand)(void *arg));
void (*uninit_channel)(ide_adapter_channel_info *channel);
void (*channel_removed)(ide_adapter_channel_info *channel);
// publish channel node
status_t (*publish_channel)(device_node *controller_node,
const char *channel_module_name, uint16 command_block_base,
uint16 control_block_base, uint8 intnum, bool can_dma,
uint8 channel_index, const char *name,
const io_resource *resources, device_node **node);
// verify channel configuration and publish node on success
status_t (*detect_channel)(pci_device_module_info *pci, pci_device *pciDevice,
device_node *controller_node, const char *channel_module_name,
bool controller_can_dma, uint16 command_block_base,
uint16 control_block_base, uint16 bus_master_base,
uint8 intnum, uint8 channel_index, const char *name,
device_node **node, bool supports_compatibility_mode);
// functions that must be called by init/uninit etc. of controller driver
status_t (*init_controller)(device_node *node,
ide_adapter_controller_info **cookie, size_t total_data_size);
void (*uninit_controller)(ide_adapter_controller_info *controller);
void (*controller_removed)(ide_adapter_controller_info *controller);
// publish controller node
status_t (*publish_controller)(device_node *parent, uint16 bus_master_base,
io_resource *resources, const char *controller_driver,
const char *controller_driver_type, const char *controller_name,
bool can_dma, bool can_cq, uint32 dma_alignment, uint32 dma_boundary,
uint32 max_sg_block_size, device_node **node);
// verify controller configuration and publish node on success
status_t (*detect_controller)(pci_device_module_info *pci, pci_device *pciDevice,
device_node *parent, uint16 bus_master_base,
const char *controller_driver, const char *controller_driver_type,
const char *controller_name, bool can_dma, bool can_cq,
uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size,
device_node **node);
// standard master probe for controller that registers controller and channel nodes
status_t (*probe_controller)(device_node *parent, const char *controller_driver,
const char *controller_driver_type, const char *controller_name,
const char *channel_module_name, bool can_dma, bool can_cq,
uint32 dma_alignment, uint32 dma_boundary, uint32 max_sg_block_size,
bool supports_compatibility_mode);
} ide_adapter_interface;
#define IDE_ADAPTER_MODULE_NAME "generic/ide_adapter/v1"
#endif /* _IDE_PCI_H */
headers/private/drivers/ide_types.h
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/*
* Copyright 2002/03, Thomas Kurschel. All rights reserved.
* Distributed under the terms of the MIT License.
*/
#ifndef __IDE_TYPES_H__
#define __IDE_TYPES_H__
#include <iovec.h>
#include <lendian_bitfield.h>
// IDE task file.
// contains the command block interpreted under different conditions with
// first byte being first command register, second byte second command register
// etc.; for lba48, registers must be written twice, therefore there
// are twice as many bytes as registers - the first eight bytes are those
// that must be written first, the second eight bytes are those that
// must be written second.
union ide_task_file {
struct {
uint8 features;
uint8 sector_count;
uint8 sector_number;
uint8 cylinder_0_7;
uint8 cylinder_8_15;
LBITFIELD8_3(
head : 4,
device : 1,
mode : 3
);
uint8 command;
} chs;
struct {
uint8 features;
uint8 sector_count;
uint8 lba_0_7;
uint8 lba_8_15;
uint8 lba_16_23;
LBITFIELD8_3(
lba_24_27 : 4,
device : 1,
mode : 3
);
uint8 command;
} lba;
struct {
LBITFIELD8_3(
dma : 1,
ovl : 1,
_0_res2 : 6
);
LBITFIELD8_2(
_1_res0 : 3,
tag : 5
);
uint8 _2_res;
uint8 byte_count_0_7;
uint8 byte_count_8_15;
LBITFIELD8_6(
lun : 3,
_5_res3 : 1,
device : 1,
_5_one5 : 1,
_5_res6 : 1,
_5_one7 : 1
);
uint8 command;
} packet;
struct {
LBITFIELD8_5(
ili : 1,
eom : 1,
abrt : 1,
_0_res3 : 1,
sense_key : 4
);
LBITFIELD8_4(
cmd_or_data : 1, // 1 - cmd, 0 - data
input_or_output : 1, // 0 - input (to device), 1 - output
release : 1,
tag : 5
);
uint8 _2_res;
uint8 byte_count_0_7;
uint8 byte_count_8_15;
LBITFIELD8_5(
_4_res0 : 4,
device : 1,
_4_obs5 : 1,
_4_res6 : 1,
_4_obs7 : 1
);
LBITFIELD8_7(
chk : 1,
_7_res1 : 2,
drq : 1,
serv : 1,
dmrd : 1,
drdy : 1,
bsy : 1
);
} packet_res;
struct {
uint8 sector_count;
LBITFIELD8_4( // only <tag> is defined for write
cmd_or_data : 1, // 1 - cmd, 0 - data
input_or_output : 1, // 0 - input (to device), 1 - output
release : 1,
tag : 5
);
uint8 lba_0_7;
uint8 lba_8_15;
uint8 lba_16_23;
LBITFIELD8_3(
lba_24_27 : 4,
device : 1,
mode : 3
);
uint8 command;
} queued;
struct {
// low order bytes
uint8 features;
uint8 sector_count_0_7;
uint8 lba_0_7;
uint8 lba_8_15;
uint8 lba_16_23;
LBITFIELD8_3(
_5low_res0 : 4,
device : 1,
mode : 3
);
uint8 command;
// high order bytes
uint8 _0high_res;
uint8 sector_count_8_15;
uint8 lba_24_31;
uint8 lba_32_39;
uint8 lba_40_47;
} lba48;
struct {
// low order bytes
uint8 sector_count_0_7;
LBITFIELD8_4(
cmd_or_data : 1, // 1 - cmd, 0 - data
input_or_output : 1, // 0 - input (to device), 1 - output
release : 1,
tag : 5
);
uint8 lba_0_7;
uint8 lba_8_15;
uint8 lba_16_23;
LBITFIELD8_3(
_5low_res0 : 4,
device : 1,
mode : 3
);
uint8 command;
// high order bytes
uint8 sector_count_8_15;
uint8 _1high_res;
uint8 lba_24_31;
uint8 lba_32_39;
uint8 lba_40_47;
} queued48;
struct {
uint8 _0_res[3];
uint8 ver; // RMSN version
LBITFIELD8_3(
pena : 1, // previously enabled
lock : 1, // capable of locking
pej : 1 // can physically eject
);
} set_MSN_res;
struct {
uint8 r[7+5];
} raw;
struct {
uint8 features;
uint8 sector_count;
uint8 sector_number;
uint8 cylinder_low;
uint8 cylinder_high;
uint8 device_head;
uint8 command;
} write;
struct {
uint8 error;
uint8 sector_count;
uint8 sector_number;
uint8 cylinder_low;
uint8 cylinder_high;
uint8 device_head;
uint8 status;
} read;
};
typedef union ide_task_file ide_task_file;
// content of "mode" field
enum {
ide_mode_chs = 5,
ide_mode_lba = 7
};
// mask for ide_task_file fields to be written
enum {
ide_mask_features = 0x01,
ide_mask_sector_count = 0x02,
// CHS
ide_mask_sector_number = 0x04,
ide_mask_cylinder_low = 0x08,
ide_mask_cylinder_high = 0x10,
// LBA
ide_mask_LBA_low = 0x04,
ide_mask_LBA_mid = 0x08,
ide_mask_LBA_high = 0x10,
// packet
ide_mask_byte_count = 0x18,
// packet and dma queued result
ide_mask_error = 0x01,
ide_mask_ireason = 0x02,
ide_mask_device_head = 0x20,
ide_mask_command = 0x40,
ide_mask_status = 0x40,
// for 48 bits, the following flags tell which registers to load twice
ide_mask_features_48 = 0x80 | ide_mask_features,
ide_mask_sector_count_48 = 0x100 | ide_mask_sector_count,
ide_mask_LBA_low_48 = 0x200 | ide_mask_LBA_low,
ide_mask_LBA_mid_48 = 0x400 | ide_mask_LBA_mid,
ide_mask_LBA_high_48 = 0x800 | ide_mask_LBA_high,
ide_mask_HOB = 0xf80
}; // ide_reg_mask
// status register
enum {
ide_status_err = 0x01, // error
ide_status_index = 0x02, // obsolete
ide_status_corr = 0x04, // obsolete
ide_status_drq = 0x08, // data request
ide_status_dsc = 0x10, // reserved
ide_status_service = 0x10, // ready to service device
ide_status_dwf = 0x20, // reserved
ide_status_dma = 0x20, // reserved
ide_status_dmrd = 0x20, // packet: DMA ready
ide_status_df = 0x20, // packet: disk failure
ide_status_drdy = 0x40, // device ready
ide_status_bsy = 0x80 // busy
}; // ide_status_mask
// device control register
enum {
// bit 0 must be zero
ide_devctrl_nien = 0x02, // disable INTRQ
ide_devctrl_srst = 0x04, // software device reset
ide_devctrl_bit3 = 0x08, // don't know, but must be set
// bits inbetween are reserved
ide_devctrl_hob = 0x80 // read high order byte (for 48-bit lba)
}; // ide_devcntrl_mask
// error register - most bits are command specific
enum {
// always used
ide_error_abrt = 0x04, // command aborted
// used for Ultra DMA modes
ide_error_icrc = 0x80, // interface CRC error
// used by reading data transfers
ide_error_unc = 0x40, // uncorrectable data error
// used by writing data transfers
ide_error_wp = 0x40, // media write protect
// used by all data transfer commands
ide_error_mc = 0x20, // medium changed
ide_error_idnf = 0x10, // CHS translation not init./ invalid CHS address
ide_error_mcr = 0x08, // media change requested
ide_error_nm = 0x02, // no media (for removable media devices)
}; // ide_error_mask
typedef struct ide_channel_info *ide_channel_cookie;
#endif /* __IDE_H__ */