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completed DMA acc for NV30 architecture, still untested. Fixed two doubled registerdefines which adress the same registers.

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11108 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2005-01-28 21:17:14 +00:00
parent a77de570a2
commit 41dde765fc
2 changed files with 47 additions and 45 deletions
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src/add-ons/accelerants/nvidia/engine/nv_acc.c
+11 -11
View File
@@ -701,7 +701,7 @@ status_t nv_acc_init()
/* activate Zcullflush(?) */ /* activate Zcullflush(?) */
ACCW(DEBUG3, (ACCR(DEBUG3) | 0x00000001)); ACCW(DEBUG3, (ACCR(DEBUG3) | 0x00000001));
/* unknown */ /* unknown */
ACCW(NV30_WHAT, (ACCR(NV30_WHAT) | 0x00040000)); ACCW(NV25_WHAT1, (ACCR(NV25_WHAT1) | 0x00040000));
} }
/*** setup screen location and pitch ***/ /*** setup screen location and pitch ***/
@@ -781,28 +781,28 @@ status_t nv_acc_init()
ACCW(NV10_FBTIL5AD, 0); ACCW(NV10_FBTIL5AD, 0);
ACCW(NV10_FBTIL6AD, 0); ACCW(NV10_FBTIL6AD, 0);
ACCW(NV10_FBTIL7AD, 0); ACCW(NV10_FBTIL7AD, 0);
/* copy tile setup stuff from 'source' to acc engine */ /* copy some RAM configuration info(?) */
if (si->ps.card_arch >= NV20A) if (si->ps.card_arch >= NV20A)
{ {
/* unknown: */
if (si->ps.card_type > NV40) if (si->ps.card_type > NV40)
{ {
ACCW(NV40P_WHAT_T0, ACCR(NV20_FBWHAT0)); ACCW(NV40P_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV40P_WHAT_T1, ACCR(NV20_FBWHAT1)); ACCW(NV40P_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));
ACCW(NV40P_WHAT_T2, ACCR(NV20_FBWHAT0)); ACCW(NV40P_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV40P_WHAT_T3, ACCR(NV20_FBWHAT1)); ACCW(NV40P_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1));
} }
else else
{ {
ACCW(NV20_WHAT_T0, ACCR(NV20_FBWHAT0)); ACCW(NV20_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV20_WHAT_T1, ACCR(NV20_FBWHAT1)); ACCW(NV20_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));
if (si->ps.card_type == NV40) if (si->ps.card_type == NV40)
{ {
ACCW(NV40_WHAT_T2, ACCR(NV20_FBWHAT0)); ACCW(NV40_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV40_WHAT_T3, ACCR(NV20_FBWHAT1)); ACCW(NV40_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1));
} }
} }
} }
/* copy tile setup stuff from 'source' to acc engine */
/* tile 0: */ /* tile 0: */
/* tile invalid, tile adress = $00000 (18bit) */ /* tile invalid, tile adress = $00000 (18bit) */
ACCW(NV10_TIL0AD, ACCR(NV10_FBTIL0AD)); ACCW(NV10_TIL0AD, ACCR(NV10_FBTIL0AD));
src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c
+36 -34
View File
@@ -467,15 +467,14 @@ status_t nv_acc_init_dma()
ACCW(NV4X_DMA_SRC, 0x00001140); ACCW(NV4X_DMA_SRC, 0x00001140);
break; break;
case NV30A: case NV30A:
/* /* init some function blocks, but most is unknown.. */
pNv->PGRAPH[0x0084/4] = 0x40108700;//acc DEBUG1 ACCW(DEBUG1, 0x40108700);
pNv->PGRAPH[0x0890/4] = 0x00140000;//0x00400890 nieuw: unknown!!<<<<<<<<(NV25) ACCW(NV25_WHAT1, 0x00140000);
pNv->PGRAPH[0x008C/4] = 0xf00e0431;//acc DEBUG3 ACCW(DEBUG3, 0xf00e0431);
pNv->PGRAPH[0x0090/4] = 0x00008000;//acc NV10_DEBUG4 ACCW(NV10_DEBUG4, 0x00008000);
pNv->PGRAPH[0x0610/4] = 0xf04b1f36;//NVACC_NV4X_WHAT2 nw, dus ook op NV30!<<< ACCW(NV25_WHAT0, 0xf04b1f36);
pNv->PGRAPH[0x0B80/4] = 0x1002d888;//0x00400b80 nieuw: unknown!!<<<<<<< ACCW(NV25_WHAT2, 0x1002d888);
pNv->PGRAPH[0x0B88/4] = 0x62ff007f;//0x00400b88 nieuw: unknown!!<<<<<<< ACCW(NV25_WHAT4, 0x62ff007f);
*/
break; break;
case NV20A: case NV20A:
/* /*
@@ -521,11 +520,11 @@ status_t nv_acc_init_dma()
{ {
if (si->ps.card_type == NV40) if (si->ps.card_type == NV40)
{ {
/* copy unknown tile setup stuff from 'source' to acc engine(?) */ /* copy some RAM configuration info(?) */
ACCW(NV20_WHAT_T0, ACCR(NV20_FBWHAT0)); ACCW(NV20_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV20_WHAT_T1, ACCR(NV20_FBWHAT1)); ACCW(NV20_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));
ACCW(NV40_WHAT_T2, ACCR(NV20_FBWHAT0)); ACCW(NV40_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV40_WHAT_T3, ACCR(NV20_FBWHAT1)); ACCW(NV40_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1));
/* setup location of active screen in framebuffer */ /* setup location of active screen in framebuffer */
ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
@@ -536,11 +535,11 @@ status_t nv_acc_init_dma()
} }
else else
{ {
/* copy unknown tile setup stuff from 'source' to acc engine(?) */ /* copy some RAM configuration info(?) */
ACCW(NV40P_WHAT_T0, ACCR(NV20_FBWHAT0)); ACCW(NV40P_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV40P_WHAT_T1, ACCR(NV20_FBWHAT1)); ACCW(NV40P_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));
ACCW(NV40P_WHAT_T2, ACCR(NV20_FBWHAT0)); ACCW(NV40P_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0));
ACCW(NV40P_WHAT_T3, ACCR(NV20_FBWHAT1)); ACCW(NV40P_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1));
/* setup location of active screen in framebuffer */ /* setup location of active screen in framebuffer */
ACCW(NV40P_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); ACCW(NV40P_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
@@ -552,22 +551,25 @@ status_t nv_acc_init_dma()
} }
else /* NV20A and NV30A: */ else /* NV20A and NV30A: */
{ {
/* /* copy some RAM configuration info(?) */
//NVACC_NV20_WHAT0 from NV20_FBWHAT0 ACCW(NV20_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0));
pNv->PGRAPH[0x09A4/4] = pNv->PFB[0x0200/4]; ACCW(NV20_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1));
//NVACC_NV20_WHAT1 from NV20_FBWHAT1 /* copy some RAM configuration info(?) to some indexed registers: */
pNv->PGRAPH[0x09A8/4] = pNv->PFB[0x0204/4]; /* b16-24 is select; b2-13 is adress in 32-bit words */
ACCW(RDI_INDEX, 0x00ea0000);
/* data is 32-bit */
ACCW(RDI_DATA, NV_REG32(NV32_PFB_CONFIG_0));
/* b16-24 is select; b2-13 is adress in 32-bit words */
ACCW(RDI_INDEX, 0x00ea0004);
/* data is 32-bit */
ACCW(RDI_DATA, NV_REG32(NV32_PFB_CONFIG_1));
pNv->PGRAPH[0x0750/4] = 0x00EA0000; /* setup location of active screen in framebuffer */
pNv->PGRAPH[0x0754/4] = pNv->PFB[0x0200/4]; ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
pNv->PGRAPH[0x0750/4] = 0x00EA0004; ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer));
pNv->PGRAPH[0x0754/4] = pNv->PFB[0x0204/4]; /* setup accesible card memory range */
ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1));
pNv->PGRAPH[0x0820/4] = 0;//NV20_OFFSET0 ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1));
pNv->PGRAPH[0x0824/4] = 0;//NV20_OFFSET1
pNv->PGRAPH[0x0864/4] = pNv->FbMapSize - 1;//NV20_BLIMIT6
pNv->PGRAPH[0x0868/4] = pNv->FbMapSize - 1;//NV20_BLIMIT7
*/
} }
/* NV20A, NV30A and NV40A: */ /* NV20A, NV30A and NV40A: */